)> Cl. Cl. ..., m V, V,

-I ..., QJ :J V, -QJ d. 0 :J

\

Main Points

• Address Translation Concept - How do we convert a virtual address to a physical

address?

• Flexible Address Translation f1..t:?z:.Mo/2_'-( I R. lz G .z: ON .s OF V ,I a.. TU AL

- Segmentation --k_ LvMPL lz ?< MF=f1 MGT

- Paging _r= L}: NS Afl.. C ()\JJ- (lA6 Sz. D ~ /J, DD f?_i;.ss

(_ - i3AD {? 0 /l.. sfAflsr'z A()O/l~SS u~AG~

~,f ~c~

- Multilevel translation

• Efficient Address Translation IS o ,H -C & p '-( o/\J W/L 2 i ~

- Translation Lookaside Buffers 5 Z-AC:: I( G (l_o~t ~l

- Virtually and physically addressed caches l. DA

O ON i) G. MANO

Address Translation Concept

Virtual Address

Mrtu

Processor l·······················>I Translation I Invalid··········• Raise . Exception

~

Data ""

Valid

~··················> Physical Address

Physical Memory

... Data

(_'[tJ fz.Arl p AC:. r-z Tl\ r'1 L fz S

Beyond Paging: Sparse Address Spaces

• Might want many separate segments

- Per-processor heaps

- Per-thread stacks

- Memory-mapped files

- Dynamically linked libraries

• What if virtual address space is large?

- 32-bits, 4KB pages=> SOOK page table entries

- 64-bits => 4 quadrillion page table entries

Multi-level Translation

• Tree of translation tables

- Paged segmentation

- Multi-level page tables

- Multi-level paged segmentation

• All have pages as lowest level; why?

· Multilevel Translation with

Pages at Lowest Level

• Efficient memory allocation (vs. segments)

• Efficient for sparse addresses (vs. 1 level paging)

• Efficient disk transfers (fixed size units)

• Easier to build translation lookaside buffers

• Efficient reverse lookup (from physical -> virtual)

• Variable granularity for protection/sharing

• Except: see discussion of superpages

Cc.)/t Si_

11Af

Paged Segmentation

• Process memory is segmented • Segment table entry:

- Pointer to page table

- Page table length {# of pages in segment) - Access permissions

• Page table entry: - Page frame - Access permissions

(~ ,,~t­

)(~ 6

-:1 '2... l:, ,-._

x 8'b < r'-:-"-+1 ~

-z_ ( ~c,.,c. (

PT)

• Share memory or set access permissions at either page or segment-level

v: r+__,_( -f,()O{l ;,-,_

Implementation ; f--I Li-; ~ t. .s Ct>~ (' t-

~ J C ~ _.,

Physical Memory

Processor )' ~( ~ ~'"3l. ~jl-

It) c.f~r

I"'""-'-( -----('11-..,

1<~ ~'

~~~ 5-f-i_c({ ~~ -Z.-

t_. -r~

.t- fe., .. /"3 Si-s.-v· Virtual

,,..- -- ~ \

\ ) ..-p_.r ~\ --

, 1 Address : \ ...----./---....----. • I I : ............ .. .................................... .. ~ Segment/ Page Offset ................................................... ..

- - (

································-:················. L. .......... .......... ....... ~ .......... ...... > Exception ...

Segme~t Table

Page Table Size c~ .............. ~-

.. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. . r:: .. ':':I. ..........

.s"~ Page Table

'

Access

Read

R/W

R/W

R/W Frame Access \ . ~

Read

..... > . Read ..

......... ..................

Physical

Address ...........

"" .. ................................. ->I Frame I Offset 1 ....... ..

............. >

\

Question

• With paged segmentation, what must be saved/restored across a process context switch?

Multi-level or hierarchical page tables

• Ex: 2-level page table - Level 1 table: each PTE

points to a page table

- Level 2 table: each PTE . points to a page

• Can share/protect/page in/out at either level 1 or level 2

L4-"~( \ t~_,t.( 't. ½ (( ~

I { 0 (0

O~'S ~+ \ (.. ~' ~~

~-z_ ~,1

Level 1 Table

. • •

~7 ~lV­,X~b

Level2 Tables

•••

?_H/3

Implementation

Processor

Virtual

Address

··>I Index 1 I Index 2 I Index 3 I Offset ]·····································: Physical j Address l

Iii

Physical Memory

Level 1

···································:·~ t-------1

Frame I Offset ] ....... ~ I I

...

Level 2 :. ·>.-------.

·················:····························> -------1

Level 3 ···•----

·························································> t---------1

x86 Multilevel Paging ,

• Omit sub-tree if no valid addresses

- Good for sparse address space

• 4KB pages

• Each level of page table fits in one page

• 32-bit: two level page table (per segment)

• 64-bit: four level page table (per segment)

x86-32 Paging 10 10 12

Virtual address

I VPN3 I VPN4 I VPO I --- , _ -·"' ,---"····,

l i

Page Page Directory Table i

' ~ PDE ~ ~ PTE • = ...• --···

CR3 · -,c=.. ...... i .

.

20 l 12 '

I PPN I PPO I cal address , .. ·- -

16 9

l VPN1 l --= - " •. - ···-··· ····-. .• - ,-;.. - -·,..;c, -- - 7 -

i

Page Map

Level4

~ PM4LE . ;

CR3

I

x86-64 Paging 9 9 9

VPN2 I VPN3 I VPN4 I. " ---- -------- - ----,------------- -----,- .,;-:-':

____ - - ,i' .. .,,_ ·-·- .. ,-.- ... -;

Page

Directory

Pointer Page Page Table Directory Table

... PDPE .. ..... PDE . ,..... PTE .

-- ' ---- ---· ~ -

-~ --

36 i 12

PPN l PPO

12 VPO

l

'

Virtual address

I ----··"···--------•----;...C,.,,,.; .. -

I

L\ '?5 b rt S o \­

v-:, tu .J A O 0) R.~ ~<;

L...i s ·. I I:. TC3 s~...rv~ 8

cal address

~l <£ b ~ 0 <?- ~k, ~~~J 4\-O0aJiSS 7-S t 1 (s

Page table entries (x86 32 bit) f"'\o O L ri ~ Ji O A cce_ s<; ( tJ .s ~ S \1-J

Empty

4KB page

0 -:£f?_TY

Ignored

Bits 31:12 of address of page frame lgn l·GI O

f '-Y? '\-r~---- 'l. t:I. l\~" ~re\

Cc_ Cl, C. ~,e. ( S/o') W i-+ ~ -ft.eo vs f

{_ I/0 ) \1/

us~ r / 5 u f<?...rv:sor

"'r ~ ( s"7" s +~,...+ (LAM

0

Pl Pl UR / /I 1

\!')

I

;Ave.(~&

\ <!.. .... ll -w r,-{ '­d\

t"'e. ~~ - 01\. \y

Page directory e .____5 (x86 32 bit) \/fl '-1, 9

Empty

4MB page

Page table

Bits 31:22 of address of 4MB page frame

Ignored

0

Bits 31:12 of address of page table

us~ Q:.:rT

6 -G,

lgn

lgn I

ol g n

0

Pl Pl UR / /I 1

cAc\--\~~ 0 '1:,S A- ~LVZ-­

c_-r:.,/ o)

~)R c--------~= ------(---/ ~,)\,'{ w r~t e.. *(bu,~

[--s/o'>

~

\)',e.,( o 90~ Dr) (,v e (t,, #., O r,1 v-z ~ ', ; ,;_ 'r~

'7) ,, ~y v

CR3 register

Virtual address

Address of PDE

PDE

Address of PTE

PTE

Physical address

Small page translation

Address of page directory SBZ

PDE index PTEindex Offset

Address of page directory

Note: addresses Page table base address in physical memory!

Page table base address

Small page base address Access control 11

Small page base address Offset

Base address

1024 entries 4kB

Page table for small pages

Page director

Translates VA[31:22]

1024 entries 4kB

Translates VA[21:12]

Page table

Page table

4kB page

4kB page

VA[ll:O] = offset in page

Question

• Write pseudo-code for translating a virtual address to a physical address for a system using 3-level paging, with 8 bits of address per level

p TI) r ADt>«. '>'> ;lLI J I p ( LA l)pe_ '>°"> ,~ g_ Ox~]

x86 Multilevel Paged Segmentation

• Global Descriptor Table (segment table)

• Each segment descriptor

- Pointer to (multilevel) page table

- Segment length

- Segment access permissions

• Context switch

- change global descriptor table register (GDTR), pointer to global descriptor table

- Side effect: invalidates TLB

Multilevel Translation

• Pros:

- Allocate/fill only page table entries that are in use

- Simple memory allocation

- Share at segment or page level

• Cons:

- Space overhead: one pointer per virtual page

- Multip·le lookups per memory reference

Page Translation in the OS

• OS's need to keep their own data structures

- List of memory objects (segments)

- Virtual page-> physical page frame

- Physical page frame-> set of virtual pages

- Keep track of copy on write, load on demand, ...

• Why not just use the hardware page tables?

Kernel Page Translation

• Kernel maintains its own page translation data structures - Portable, flexible

- Copy changes down into hardware page tables

• Example: Inverted page table - Hash from virtual page-> physical page

- Space proportional to# of physical pages

• Example: virtual/shadow page table - Linux kernel tables mirror x86 structure, even on

ARM