© imec 2006 A Scalable Programmable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio B. Bougard (presenter), D. Novo, F. Naessens,

© imec 2006

A Scalable Programmable Baseband Platform for Energy-Efficient

Reactive Software-Defined-Radio

B. Bougard (presenter), D. Novo, F. Naessens, L. Hollevoet, T. Schuster, M Glassee, A. Dejonghe, L. Van der Perre

CrownCom 2006Mykonos, Greece

June 9, 2006

© imec 2006 CONFIDENTIAL

A user’s dream:Anything, anywhere, anytime

Fixed wirelessaccess802.16

Publichot-spot802.11

OfficeWLAN802.11

Higher Rate Cellular Mobile

DVB-HDAB

Tomorrow’s

new standard

?


Today’s solution: multiple radios


All cost factors direct us towards SDRs

$ Silicon Area

$ #components

$ Volume

$ Time-to-Market

$ Various NRE

Software Defined Radio


SDR: a wireless dream come true?

SDR


Outline

Reactive SDR platform requirements

State-of-the-art

Design methodology for flexibility and low energy

Reactive radio platform architecture

Scalable platform interconnect

Reactive digital front-end

Coarse-Grain Array based baseband processor

Radio Control processor

Preliminary design results


Outline


State-of-the-art









Reactive Software defined radio: definition

Base-station SDR (90% SoA)

Terminal SDR -> hot topic

- Single-mode Terminal SDR

- Multi-mode Terminal SDR

- Mode-configurable

- Reactive radio

- Cognitive radio

Tier 1 – Software

Controlled Radio

Tier 2 – SoftwareDefined Radio

Tier 3 – Ideal

Software Radio

Tier 4 – Ultimate

Software Radio

Tier 0

Hardware Radio


Required Reactive radio platform features

Low Cost

Energy Aware Spectrum Aware

Long HW lifespan

Short SW deployment time

Scalable HW/SW

Energy scalable HW

Energy scalable algorithms

Energy scalable SW mapping

Techno-aware energy managnt

Versatile RX FE architecture

Versatile TX FE architecture

Powerful MAC/RLC/QoS Ctrl


Outline


State-of-the-art









SDR State-of-the-art: no global approach



Basebandprocessor

MPSOC

Mixed signal platform

Single thread

Static multi-thread

Dynamic multi-thread

Scope

Concurrency

Management

Mapping

productivity

Single-modereconfigurable

Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiency

[Mips/mW]

5

50

500



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiency

TI

5

50

500



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiency

Sandbridge5

50

500



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiencyICERA

5

50

500



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiency

SH5

50



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiency

EVP5

50

500



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiencySODA

5

50

500



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000Mbps

ASM

Processor C

Platform C

Energy efficiency

5

50

500



Basebandprocessor

MPSOC


Single thread

Static multi-thread


Scope

Concurrency

Management

Mapping

productivity


Reactive

multi-mode

Cognitiveradio

Performance

1-10Mbps

10-100Mbps

100-1000MbpsASM

Processor C

Platform C

Energy efficiency

Objective

5

50

500


Unique approach:Making flexibility rhyme with low-energy

Energy scalable- front-end- baseband platform- air interface algorithm- protocols

Joint quality-of-experienceand energy managementto translate energy scalability in low power operation


Outline


State-of-the-art








Opportunistic partitioning

Typical Wireless LAN: Typical Cellular scenario:

Transmit 5% Transmit .5%

Receive 5% Receive .5%

Idle/Listen 90% Idle/Listen 99%

Approach: Flexibility where needed

Ultra Low Power generic / low flexible listen/scan circuitry (Digital Front End)

Processor-based Digital Transceiver with aggressive power management

Processor power-overhead amortized by low utilization!


Systematic methodology to design energy-aware SDR platform and software

Application analysis and modeling

Platform independent optimization

Opportunisticpartitioning

Platform architecturedefinition

Inter-thread communication and RT management Interconnect refinement

Threads implementation

Cores Uarchitecturerefinement

Virtual platform modeling

SW mapping HW design


Resulting platform template

DFE tile SyncPro

DFE tile SyncPro

DFE tile SyncPro

BW optimizedscalable

interconnect

Platform &

MAC ctrl

BB engine

BB engine

FEC engine

L2 Periphand HI

‘white box’ design environment:• true ESL flow • scalable retargetable virtual platform• Smooth HW/SW co-design, verification and test flow

SDR-tuned CGA:• C compiler• high performance- power ratio • ILP vs. DLP tradeoff

Digital front end:• Solution for reactive radio • Ultra low power in standby

Scalability & Heterogeinity enabling flexibility @ low power through cross layer manager


Outline


State-of-the-art










BB1 BB2 L2 mem


ESL flow provides efficient debug/profiling/recycle environment

Coware CSCTM


Digital Front-end: Scalable autonomous detection/synchronization units

Multiple detection tiles allowing flexible support for MIMO reception and/or multi-mode scanning.

Tiles’ datapath is straight-through (no processor or controller is part of the data path).

Digital signal detection is performed in an application specific processor in each tile.

Hierarchical activation and configuration is performed by a global resource activity controller (RAC).

5mW active power per (re)active tile (CMOS90)


Hierarchical activation

Key idea: gradually enable the more power-consuming parts of the platform as the chance of a valid signal reception increases.

Probability ofsignal detection

Power consumption

off AGC Timesync

Packetdecoding

Probability ofsignal detection

Power consumption

off AGC Timesync

Packetdecoding


Synchronization Processor Micro-architecture optimized for ultra-low-power

CMOS 90 nm design

80MHz

< 0.1 mW/MHz @ 0.7V including instruction fetch and load/store


Select the right baseband processor

a tightly integrated combination of

a VLIW DSP and a Coarse Grain Array

a dedicated ISA exploited DLP (intrinsic-

controlled SIMD) a compiler to map applications described in C directly on these architectures

Baseband processing is dataflow dominated

Baseband processing is computing intensive (4 op/memory access)

Wireless requires low power

CGA provides dense interconnection network matching DF

CGA achieves very high IPC

CGA provides low power through low instruction fetch freq.

Low TTM requires programming ease


Baseband architecture: ADRES

400MHz core

200-400MHz L1

25GOPS effective

64MOPS/mW

3 mm2 (with L1)

FetchInstruction Dispatch

Instruction Decode

Central Registerfile

FU FU FU

RC RC RC

RC RC RC

RC RC RC

…

…

…

…

Support IEEE 802.11n


Outline


State-of-the-art









MAC/cognitive controller

DFE Tile

Baseband CGA Tile

Outer modem

Tile Sleep (mW) 0 0 0 0 Idle (mW) 0.5 0.2 4 1 Active (mW) 50 20 400 100 Sleep->Idle 100 microseconds Idle->active 1 microsecond

IEEE802.11n IEEE802.16e DVB-H Standby 3 mW 2 mW 10mW Active max 300mW 70mW 200mW


Conclusions

CR spectrum data mining and agile air interface requirements claim for SDR implementations

To be viable, a SDR platform must be both low cost and low power First step toward CR SDR platform: reactive radio platform Heterogeneous MPSoC is best fit approach for SDR due to variety of

task requirements. Energy-scalable design coupled with adaptive joint QoS and energy

management are the keys to bring flexibility and energy-efficiency together

We proposed a methodology to design energy-scalable SDR MPSoC architecture with balanced tradeoff between cost, energy efficiency and flexibility

We are designing such SoC targeting 802.11n, 802.16e and 3GPP-LTE standards (>100Mbps)

First results: 90 nm CMOS 2 Mgates 2-10mW standby power (when reactive to at least one air interface) <300mW average power when operating a standard


Thank you!

Documents

© imec 2006 A Scalable Programmable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio B. Bougard (presenter), D. Novo, F. Naessens,