Arquitectura mínimaIEEE Standard 1149.6:
Boundary-Scan Testing of
Advanced Digital Networks
4200-537 Porto - PORTUGAL
Tel. 351 225 081 748 / Fax: 351 225 081 443
(
[email protected] / http://www.fe.up.pt/~jmf)
Outline
AC coupling, differential signalling
1149.6: test driver and test receiver
Conclusion
Scope and objectives
Objectives
Cope with differential and/or AC-coupled interconnections, enabling
high fault coverage with minimum impact on mission logic
Reuse as much as possible IEEE 1149.1 tools (ensure compatibility
with 1149.1 / 4)
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
AC-coupling, differential signalling
TX:
RX:
1149.6 defect model
1149.6 defect model (cont.)
Testing AC-coupled / differential networks
BS cell placement has an impact on circuit performance and defect
coverage
Modified BS cells must ensure:
Signal transmission over AC-coupled nets
Logic level detection from AC test signals
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
1149.6 drivers and receivers
the AC Mode, and a test signal
suited for AC-coupled
networks is applied to the pin
A test receiver at the input cell derives logic level information
from the incoming AC / DC test signal
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
1149.6 instructions for AC-coupled differential networks
EXTEST_PULSE generates a transition even when the new test value at
the driver pin retains its previous value
EXTEST_TRAIN provides multiple additional transitions (to cope with
transient
conditions, when necessary)
Both cause the driver pins to change state at least twice in
Run-Test / Idle
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
EXTEST_PULSE
EXTEST_TRAIN
General AC pin driver
The test receiver
Extracts test data even in the presence of an unknown offset
The solution is to look for valid transitions (with a minimum
voltage swing ΔV and a maximum transition time Δt)
Single-ended signal
Operation of the test receiver
When an AC testing
transitions at the input pin
and sends the logic level information to the capture / shift stage
of the BS cell
When the current instruction is EXTEST, the test receiver sends the
input logic level to the capture / shift stage of the BS cell
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
The test receiver : transition detection and offset removal
A delay element and an hysteretic comparator
Detect input signal transitions (by comparing a signal with a
delayed version of itself)
Provide an output at standard logic levels (removing unknown
offsets)
In+:
In-:
Out:
The test receiver (AC Mode / DC Mode test receiver model)
Test receiver model supporting AC Mode (AC testing instructions)
and DC Mode (EXTEST):
or a time-decaying variant:
IEEE std 1149.6, p. 27: “two simple comparators, one to sense
rising edges and the other to sense falling edges; two VHyst
voltage sources, to set the hysteresis voltage for the comparators;
and a D-type flip-flop memory element, to hold the reconstructed
signal.”
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
Test receiver support for AC testing instructions
The output of the hysteretic comparator FF will also be as shown
when the input signal Vin decays over time
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
Test receiver support for (DC) EXTEST instruction
The delay network (RC) is replaced by a bias voltage, since
transition detection is no longer required
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
BS cell with test receiver
1149.6 std 6.2:
“When an AC testing instruction is in effect, it is the purpose of
the test receiver to reconstruct the test waveform driven by the
upstream driver when either AC- or DC-coupling is used. It does
this by reacting to the edges and not the levels of the input
waveform. When (DC) EXTEST is in effect, the test receiver behaves
as a level detector.”
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
BS cell with test receiver
(DC Mode)
1149.6 std 6.2.2.1-d): “Whenever a test receiver is operating in
the level-detection mode on an AC input pin, the test receiver
output shall be cleared of prior history on the falling edge of TCK
in the Capture-DR TAP Controller state.”
1149.6 std 6.2.2.2-a):
“the output of the test receiver is only relevant during the window
of time between the falling and rising edges of TCK in the
Capture-DR (…) state.”
A valid input (> Vbias+Vhyst or < Vbias – Vhyst) will force
the HC FF into Set or Clear; otherwise the Capt. FF state will be
retained
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
Test receiver operation
Set: Vin–Vhyst > Vbias (i.e. Vin > Vbias+Vhyst)
Clear: Vin+Vhyst < Vbias (i.e. Vin < Vbias-Vhyst)
Invalid input (within the test window): the Capture FF will retain
the current value
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
BS cell with test receiver
(AC Mode)
Valid transitions will force the HC FF into Set or Clear; if no
valid transitions occur, the Capture FF state will be
retained
1149.6 std 6.2.3.1-d): “Whenever a test receiver is operating in
the edge-detection mode on an AC input signal, the test receiver
output shall be cleared of prior history at a time between exiting
the Shift-DR TAP controller state and before entering (…) Update-DR
(…).”
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
Test receiver operation
Valid input: set / clear the HC FF
Invalid input (within the test window): the Capture FF will retain
the current value
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
*
Conclusion
Compatibility with 1149.1 enables minimal impact on 1149.1
tools
Inverted Data
