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ESD-06 硬體合成實驗 Hardware Synthesis Experiments. 陳慶瀚 機器智慧與自動化技術 (MIAT) 實驗室 國立中央大學資工系 2009 年 10 月 22 日. 實驗一:控制器硬體合成. architecture miat of g0 is signal s0,s1,s2,s3,s4 : std_logic; begin process(clk,rst) begin if rst='0' then - PowerPoint PPT Presentation
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陳慶瀚機器智慧與自動化技術 (MIAT)實驗室國立中央大學資工系2009年 10月 22日
ESD-06硬體合成實驗 Hardware Synthesis Experiments
實驗一:控制器硬體合成
library ieee;use IEEE.STD_LOGIC_1164.all; entity g0 is port( clk : in std_logic; rst : in std_logic; OK : in std_logic; L1,L2 : in std_logic; V1,V2 : out std_logic; Start_M : out std_logic; Stop_M : out std_logic);end g0;
architecture miat of g0 is signal s0,s1,s2,s3,s4 : std_logic;
begin process(clk,rst) begin if rst='0' then s0<='1'; s1<='0'; s2<='0'; s3<='0'; s4<='0'; elsif clk'event and clk='1' then if s0='1' and OK='1' then s0<='0'; s1<='1'; elsif s1='1' and L1='1' then s1<=‘0’; s2<=‘1’; s3<=‘1’; elsif s2='1' and s3='1' and L2='1' then s2<=‘0’; s3<=‘0’; s4<=‘1’; elsif s4='1' then s4<=‘0’; s0<=‘1’; end if; end if; end process; V1<=s1; Start_M<=s2; V2<=s3; Stop_M<=s4;END miat;
VHDL Sample Code
Waveform Simulation
實驗二:演算法硬體合成Sum=0; I=0;for(I=0;I<=10;I++){ Sum = Sum + I;}
0
1
2
Sum=0; i=0
Sum=Sum+i
i=i+1
i<10
i=10
實驗二:演算法硬體合成0
1
2
Sum=0; i=0
Sum=Sum+i
i=i+1
i<10
i=10
GRAFCET控制器
Datapath
模擬
實驗三: Pipelined控制器設計0 Idle
1 Initialization
S
:= 1
2 Stage Control Signal Generating
3 Pipe_Controlmodule
4 Count++5 End
S3_2S3_0
S3_1
S3_0 (Pipe_module) & (Stage Controller) & (counter)S3_1 (Pipe_module) & !(Stage Controller) & (counter)S3_2 (Pipe_module) & !(Stage Controller) & !(counter)
:= 1
:= 1:= 1
Pipelined Control Sub-Grafcet
s
3A1
30
3B1
3P1
3A2
3B2
3P2
31
BEGIN
END
c1_0
c1_1
c2_0
c2_1
s2s1
=1 =1
=1
3An
3Bn
3P3
sn
=1
cn_0
cn_1
Stage Control Signal Generation