í ô r ò ð ï > µ í ñ W Z ] µ } ( } u µ ] v P &W'users.ece.cmu.edu/~jhoe/course/ece643/F20handouts/L15.pdf · Title: Microsoft PowerPoint - L15-arch Author: jhoe Created Date:

18-643-F20-L15-S1, James C. Hoe, CMU/ECE/CALCM, ©2020

18-643 Lecture 15:Architecture of Computing FPGAs

James C. HoeDepartment of ECE

Carnegie Mellon University


Housekeeping• Your goal today: explore the question of

“architecture” for “programmable hardware”What does it even mean??

• Notices– Handout #7: lab 3, due noon, Monday, 10/26– Handout #8: paper reviews, due weekly starting 11/9– Handout #9: lab 4, look for on Friday– Midterm in class, Wed 10/28– Proposal due Friday 10/30, worth 30% of project

• Readings– ??


18-643 Review Template: Summary

• What to look for in a paper/presentation– what is the question/problem?– why is this question/problem important?– why is this question/problem hard?– what is the answer/solution offered by the paper?– what is new, novel about the answer/solution?– how does the paper argue/support the

answer/solution is correct/good?

• If you don’t know the answers, you didn’t “read” the paper, OR, the paper/presentation is bad


18-643 Review Template: Critic

• What to think about while reading– soundness: is the paper's answer/solution

correct/good? – impact: is the paper's answer/solution important?– novelty: does the paper teach something new and

not obvious? – strengths: what makes the paper standout?– weaknesses: what could be improved?

• If you don’t know the answers, you didn’t “read” the paper

Don’t accept what a paper says unless you agree

18-643-F20-L15-S5, James C. Hoe, CMU/ECE/CALCM, ©2020[https://en.wikipedia.org/wiki/Fallingwater]


We mean this “Architecture”“The term architecture is used here to describe the attributes of a system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation.”

--- Amdahl, Blaauw, Brooks, “Architecture of the IBM System/360”.Footnote explaining the 2nd word in paper abstract; 1st word is “The”.

• Concept arose with IBM 360 family of computers– separate software from hardware– separate programmers from hardware designers

• A compromise between too much vs too little– pay in cost & perf for included not needed– pay in complexity & perf for needed not included

• Must have a purpose in mind to optimize


FPGA “Architecture” Yesteryears


Was there an architecture to speak of?

I

I/O pins

programmable lookup tables (LUT) and flip-flops (FF)

aka “soft logic” or “fabric”

Inte

rcon

nect

LUT FF

programmable routingYes. Who lives above? Who lives below?What is fixed? What is the purpose?


FPGA Architectural Advances

• 1990s– fast carry– LUT RAM– block RAM

• 2000s– programmable clock

generator– PowerPC core– gigabit transceiver– multiplier and DSP splices– Ethernet and PCI-E

• 2010s– system monitor – ADC– power management– ARM cores and GPU– DRAM controller– floating point arithmetic

Who lives above? Who lives below?

What is fixed? What is the purpose?


This definitely has an architecture

[http://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html]

hard-architecture external to fabric, but

don’t overlook the Vivado-imposed AXI-

based soft-architecture


If you asked 5 years ago,

• What is FPGA architecture?

One is Xilinx, the other Intel. Which is which?


Rise of True Architecture and Divergence


Today’s FPGAs not RTL targets

[Xilinx Versal] [Intel Agilex]

[Achronix Speedster MLP]

[Xilinx Zynq]


Are They still FPGA?

• Spatial data and computenot CPU

• Highly concurrentnot multicore

• Finely controllablenot GPU

• Wire-cycle granularity actionsno software of any kind

• Reprogrammablenot ASIC


Architecture follows Purpose • FPGA vendors doing what markets want

– future “FPGA” not sea-of-gates for RTL netlist– FPGAs wanted not because can’t afford ASICs

• Purposeful architectures for targeted use/app– make select things easier/cheaper to do– be very good at what it is intended to do

• Coping with architectural divergence– soft-logic adds malleability to “architecture”– 2.5/3D integration allows specialization off a

common base– push reconvergence of abstraction up the stack


Let's talk FPGA architecture in 2020

• Who lives above?– past: “RTL jocks”– future: application developers? TensorFlow

• Who lives below?– past: circuit designers, microarchitects, CAD– future: above + library developers + systems/API

• What is fixed?– what has to be small, fast, and low power– soft-logic adds a new buffer between hard vs soft

• What is the purpose? . . . .


Applications

• Who is most desperate (value and volume) for performance under power/energy/cost/weight/... constraints, e.g.,– networking, telco– ML, data analytics– near memory/storage processing– autonomous driving, AR/VR – datacenter virtualization

• Who has the next magic algorithm if only it were faster/smaller/cheaper/lower-power, e.g., ???


Technology Underpinnings• 3D Integration

– separate hard blocks (mem, DSP, NoC?) from fabric– application-specialization die of hardened accel’tor

• Connectivity– high-speed transceivers, optical?– system interfaces (memory, storage, CC)

• High-level design (who programs? how?)– domain-specific languages and libraries– smarter/friendlier compilers– abstraction for programming ease and portability

• PR and QoS support management


Programmable HW as 3rd Paradigm in Computing


Past: Ingrained Formula of Hard vs Soft

• Do as much as possible in SW • HW where SW not good enough

No room for FPGA except as poor man’s HW

SW@CPUsmem

network

storage

video& I/O


Accelerators

Present: Emergence of FPGAs Ad Hoc

• More things SW not good enough• Neither is HW when

– functionalities not fixable at deployment – require many functionalities but never all at once

FPGA as softened HW middle ground

SW@CPUsmem FPGA

network

storage

video& I/O

FPGA

FPGA

FPGA


Future: Programmable HW 3rd Paradigm

• Where does it go?• What does it do?

– where SW not fast/efficient enough– where HW not flexible enough

• Who gets to see/program it?– staying metal (offline administered)– kernel managed library of functionalities– application-specific user programming– FPGA self-reconfigure to tune or adapt???

System device w. definite purpose & architecture, distinct from traditional FPGAs’


Reimagine “FPGAs” Fundamentally

Purpose:1. lend smarts to dumb HW2. manipulate on-the-move data3. fine-grain intervention over SW

FPGA as Data “Nexus”

in Servers

network

storage

video& I/O

Accelerators

CPUs

mem

Documents

í ô r ò ð ï > µ í ñ W Z ] µ } ( } u µ ] v P &W'users.ece.cmu.edu/~jhoe/course/ece643/F20handouts/L15.pdf · Title: Microsoft PowerPoint - L15-arch Author: jhoe Created Date: