DIAKOM · ® Triscend E5 Configurable System-on-Chip Family January, 2000 (Version 1.00) Product Description © 1998-2000 by Triscend Corporation. All rights reserved. Patents

® Triscend E5 ConfigurableSystem-on-Chip Family

January, 2000 (Version 1.00) Product Description

© 1998-2000 by Triscend Corporation. All rights reserved. Patents pending.Subject to change. Visit www.triscend.com for the latest revision of this document.Comments, questions, or suggestions on this document? Please send them to [email protected].

! Industry’s first complete ConfigurableSystem-on-Chip (CSoC)

- High-performance, industry-standard "turbo"8032 microcontroller (8051/52 compatible, 10MIPS at 40 MHz)

- Up to 64Kbytes of on-chip, dedicated systemRAM (XDATA RAM)

- Up to 3,200 Configurable System Logic (CSL)cells (roughly 40,000 gates)

- High-performance dedicated internal bus- Advanced system debug capability- Stand-alone operation from a single external

memory (code + configuration)

- Advanced four-layer metal, 0.35µ CMOS pro-cess technology, 3.3 volt with 5 volt-tolerantI/O

! Enhanced, high-performance, 8032-based"Turbo" microcontroller

- Binary- and instruction-set compatible withother 8051-and 8052-based devices

- 4 cycles per instruction byte provides up to 10MIPS performance at 40 MHz

- Configurable, extendable architecture sup-ports user-designed or library-provided pe-ripherals

- Two-channel DMA controller supporting sin-gle-clock transfers

- Programmable wait-state capability- Dual 16-bit data pointers- Three programmable 16-bit timer/counters- Programmable, full duplex asynchronous se-

rial communications port- 256-byte scratchpad RAM- Protected programmable watchdog timer

- Programmable power-down modes, includingindividual PIO options

- Separate 64K address spaces for code anddata

- 12 interrupt sources with three priority levels- Embedded debugging capabilities

! Embedded Configurable System Logic (CSL)matrix

- Fast, flexible CSL logic cells support combi-natorial logic, arithmetic, memory, sequential,and bus functions

- Up to 3,200 CSL cells per device- Easy, synchronous access to and from the

system bus- Programmable intercommunications network

between system bus, CSL cells, and pro-grammable I/O (PIO) pins

- Contention-free bi-directional bussing

! High-performance, dedicated ConfigurableSystem Interconnect (CSI) system bus

- 8-bit read and write data, 32-bit address- Up to 40 Mbytes/sec transfer rates- Simple, synchronous interface to CSL periph-

erals, seamless connection to the microcon-troller

- Multi-master bus with round-robin arbitration- Expandable to off-chip function through mem-

ory interface unit (MIU)- Flexible on-chip address decoders provide

easy access to CSL functions- Programmable wait-state support- Open standard- Forward compatible with future Triscend con-

figurable system-on-chip devices

Table 1. Triscend E5 Configurable System-on-Chip Family

Device

EmbeddedProcessor

CoreDedicatedResources

SystemRAM

ConfigurableSystem Logic

(CSL) Cells

CSIAddressSelectors

PIOPins(Max)

TE502 8Kx8 256 16 92

TE505 16Kx8 512 32 124

TE512 16Kx8 1,152 72 188

TE520 40Kx8 2,048 128 252

TE532

8032 "Turbo"

(3) 16-bit countersUSART

Watchdog timer

Interrupt controller

High-speed internal busMemory interface unit2-channel DMA controllerPower managementPower-on resetHardware breakpoint unit

JTAG port 64Kx8 3,200 200 316

http://www.triscend.com

mailto:[email protected]

Triscend E5 Configurable System-on-Chip Family

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! Enhanced programmable input/output (PIO)ports

- Up to 315 user-programmable I/O per device- Inputs, outputs, or bi-directional ports for the

microcontroller, dedicated peripherals, or pro-grammable logic peripherals

- Selectable output drive from 4 mA to 12 mA- BusMinder™ circuit provides pull-up, pull-

down, or weak-follower capability- Optional input hysteresis- Optional power-down operation, individually

selectable on every pin- Input, output and output enable flip-flops for

optimal set-up and clock-to-output perform-ance

- 5 volt tolerant inputs while operating at 3.3volts

! Memory interface unit (MIU) for flexible,glueless interface to external memory

- Direct connect interface to an external 256Kx8memory for initialization and code storage

- Expandable from 18 up to 32 address lines- Variable-speed read/write timing simplifies in-

terface design

- Access external peripherals by sharing MIUdata and address pins

! Two-channel advanced DMA controller

- Proxy bus masters for CSL “soft modules”- Up to 40 Mbytes/s transfer rate (1 byte/cycle)- Auto-initialization of channels- Multiple addressing modes- Software-initiated DMA requests- Optional interrupt at end of a transfer- Block data transfers- CRC checking- DMA channel request and acknowledge sig-

nals distributed to the CSL matrix

! Programmable power-down modes

- Selectively disable function during power-down

- Typically consumes less that 50 µA in fullpower-down mode

! On-chip oscillator, crystal oscillator ampli-fier, and clock distribution circuitry


(CSL)matrix

PIOPIOPIOPIOPIO

BusArbiter

PowerControl

Ad

dre

ss B

us

SelectorSelector

Dat

a B

us

Clock andCrystal

OscillatorControl

Power-OnReset

To external memoryfor initialization and

code storage

Configurable SystemInterconnect (CSI) bus

Configurable SystemInterconnect bus

socket

CPU

USART

WatchdogTimer

InterruptUnit

256x8RAM

Timer 0

Timer 1

Timer 2

8032 "Turbo" MCU

Selector

SelectorSelector

AddressMappers

Two-channelDMA Controller

JTAG Interface

Byte-wideSystem RAM

HardwareBreakpoint Unit

MemoryInterface Unit

Selector

PIO

PIOPIO

Figure 1. Triscend E5 Configurable System-on-Chip (CSoC) block diagram.

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! Four-pin IEEE 1149.1 JTAG interface port fordownload and debugging

- Supports SAMPLE/PRELOAD, EXTEST, IN-TEST, BYPASS, and IDCODE instructions

- 8032 reset and CSoC reset- Full access to the CSI system bus and all ad-

dressable locations

! Multiple in-system programming modes

- Unlimited, in-system programmability- Byte-wide using standard FLASH, EPROM, or

SRAM memories- Serially using serial sequential-access PROM

memories (SPROMs)

- Via JTAG using internal system RAM to storeprogram code

- 'Stealth'-mode operation from internal RAMduring battery-backed operation

! Dedicated in-system debugging, hardwarebreakpoint unit

- Two breakpoint units monitor system address,data, control, and processor instruction type

- Breakpoint indicator and control from Config-urable System Logic (CSL)

Overview

The Triscend E5 configurable system-on-chip inte-grates, on a single device, a performance-enhanced 8032 “Turbo” embedded microcontroller,a large block of SRAM, a high-speed dedicatedsystem bus, and configurable logic, intimately con-nected to the processor and system bus. The E5family is a highly integrated, fully static single-chipsystem optimized for embedded systems applica-tions. Each member of the E5 family contains anidentical microcontroller and set of dedicated re-sources, as shown in Figure 1. However, the sizeof the dedicated system RAM, the number of pro-grammable I/O (PIO) pins, and the amount of con-figurable system logic grows with the larger mem-bers of the family, as shown in Table 1.

The embedded high-performance 8032-based"Turbo" microcontroller is instruction-compatiblewith other industry-standard 8032/52-based de-vices, leveraging the vast software library for the8032 architecture. While the instruction cycle forthe original 8032 microcontroller is 12 clock cycles,the 8032 "Turbo" microcontroller provides betterperformance because each instruction cycle is onlyfour clock cycles. The result is improved perform-ance at the same clock frequency.

The 8032 "Turbo" core offers other advantagesover the original 8032. The 8032 "Turbo" MCUprovides a protected watchdog timer plus an addi-tional data pointer, easing data transfer routines.

Configurable System Interconnect (CSI) Bus

CSI Bus Sockets

Configurable System-on-ChipSystem Resources

SPISerial

Interface

Pulse-WidthModulator

8-bit UARTwith paritygeneration/detection

"Soft" modulesimplemented in the

Configurable System Logic(CSL) matrix

Figure 2. "Soft" modules are built from Configurable System Logic (CSL) resources. moduleconnects to the configurable system-on-chip system via a Configurable System Inter-connect (CSI) bus socket, providing easy “drag-and-drop” customization.


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The embedded SRAM-based Configurable SystemLogic (CSL) matrix provides "derivative on de-mand" system customization. The high-performance configurable logic architecture con-sists of a highly interconnected matrix of CSL cells.Resources within the matrix provide easy, seam-less access to and from the internal system bus.

Each CSL cell performs various potential functions,including combinatorial and sequential logic. Thecombinatorial portion performs Boolean logic op-erations, arithmetic functions, and memory. Thesequential element performs independently or intandem with the combinatorial function.

The abundant programmable input/output blocks(PIOs) provide the interface between external func-tions and the internal system bus or configurablesystem logic. Each PIO offers advanced I/O op-tions including selectable output drive current, op-tional input hysteresis, and programmable low-power functionality during power-down mode.

A high-performance internal system bus—calledthe Configurable System Interconnect (CSI) bus—interconnects the microcontroller, its peripherals,and the CSL matrix. The bus provides eight bits ofread data, eight bits of write data, and a 32-bit ad-dress. Address mapping logic translates the8032's 16-bit address to the 32-bit address used bythe internal system bus.

Multiple masters arbitrate for bus access. Potentialbus masters include the 8032 "Turbo" microcon-troller, the JTAG interface, the read and writechannels of each DMA channel, and the memoryinterface unit (MIU) in some modes of operation.Functions implemented in the CSL matrix can usea DMA channel as a "proxy" master, re-using thecontrol logic already contained in the DMA chan-nels to become a master on the CSI bus.

A memory interface unit (MIU) connects the Tris-cend E5 configurable system-on-chip to externalmemory. The MIU typically connects to an externalFLASH memory device that holds the E5's initiali-zation program plus the user's code. The MIU in-terface is reusable for connections to other externalcomponents. The external read, write control, andchip-select signals are programmable providingflexible set-up, strobe, and hold timing.

The two-channel DMA controller provides high-bandwidth communication between functions, up to40 Mbytes per second. Its easy-to-use handshakesimplifies interface and control logic. Functionsfrom within the CSL matrix can request DMAtransfers, the DMA controller providing "proxy" busmastering capabilities.

A large block of fast, byte-wide SRAM providesinternal storage for temporary data storage or forcode. Though typically used for data, code can beexecuted from internal RAM, offering faster accessplus security in battery-backed applications.

TriscendConfigurable

System-on-Chip(CSoC)

TCK TMS TDI TDO

CE- OE- D[7:0] A[17:0]WE-

188

PIO

RST-

XTALIN

XTALPIO

PIO

PIO

PIO

PIOVSYS

+3.3VPIO

PIO

PIO

PIO

PIO

PIO

Up to 1

25 P

IO p

ins

in208-p

in P

QF

P p

ack

age

+3.3V16

VCC

GND28

GND

JTAG Connector

TCK TMS TDI TDO

Flash ROM256Kx8

CE- WE- OE- D[7:0] A[17:0]

SLAVE-

+3.3V

VCC

GND GND

+3.3V

GND

Figure 3. A complete Triscend E520 Configurable System-on-Chip (CSoC) design.

5 www.triscend.com

The majority of the system, including the micro-controller, operates from a single bus clock signal.Optional sources for the bus clock include driving itdirectly from an off-chip signal, connecting an ex-ternal crystal or ceramic oscillator between thededicated crystal-oscillator amplifier pins, or usingthe internal ring oscillator. Six other global buffersprovide high-fanout signals to CSL functions. Thebus clock and the global buffers can optionally bestopped upon a breakpoint event and shut off dur-ing power-down mode.

Power management control provides selectablepower-down options over internal functions. Fur-thermore, each PIO provides pin-by-pin power-down settings.

The E5 configurable system-on-chip, like other ad-vanced processors, is built from leading-edge staticCMOS technology. The E5 device is infinitely in-system programmable. A power-on reset circuitguarantees proper start-up operation after power isasserted. There are various initialization (boot-strapping) modes to support different applicationrequirements. The E5 can load itself automaticallyafter power-on from an external, byte-wide bootmemory. Optionally, the E5's configuration data isstored in a serial sequential-access PROM. In se-rial mode, the user's code is copied to and exe-cuted from the internal SRAM. Serial mode frees anumber of device pins so that they can be used asuser-defined PIO pins.

In security-conscious applications, the user's pro-gram is stored in internal RAM and battery-backedusing external circuitry. If the E5 configurablesystem-on-chip is in ‘stealth’ mode, it boots frominternal RAM when VCC is re-applied after batteryback-up. Stealth mode optionally disables theJTAG interface port and disables external fetchesvia the MIU.

An internal initialization boot ROM controls the startof initialization during power-on after the RST- pinis released. The primary purpose of the initializa-tion boot ROM is to find the user's initialization dataand code stored in the secondary boot code, usu-ally held in PROM.

Initialization programs can also be downloadeddirectly to internal SRAM through the JTAG port.Likewise, initialization programs can be written toexternal flash via JTAG through the MIU interface.

Besides downloading initialization programs, theJTAG port offers nearly full access to the micro-controller, peripherals, and CSL functions to aid indebugging. The JTAG interface can become a busmaster on the internal CSI bus. During systemdebugging, the JTAG port also sets up the internalhardware breakpoint unit.

The hardware breakpoint unit contains two func-tions that monitor the 8-bit read or write data bus,the 32-bit internal address bus, control signals andthe type of processor instruction (code or data ac-cess). Upon a predefined set of conditions, thebreakpoint unit halts execution of the applicationprogram. Via JTAG control, the user can single-step instruction execution of the processor.

Together, the 8032 "turbo" microcontroller, its dedi-cated peripherals, the on-chip RAM, the internalCSI system bus, and the CSL matrix and PIOsform a powerful, integrated, configurable system.

8032 "Turbo" Microcontroller

The Triscend E5 8032-based configurable system-on-chip is fully instruction set compatible with otherindustry-standard 8032/8051 microcontrollers. Itincludes the resources of the standard 8032 in-cluding three 16-bit timer/counters; a full-duplexserial port and twelve interrupt sources with threepriority levels.

The E5 features a performance-enhanced 8-bitCPU with a redesigned core processor, reducingunnecessary clock and memory cycles. The in-struction cycle of a standard 8032 is twelve clockcycles while the Triscend E5 reduces this to fourclock cycles for the majority of instructions, therebyimproving performance by an average of 1.5 to 3times.

This naturally speeds up the execution of the in-structions. Consequently, the E5 offers moreprocessing power compared to the original 8032,even using the same frequency crystal. For agiven throughput, the E5 can be operated from alower-frequency clock than the original 8032, re-ducing power consumption.

The E5 also provides dual Data Pointers (DPTRs)to boost block data memory transfers.

PPrrooggrraammmmaabbllee II//OO PPoorrttss

The original 8032 offers up to four 8-bit ports, atotal up to 32 lines. In the E5, the 8032 processorcore is embedded with other functions. The proc-essor optionally connects to as many PIO pins asrequired by the application.

UUAARRTT

The Triscend E5's UART is a superset of theUART in the original 8032 family, though offerstiming compatibility. The UART provides enhancedfeatures such as automatic address recognitionand frame error detection.

TTiimmeerrss

The E5's 8032-based microcontroller has three 16-bit timers that are functionally similar to the timers


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of the original 8032 family. When used as timers,they optionally operate at either 4 clocks or 12clocks per count, thus providing a mode that emu-lates the timing of the original 8032.

The E5 also features a protected watchdog timer.This timer is used as a system monitor or to time avery long period.

IInntteerrrruuppttss

The Interrupt structure in the Triscend configurablesystem-on-chip is slightly different from that of theoriginal 8032. Due to the presence of additionalfeatures and peripherals, the number of interruptsources and vectors is increased.

DDaattaa PPooiinntteerrss

The original 8032 had only one 16-bit Data Pointer(DPL, DPH). In the E5, there is an additional 16-bitData Pointer (DPL1, DPH1). This new DataPointer inhabits two previously unused SFR loca-tions in the original 8032.

PPoowweerr MMaannaaggeemmeenntt

Like the original 80C31, the E5 provides Idle andPower-Down modes of operation. Idle mode stopsthe MCU while the timers, serial port and interruptblock continues to operate. Power-Down mode

optionally stops all the clocks and completely haltschip operation, the lowest power-consumptionstate.

PPoowweerr--OOnn rreesseett

The Triscend configurable system-on-chip has anon-chip Power-On Reset facility. This eliminatesthe external capacitor-resistor network required inoriginal 8032 designs.

DMA Controller

The Triscend E5's direct memory access (DMA)controller contains two independent channels.Each channel is autonomous from the 8032 micro-controller, freeing the processor from mundane,performance-stealing, data transfer operations.Each channel is designed to transfer a byte of dataon each clock cycle, maximizing the data transferbandwidth. Several different data transfer modesare available including those between memory anda device, in any direction. A device associates it-self with a particular channel through a DMA con-trol register (DMACTRL), which contains a requestand acknowledge signal pair. The two DMA chan-nels can also be paired to perform memory-to-memory operations.

Control Logic

DMA Channel 0 DMA Channel 1

FIFOFIFOFIFOFIFO

CRC

Address Bus and Data Write Bus

Data Read Bus

PendingRequestsCounter

TransferCounterAddressCounter

Bus Request/Grant Bus Request/Grant

Figure 4. Block diagram of the embedded two-channel DMA controller.

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The main features of the DMA controller unit are:

! Two independent channels for device or mem-ory transfers

! Transfer rates up to 40 Mbytes/sec

! Auto-initialization of channels

! Programmable transfer parameters

! Multiple addressing modes

! Interrupt capabilities

! Memory-to-memory transfers capabilities

! Block transfers

! Software-initiated DMA requests

! Four-byte FIFO

! Asynchronous request/acknowledge handshake

! CRC on DMA data stream

FFuunnccttiioonnaall DDeessccrriippttiioonn

The DMA unit is composed of two channels asshown in Figure 4. A set of parameters defines theoperation for a specific DMA channel, including thememory starting address and starting transfercount, the direction of the transfer, and a variety ofother transfer characteristics. Each channel has itsown register set. The control logic block containsthe address counter, the current transfer count, thepending requests counter and channel controllogic. The data FIFO serves as a temporary bufferbetween the I/O device and memory. The CSI busarbiter treats each channel as independent busmasters.

DDMMAA IInniittiiaalliizzaattiioonn aanndd TTeerrmmiinnaattiioonn

The DMA channels are initialized through their pro-grammable registers. Once the transfer parame-ters have been programmed, the DMA channelmust first be enabled and the transfer initialized.Setting the EN bit in the respective DMA_CTRLx_0register enables the DMA channel. Once enabled,the DMA channel accepts requests. At that point,the DMA accept requests but cannot service them.A transfer is initialized by setting the INIT bit. Uponinitialization, the first DMA request loads the startaddress and start count into their respective count-ers. The INIT bit is reset by hardware and theDMA controller services the request. Software candetect that a transfer has been initiated when theINIT bit is cleared. The next transfer parameterscan be updated and the INIT bit set.

Requests are processed on a cycle basis. Re-quests lasting more than one clock cycle are inter-preted as multiple requests. If the DMA cannot

process all the incoming requests, a Pending Re-quest Counter keeps track of such requests. Atotal of 64K pending requests are possible. If theEN is cleared in the middle of a block transfer, anysubsequent requests are ignored by the DMA andby the pending request counter. The counters canbe read through software until it is reset. Thecounters are initialized either by the CLR bit or byenabling the DMA channel.

In case a DMA channel is not responding properly,it is possible to reset it through the CLR bit in thecontrol register. Once the CLR bit is set, the DMAchannel is in a reset state. It exits this state onlyafter the CLR bit is cleared. After a power-on resetor other system-wide reset, CLR is set.

A block transfer normally completes when thetransfer counter reaches zero. At that point, de-pending on the mode, the DMA transfer eitherstops or continues. The DMA continues with thenext block transfer if the INIT bit is set, or if con-tinuous mode is enabled. Resetting the DMA chan-nel also terminates a block transfer. The lattermethod should be used very carefully.

AAbboorrttiinngg aa DDMMAA ttrraannssffeerr

Software can cleanly abort an operation in the mid-dle of a DMA transfer. Once the user detects thatthe current DMA transfer can be aborted, the DMAchannel can be disabled cleanly by clearing the ENbit. The next step is to reset the DMA channellogic, accomplished by setting the CLR bit. Onlyone clock cycle is necessary to reset the DMAchannel logic. Once the CLR is cleared, the DMAchannel is again ready to use. Except for a fewimportant control bits (refer to the reset values ofeach field of the DMA registers), the rest of theconfiguration registers will have kept their previ-ously programmed values. By writing a few com-mand bits to the control register, the previoustransfer could be repeated.

TTrraannssffeerr hhaannddsshhaakkiinngg

The DMA controller always does the read transferfirst and stores the data into its temporary FIFO.Then it performs the write transfer.

TTrraannssffeerr MMooddeess

This section describes the basic DMA transfertypes and features. Some of these transfer modescan be combined to form more complex and pow-erful operations.

SSiinnggllee TTrraannssffeerr MMooddee

In this mode, the DMA initiates a single byte trans-fer for each request. If the requests are assertedduring every cycle, then the DMA controller at-tempts to service the requests as fast as it can.The DMA services requests until the transfer count


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reaches zero. At that point, the transfer is com-pleted. This is the default mode.

BBlloocckk TTrraannssffeerr MMooddee

In this mode, a single request initiates a transfer ofan entire block of data. Upon receiving the re-quest, the DMA controller starts transferring datauntil the transfer count reaches zero. If a requestis received at any time during the block transfer,the request is recorded in the Pending RequestsCounter. The new request is serviced at the end ofthe current block transfer.

SSooffttwwaarree RReeqquueesstt

When this mode is active, the DMA controller re-sponds to a DMA request initiated from software.Setting the SFTREQ bit in the DMA channel controlregister enables this mode. Software can then re-quest a DMA transfer. Software requests that can-not currently be served are recorded in the pendingrequest counter. A software request is cleared byhardware on the cycle following the set operation.If the software request is set while the DMA chan-nel is disabled, then the request is ignored.

SSiinnggllee IInniittiiaalliizzaattiioonn

Setting the INIT bit initializes a transfer. Upon re-ceiving the first request, the INIT bit is reset byhardware and the single, software or block transfercontinues until the transfer count reaches zero. Atthat point, the DMA controller waits for a new ini-tialization command.

CCoonnttiinnuuoouuss AAuuttoo--IInniittiiaalliizzaattiioonn

Setting the CONT initiates a transfer similar to theINIT bit, but upon completion of the current trans-fer, the DMA controller automatically reinitializes asif the INIT bit were set again. Automatic refresh ofsome external display is one potential applicationof this mode.

MMeemmoorryy--ttoo--MMeemmoorryy TTrraannssffeerr

By pairing the channels together, the DMA control-ler supports memory-to-memory transfers. Thechannel that reads the data from memory, is themaster, and the other channel, which writes thedata back into memory, is the slave. Setting thePAIR bit in the control register of both channelsenables this mode. Transfers are initiated usingthe master's control register. However, the slavechannel must be enabled and its transfer parame-ters set correctly.

LLiinnkkeedd ttrraannssffeerrss

Linked transfers are possible using a single-initialization, software block transfer. The pa-rameters of the first block transfers are pro-grammed into the appropriate control registers and

the transfer is initiated through the INIT bit and theSFTREQ bit. Once the INIT bit is cleared by hard-ware—meaning the DMA channel has initiated thetransfer—software loads the address and transfercount parameters of the next block of data. Afterloading the parameters, software sets the INIT andSFTREQ bits. Upon completion of the first blocktransfer, the DMA channel loads the new parame-ters and initiates the new transfer. Software re-peats the previous steps until it reaches the end ofthe linked list.

BBuuss AAddddrreessss GGeenneerraattiioonn

Each DMA channel generates a memory addressfor every request. The first address of a blocktransfer is the starting address, held in starting ad-dress control register. This address value is thenloaded into the current address counter upon thefirst request of a block transfer. Once the addressis broadcast to memory, it is updated for the nextrequest. The addressing option is configuredthrough two of the DMA channel's control registerbits, as shown in Table 2.

For debug purposes, the current address of a blocktransfer as well as the current count are visible tosoftware.

DDaattaa FFIIFFOO

The data FIFO serves as a temporary buffer be-tween the requesting I/O device and memory. Be-cause of the CSI bus structure and the multi-master handshaking, four locations are required.

CCRRCC FFeeaattuurree

A cyclic redundancy check (CRC) can be per-formed on a single DMA stream. The CRC logicmonitors the Data Read bus as it enters the DMA'sFIFOs. The CRC logic is shared between the twoDMA channels and is enabled for either one of thechannels by setting the CRC_EN bit in the corre-sponding DMA channel control register. A 0-to-1transition on CRC_EN resets the CRC shift-registerto zero. Once enabled, the CRC logic is activatedany time a byte of data is written into a FIFO. Oncea transfer is completed, the output of the CRCregister can be read by software, and the CRC sig-nature can be compared with the expected value.

The CRC logic uses a CRC-CCITT 16-bit divisorpolynomial, as shown in the equation below. Thealgorithm is capable of detecting any one, two oran even number of bits in error as well as a largenumber of burst errors.

X16 + X12 + X5 + 1

IInntteerrrruuppttss GGeenneerraattiioonn

The DMA controller can generate interrupts uponthe following three events.

9 www.triscend.com

Transfer terminal count: This event is generatedwhen a block transfer is complete (when thetransfer counter reaches its terminal count of 0).

Transfer Initialization: This event is generatedupon the first request of block transfer if the INITbit is set.

Pending Request Overflow: This event is gener-ated when the pending request counter overflows,indicating that the DMA controller cannot keep upwith the number of incoming requests.

The status of these events is recorded in the inter-rupt status register, independent of their corre-sponding interrupt-enable bits. The status bits arereset by software by writing a one into them. Writ-ing a zero does not affect the state of any statusbits. Some of the status bits are also cleared bysome hardware action (refer to "DMA InterruptRegister").

CCoonnffiigguurraattiioonn RReeggiisstteerrss

Each channel has a set of 21 bytes of control andstatus registers. Some registers are used to pro-gram a specific DMA channel or to query its status.

DDMMAA SSttaarrtt AAddddrreessss RReeggiisstteerr ((oonnee ppeerr cchhaannnneell))

This set of registers defines the start address ofthe DMA transfer. The register values are loadedinto the Address Counter at the beginning of atransfer.

The DMA controller operates on 32-bit physicaladdress values, whereas the microcontroller oper-ates on 16-bit logical address values. The physicaladdress for a memory location is typically assignedautomatically by the Triscend FastChip develop-ment system and included in a header file for theuser.

The values are read/writeable.

Channel 0:

DMA Source Address Channel 0 (A[7:0])

A7 A6 A5 A4 A3 A2 A1 A0

7 6 5 4 3 2 1 0

Mnemonic: DMASADR0_0 Address: FF20h


A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0



A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0



A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0


Channel 1:


A7 A6 A5 A4 A3 A2 A1 A0

7 6 5 4 3 2 1 0



A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0



A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0



A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0


DDMMAA TTrraannssffeerr CCoouunntt RReeggiisstteerr ((oonnee ppeerr cchhaannnneell))

This field specifies the byte length of the DMAtransfer. The actual value is the number ofbytes transfer minus one. This value is loadedinto the transfer counter before the transfer starts.

The values are read/writeable.

Channel 0:

DMA Transfer Count Channel 0 (CNT[7:0])

CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

7 6 5 4 3 2 1 0

Mnemonic: DMASCNT0_0 Address: FF24h



7 6 5 4 3 2 1 0

Mnemonic: DMASCNT0_1 Address: FF25hDMA Transfer Count Channel 0 (CNT[23:16])


7 6 5 4 3 2 1 0



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Channel 1:



7 6 5 4 3 2 1 0




7 6 5 4 3 2 1 0




7 6 5 4 3 2 1 0


DDMMAA CCuurrrreenntt AAddddrreessss RReeggiisstteerr ((oonnee ppeerr cchhaann--nneell))

This register and Current Count register are usedto monitor the current state of a particular DMAchannel or for debugging. This register containsthe output of the transfer address counter. Thisregister is loaded at the beginning of a transfer andis incremented or decremented at every transfer,controlled by the address mode bits ADRM1 andADRM0.

The values are read-only.

Channel 0:

DMA Current Address Channel 0 (A[7:0])

A7 A6 A5 A4 A3 A2 A1 A0

7 6 5 4 3 2 1 0

Mnemonic: DMACADR0_0 Address: FF2Bh


A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: DMACADR0_1 Address: FF2Ch


A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0

Mnemonic: DMACADR0_2 Address: FF2Dh


A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: DMACADR0_3 Address: FF2Eh

Channel 1:


A7 A6 A5 A4 A3 A2 A1 A0

7 6 5 4 3 2 1 0

Mnemonic: DMACADR1_0 Address: FF3Fh


A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: DMACADR1_1 Address: FF40h


A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0



A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0


DDMMAA CCuurrrreenntt CCoouunntt RReeggiisstteerr ((oonnee ppeerr cchhaannnneell))

This is the output of the transfer count counter. Itindicates how many bytes are left in the currenttransfer.


Channel 0:

DMA Current Count Channel 0 (CNT[7:0])


7 6 5 4 3 2 1 0

Mnemonic: DMACCNT0_0 Address: FF2Fh



7 6 5 4 3 2 1 0

Mnemonic: DMACCNT0_1 Address: FF30h



7 6 5 4 3 2 1 0


Channel 1:



7 6 5 4 3 2 1 0


11 www.triscend.com



7 6 5 4 3 2 1 0




7 6 5 4 3 2 1 0


DDMMAA CCoonnttrrooll RReeggiisstteerr ((oonnee ppeerr cchhaannnneell))

Channel 0:

W/R- PAIR BLOCK SFTREQ CONT INIT EN CLR

7 6 5 4 3 2 1 0

Mnemonic: DMACTRL0_0 Address: FF27h7 6 5 4 3 2 1 0

CRC_EN ADRM1 ADRM0Reserved

Mnemonic: DMACTRL0_1 Address: FF28h

Channel 1:

W/R- PAIR BLOCK SFTREQ CONT INIT EN CLR

7 6 5 4 3 2 1 0

Mnemonic: DMACTRL1_0 Address: FF3Bh7 6 5 4 3 2 1 0

CRC_EN ADRM1 ADRM0Reserved

Mnemonic: DMACTRL1_1 Address: FF3Ch

All values are read/writeable.

CLR, when set, disables the DMA channel andclears the transfer counter and pending requestscounter. Clearing the bit indicates that the DMAchannel is ready to operate. Cleared by reset.

EN, when set, enables the DMA request for thechannel. When this bit is set, the pending requestscounter is cleared and the DMA channel is ready toaccept requests. When this bit is cleared, incom-ing requests are ignored. Cleared by reset.

INIT, when set, initializes a DMA transfer. An ini-tialization is associated with the transfer of eachblock transfer. When this bit is set, the startingoperation values are loaded into their correspond-ing counters at the beginning of a transfer. Oncethe transfer has started, the bit is cleared by hard-ware. Software can set it again during the currentblock transfer to prepare the DMA channel for thenext block. When cleared, the DMA stops after thecurrent transfer. Cleared by reset.

CONT, when set, indicates continuous initializationmode. When set, the DMA transfer on the currentblock continues until this bit is cleared. Cleared byreset.

SFTREQ, when set, requests a software-initiatedDMA transfer. This bit is cleared by hardware onthe following clock cycle.

BLOCK, when set, indicates block request mode.When set, a complete block transfer is performedby the DMA upon receiving a single request from adevice. Unaffected by reset.

PAIR, when set in both channels, couples the twoDMA channels to perform memory-to-memorytransfers. Unaffected by reset.

W/R- indicates the direction of the DMA transfer.When set, the DMA performs a memory-to-I/Otransfer (DMA Write). When clear, the DMA per-forms an I/O-to-memory transfer (DMA Read).Unaffected by reset.

ADRM1 and ADRM0 define the transfer addressmode as shown below. Unaffected by reset.

Table 2. DMA Address Mode Settings.ADRM1 ADRM0 Mode

0 0Increment address by oneafter each byte transfer

1 0Decrement address by oneafter each byte transfer

x 1Single address transfer(address remains constant)

CRC_EN enables CRC checking. When set, thisbit activates the CRC logic. A 0-to-1 transition onthis bit resets the CRC logic to 0.

Cleared by a power-on reset or other device-widereset.

DDMMAA PPeennddiinngg RReeqquueessttss ((oonnee ppeerr cchhaannnneell))

This field indicates the number of DMA requestsyet to be serviced. Up to 64K requests can be re-ceived ahead of their corresponding acknowledge.



Channel 0:

DMA Pending Requests Channel 0 (REQ[7:0])

REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0

7 6 5 4 3 2 1 0

Mnemonic: DMAPREQ0_0 Address: FF32h



7 6 5 4 3 2 1 0



www.triscend.com 12

Channel 1:



7 6 5 4 3 2 1 0




7 6 5 4 3 2 1 0


DDMMAA IInntteerrrruupptt EEnnaabbllee RReeggiisstteerr ((oonnee ppeerr cchhaann--nneell))

The DMA interrupt register enables individual inter-rupt events for each channel.

Channel 0:

Reserved OVR_EN INIT_EN TC_EN

7 6 5 4 3 2 1 0

Mnemonic: DMAEINT0 Address: FF29h

Channel 1:

Reserved OVR_EN INIT_EN TC_EN

7 6 5 4 3 2 1 0

Mnemonic: DMAEINT1 Address: FF3Dh

All values are read/writeable.

TC_EN, when set, enables the DMA interrupt toindicate that the transfer counter reached its termi-nal count (TC).

INIT_EN, when set, enables the DMA interruptupon initialization.

OVR_EN, when set, enables the DMA interrupt toindicate that the pending requests counter ex-ceeded 64K.


DDMMAA SSttaattuuss RReeggiisstteerr ((oonnee ppeerr cchhaannnneell))

Channel 0:

OVR INIT TC

7 6 5 4 3 2 1 0

Reserved

Mnemonic: DMAINT0 Address: FF2AhChannel 1:

OVR INIT TC

7 6 5 4 3 2 1 0

Reserved

Mnemonic: DMAINT1 Address: FF3Eh

TC, when set, indicates that the transfer counterreached terminal count. This bit is cleared whenthe INIT bit is set. This bit is set by hardware andis cleared by software by writing a one. Writing a

zero has no effect. Used in conjunction withTC_EN to flag an interrupt.

INIT, when set, indicates that initialization has oc-curred. This bit is set by hardware and cleared bysoftware by writing a one. Writing a zero has noeffect. This bit is also cleared when software setsthe INIT bit in the corresponding channel's DMAcontrol register. Used in conjunction with INIT_ENto flag an interrupt.

OVR, when set, indicates that the pending requestscounter has overflowed. This bit is set by hardwareand cleared by software by writing a one. Writing azero has no effect. This bit is also cleared whenthe corresponding channel's pending requestscounter is cleared. Used in conjunction withOVR_EN to flag an interrupt.

NOTE: The OVR, INIT, and TC bits in the DMAStatus Register are cleared by writing a‘1’ to their respective bit location. Writ-ing a zero has no effect.


DDMMAA UUnniitt CCRRCC OOuuttppuutt RReeggiisstteerr

Once a transfer is completed, the output of theCRC register can be read by software, and the sig-nature can be compared with the expected value.

DMA CRC Register (CRC[7:0])

CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0

7 6 5 4 3 2 1 0

Mnemonic: DMACRC_0 Address: FF48h

DMA CRC Register (CRC[15:8])

CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8

7 6 5 4 3 2 1 0

Mnemonic: DMACRC_1 Address: FF49h

This register is shared by both DMA channels.


IInntteerrffaacciinngg CCSSLL PPeerriipphheerraallss ttoo tthhee DDMMAA CCoonn--ttrroolllleerr

"Soft" modules implemented in the ConfigurableSystem Logic matrix, have full access to DMAservices. Access is provided via distributed DMAcontrol registers that steer DMA requests from pe-ripherals to the appropriate DMA channel and steerthe appropriate DMA channel acknowledge signalback to the peripheral, as shown in Figure 5.

13 www.triscend.com

REQSEL


DM

A C

on

tro

l Reg

iste

r

ACKSEL

DMAChannel 1

Request

Acknowledge

DMAChannel 0

Request

Acknowledge

Figure 5. DMA Control Registers steer controlsignals from CSL “soft” modules tothe DMA channels.

DMA control registers share the same program-mable address selector functions also used for ad-dress decoding and chip selects. See Table 3 forthe number of selectors available in each device.

The address location to which a DMA control reg-ister responds is programmable. A symbolic ad-dress name for the specific DMA control register isprovided during design. The actual address as-signment is usually left to the Triscend FastChipdevelopment system. All DMA control registers aresingle-byte registers and must be located withindata or SFR memory spaces.

An individual DMA control register controls a uni-directional DMA transfer, i.e., a memory-to-I/O(DMA write) or an I/O-to-memory (DMA read)transaction. However, a DMA control register isassociated with a specific DMA channel by chang-ing the SEL bit within the control register. TwoDMA control registers are required for DMA readand DMA write operations from the same periph-eral.

A DMA control register is enabled for DMA accessby setting the ENBL bits. Until enabled, all DMArequests (REQSEL) from a DMA control registerare ignored.

In standard use, only one DMA control registershould be enabled per channel, per direction at anytime, for a maximum of four. These four controlregisters cover individual DMA read and write op-erations from both channels 0 and 1. AnotherDMA control register can be enabled via softwareafter first disabling an active control register.

DDiissttrriibbuutteedd DDMMAA CCoonnttrrooll RReeggiisstteerr

- - SEL ENBL - - SEL ENBL

7 6 5 4 3 2 1 0

Write both nibbles with duplicate data.

Read register and OR bits from each nibble.

Mnemonic: User-Defined Address: User Defined

Undefined bit locations are reserved and return 0when read.

NOTE:

The distributed DMA Control registersonly connect to either the high nibble orthe low nibble of the CSI data bus. Con-sequently, application code should writeduplicate copies of the high and low nib-ble. When reading, only the high or thelow nibble will contain valid data. Thehigh and low nibbles should be ORedtogether to determine the actual settings.

SEL steers control signals to and from the DMAcontroller. If SEL is cleared, the REQSEL inputand ACKSEL output signals are steered to DMAchannel 0. If SEL is set, then the signals aresteered to DMA channel 1. The SEL control bitmust be written to both bits 5 and 1. When read,both bits must be ORed together.

ENBL, when set, allows the CSL “soft” module toaccess the DMA controller through the REQSELinput and ACKSEL output associated with DMAControl register. When ENBL is cleared, the DMAcontroller ignores any requests from the CSL mod-ule and the CSL module ignores any DMA ac-knowledges. The ENBL control bit must be writtento both bits 4 and 0. When read, both bits must beORed together.

A DMA control register is reset to 00h by a reset.

There is unrestricted read/write access to this reg-ister.

DDMMAA RReeqquueesstt SStteeeerriinngg

To request a DMA transfer, the CSL “soft” modulefunction asserts the REQSEL input on the DMAcontrol register, as shown in Figure 6. If enabled(ENBL=1), the REQSEL signal is forwarded to ap-propriate DMA channel request, depending on theSEL value. If SEL=0, then REQSEL requestschannel 0, else REQSEL requests channel 1. Ifdisabled (ENBL=0), the request is blocked.

REQSEL

ENBLSEL


DMA Select Register

DMA0 REQ

Request toDMA Controller

DMA1 REQ

Figure 6. A DMA Control Register steers DMArequests to the appropriate channel.

DDMMAA AAcckknnoowwlleeddggee SStteeeerriinngg

Once a “soft” module requests a DMA transfer,control over the transaction shifts to the DMAchannel. The DMA channel requests the CSI bus.Once granted, the DMA channel asserts is ac-knowledge signal, which is steered back to the re-


www.triscend.com 14

questing CSL “soft” module via the ACKSEL out-put. The control logic is shown in Figure 7.

When ACKSEL is asserted High, the CSL moduleshould respond appropriately. During a DMA read(I/O-to-memory transfer), the CSL module shouldpresent data on the Data Read bus. During a DMAwrite (memory-to-I/O transfer), the CSL moduleshould accept data on the Data Write bus.

BUSCLK

D Q ACKSEL

ENBLSEL

1

0


DMA Select Register

DMA1 ACK

DMA0 ACK

Acknowledge fromDMA Controller

Figure 7. DMA acknowledge signals are steeredback to the requesting CSL “soft”module.

The requesting device has to be ready to acceptthe acknowledge signal in a single cycle, since waitstate capabilities are reserved strictly for addressedoperations. The DMA controller is designed tominimize wastes bus cycles.

EExxaammppllee DDMMAA WWrriittee TTrraannssaaccttiioonn

Figure 8 shows the waveform for a typical DMAwrite operation, i.e., a memory-to-I/O transfer.Prior to the first request, one of the DMA channelsis configured for a DMA write operation and theproper values loaded into its configuration regis-ters.

Likewise, a DMA control register—part of a CSL“soft” module function—is enabled (ENBL=1) andthe channel select bit is set to steer signals to theproper DMA channel (SEL=0 for channel 0, SEL=1for channel 1).

The remainder of the transaction is as shownFigure 8.

1. The requesting “soft” module asserts its RE-QSEL DMA request signal. Within the DMAcontrol register, this incoming request issteered to the proper DMA channel.

2. The DMA channel requests the CSI bus fromthe bus arbiter. This process may require mul-tiple clock cycles.

3. Once the bus arbiter grants the bus to the DMAcontroller, the DMA presents the transfer ad-dress, the write data, and asserts its acknowl-edge signal. Within the DMA control register,the DMA channel's acknowledge signal issteered back to the requesting CSL “soft”module function. Consequently, the ACKSELsignal is asserted, signaling the “soft” modulethat data is available. The “soft” module uses

the ACKSEL signal to enable a register andcapture the value presented on the Data Writebus.

Data Write[7:0]

AckSel

Bus Clock

ReqSel " #

$

DATA

Figure 8. Example DMA Write operation.

UUssiinngg tthhee DDMMAA CCoonnttrroolllleerr aass aa PPrrooxxyy BBuuss MMaass--tteerr

“Soft” modules implemented in the CSL matrix arebus slaves, unable to request and control the busby themselves. However, a CSL module can usethe dedicated DMA controller as a "proxy" busmaster.

A bus master requires interaction with the bus ar-biter, registers and counters to track addresses,and state machines to handle the bus transferprotocol. Such logic would consume CSL logicresources, if direct bus mastering were supported.A more efficient approach is to re-use the dedi-cated resources already built into the DMA con-troller.

The DMA controller contains the logic to arbitratefor the bus, track address, and control transfers. ACSL “soft” module uses the DMA controller as a"proxy" master, causing the DMA controller to arbi-trate for and control the bus transaction.

15 www.triscend.com

Configurable System Interconnect (CSI) Bus

The Configurable System Interconnect (CSI) bus,bridges the microcontroller to its peripherals, someimplemented in the Configurable System Logic(CSL) matrix. The CSI bus provides a processor-independent migration path to future generations ofconfigurable system-on-chip devices. User-definedand library-provided “soft” modules can be movedto future Triscend configurable system-on-chipfamilies with little or no modification

The CSI bus socket provides a simple, synchro-nous interface to functions implemented in the CSLmatrix. The CSI bus interface socket consists ofthe following signals.

! An 8-bit write data port

! An 8-bit read data port.

! A 32-bit address port.

! A set of address selector (chip select) functions.

! The bus clock.

! Wait-state control and monitor signals.

! Hardware breakpoint control and monitor sig-nals.

DDaattaa RReeaadd BBuuss

Data for the 8-bit read bus is presented by the se-lected CSL “soft” module. The read data valuesfrom all “soft” modules are OR-ed together so allunselected CSL “soft” modules should drive theread bus with all zeroes. Read data may be pre-sented during every active bus cycle.

DDaattaa WWrriittee BBuuss

The 8 data write bits are presented on the CSIsocket. Write data may be presented during everyactive bus cycle.

AAddddrreessss BBuuss

All 32 address bits are presented via the CSI in-terface socket. Typically, only a few, if any, of theaddress signals are used by functions in the CSLmatrix. Typically, the actual decoding of the ad-dress bus is performed using the address selectorresources.

AAddddrreessss SSeelleeccttoorrss

The CSI socket interface practically eliminates theneed to use any CSL matrix resources to decodebus transactions. One of the more important ele-

Data Write

Data Read

Bus Clock

BreakpointControl

Wait-StateControl

Address

Sel

ecto

rs

Co

nfi

gu

rab

le S

yste

m L

og

ic (

CS

L)

Mat

rix

8032"Turbo"

Microcontroller

Side-band Signals

CSI Socket Interface

Co

nfi

gu

rab

le S

yste

m In

terc

on

nec

t (C

SI)

Bu

s

DMA Request/Acknowledge

2-ChannelDMA Controller

HardwareBreakpoint Unit

Figure 9. The Configurable System Interconnect (CSI) bus and the socket interface to "soft"modules in the CSL matrix.


www.triscend.com 16

ments in the CSI socket interface is the program-mable address decoder function, generically calleda selector. A selector performs functions much likea chip select unit or an address decoder built in aPAL-type device.

AAddddrreessss SSeelleeccttoorr OOppeerraattiioonn

A selector detects a transaction to a specifiedrange of CSI bus addresses, including the particu-lar address space. A selector decodes the full 32-bit address bus. If a transaction is to its target ad-dress range, the selector asserts one of its outputson the same clock edge that the system provideswrite data and address, synchronized to the systemclock. This approach dramatically simplifies thelogic used to access CSL “soft” modules.

The number of available selectors depends on theparticular device. The number of selectors growswith the increasing size of the CSL matrix. There isone selector for every sixteen CSL cells, as shownin Table 3.

Table 3. Number of selectors by device.

Device SelectorsTE502 16TE505 32TE512 72TE520 128TE532 200

Functionally, each selector is similar to diagramshown in Figure 10. Each selector contains two32-bit registers that define the target address. TheMATCH0 register defines which address bits matchwhen the bit is Low. The MATCH1 register defineswhich address bits match when the bit is High. Ifthe same bit location is set in both registers, thenthe corresponding address bit is a "don't care."Table 4 provides the complete functionality.

Table 4. Function of each bitwithin a Selector.

MATCH0 MATCH1 Function0 0 No match

1 0Match if addressbit is High

0 1Match if addressbit is Low

1 1 Always match

If each address bit matches with values defined inthe MATCH0 and MATCH1 register, then the se-lector further decodes read or write operations. Ifthe address matches, and there is a read transferto this location, then the selector asserts its RDSELoutput. Likewise, if the transfer is a write, then theselector asserts its WRSEL output.

AAddddrreessss SSppeecciiffiiccaattiioonn

The MATCH0 and MATCH1 register values arecreated by the Triscend FastChip developmentsystem at design time. These register values arenot changed by application software.

The addresses loaded into MATCH0 and MATCH1are symbolically defined by the user during hard-ware design. The user specifies

! The symbolic name for the address range.This is the name used in application software torefer to the target address range.

! The size of the addressed range, which mustbe a power of two, ranging from ‘1’ indicating asingle byte to ‘16M’ indicating a 16M byte re-gion.

! The address space or spaces to which the se-lector should respond.

Match0

Match1

A31 A0

A1

A2

CSI Bus Address

RDSEL

WRSEL

READ

WRITE

BCLK

Figure 10. The distributed address selector functions decode read and write transactions to atarget address range. The selectors eliminate the need to build decoding logic usingCSL resources.

17 www.triscend.com

The Triscend FastChip development system ex-amines these settings from all of the address se-lectors defined in the hardware design. It then al-locates physical addresses to each selector. Thecorresponding 8032 logical addresses are definedand specified in a header file, used with the user’sapplication code.

The MATCH0 and MATCH1 values, defined by theTriscend FastChip development system, areloaded into the selectors during the initializationprocess. FastChip also defines the values initiallyloaded into the address mapper registers.

AAddddrreessss SSeelleeccttoorr MMooddeess

An address selector performs one of three potentialfunctions as shown in Table 5.

Table 5. Address Selector Types.

SelectModes Ports Function

RDSEL Read decodeSelector

WRSEL Write decodeRDSEL R/W- control

Chip SelectSEL Chip selectREQSEL DMA request

DMA ControlACKSEL DMA acknowledge

SSeelleeccttoorr

A selector separately decodes read and write op-erations to the target address range, as shown inFigure 10. The RDSEL output indicates a readoperation, the WRSEL output indicates a write op-eration.

A selector function is called SELECT in the designlibrary.

CChhiipp SSeelleecctt

A selector in chip select mode decodes any read orwrite transaction to the target address range, reador write. Figure 11 shows a functional drawing of achip select function. The SEL performs like a chip

select function. The RDSEL output is assertedonly during read operations.

A selector function is called CHIPSEL in the designlibrary.

DDMMAA CCoonnttrrooll

A selector provides a relocatable control registerfor CSL “soft” modules requiring DMA access. TheDMA control register enables requests and steersthe request and acknowledge signals to the se-lected DMA channel. DMA control register. Seethe "DMA Controller" section for more information.

AAddddrreessss SSppaacceess

In conjunction with the address mapper, a selectordetects transactions to a specific address space.The E5, based on a standard 8032 microcontroller,supports the following address spaces.

! Code

! Data

! SFR (Special Function Register)

EExxtteerrnnaall AAcccceessss tthhrroouugghh MMIIUU

A “soft” module can access an external device us-ing PIO pins or by re-using the pins on the memoryinterface unit (MIU). A special selector mode al-lows a “soft” module to access and handle a trans-action through the MIU.

WWaaiitt--SSttaattee MMoonniittoorr aanndd CCoonnttrrooll SSiiggnnaallss

The CSI socket interface includes signals to moni-tor and control wait-states on the internal systembus.

WWAAIITTEEDD ((oouuttppuutt ffrroomm bbuuss ssoocckkeett))

The WAITED signal indicates that a wait-state wasasserted during the previous bus cycle. This signalis typically used in control logic for functions suchas FIFOs and dual-port memory.

Match0

Match1

A31 A0

A1

A2

CSI Bus Address

READ

BCLK

RDSEL

SELWRITE

Figure 11. In chip select mode, an address selector decodes any read or write transaction to thetarget address range.


www.triscend.com 18

WWAAIITTNNEEXXTT ((iinnppuutt ttoo bbuuss ssoocckkeett))

Some CSL “soft” modules require wait-states if thethey are too slow to respond in a single bus cycle.If any wait-states are required, the initial wait-statemust be asserted using an address selector.

If a “soft” module requires more than one wait-state, it must assert the WAITNEXT signal beforethe next rising clock edge on Bus Clock. Whenasserted, the WAITNEXT signal causes a wait-state on the next bus cycle.

IInniittiiaall WWaaiitt--SSttaattee IInnsseerrttiioonn

Some “soft” modules implemented in the CSL ma-trix may require wait-states, either because the“soft” module handshakes with another asynchro-nous device or if the “soft” module is too slow torespond in a single bus cycle.

If a “soft” module requires any wait-states, a se-lector must assert the first wait-state. The selectorwill only assert a wait-state if the system is ac-cessing the selector's target address space.

Should a “soft” module require additional wait-states beyond the initial wait-state asserted by theselector, then the “soft” module indicates additionalwait-states by asserting the WAITNEXT signal onthe CSI socket interface.

BBrreeaakkppooiinntt EEvveenntt MMoonniittoorr aanndd CCoonnttrrooll SSiiggnnaallss

The CSI socket interface includes signals to moni-tor and control hardware breakpoint events. Thesesignals can be used to aid system-level debugging.

BBRREEAAKK ((iinnppuutt ttoo bbuuss ssoocckkeett))

CSL functions can force a hardware breakpointevent by asserting the BREAK signal. The hard-ware breakpoint unit typically only monitors trans-actions on the CSI bus. The BREAK signal allowsCSL functions to interact with the hardware break-point unit.

For example, a CSL function could be monitoring aserial communications stream that rarely interactswith the system bus. Upon detecting a particularpattern, the CSL function could force a breakpointevent, stopping the system. The state of the sys-tem or CSL functions could then be monitoredthrough the JTAG port.

EEVVEENNTT ((oouuttppuutt ffrroomm bbuuss ssoocckkeett))

CSL functions can monitor hardware breakpointevents using the EVENT signal. When EVENT isasserted, a hardware breakpoint event has oc-curred, either caused by the hardware breakpointevent or by another function in the CSL matrix.

CCSSII BBuuss TTrraannssaaccttiioonnss

The following section describes example CSI bustransactions, demonstrating the interaction of aCSL “soft” module and the CSI bus socket.

DDaattaa WWrriittee TTrraannssaaccttiioonnss

During a data write transaction, the system sendsdata to a CSL “soft” module. The system presentsboth write data and address.

Figure 12 shows a single-cycle write transaction toa CSL “soft” module. Write data and address arepresented on the CSI socket interface. The ad-dress is decoded using one the selector functions.If the transaction is to the address selector's tar-geted address range, then the selector asserts itsWRSEL signal. The CSL “soft” module usesWRSEL to enable a register and capture the writedata.

Bus Clock

WrSel

Data Write[7:0] DATA

Figure 12. A single-cycle write transaction to aCSL “soft” module.

Figure 13 demonstrates a similar transaction, ex-cept that the CSL “soft” module requires two clockcycles to capture the write data. The CSL “soft”module's selector is configured to assert the initialwait-state. When the selector detects that thesystem is addressing its target address range, itasserts its WRSEL signal and automatically as-serts an initial wait-state.

Seeing a wait-state during the first bus cycle, thesystem holds its Data Write and Address values.Correspondingly, the selector continues to assertits WRSEL output. Because the CSL “soft” modulewill capture the write data during the second buscycle, the “soft” module does not assert itsWAITNEXT signal to insert additional wait-states.The system, seeing no wait-states during the sec-ond bus cycle, continues on to the next bus trans-action. Consequently, the selector de-asserts itsWRSEL output after the second bus cycle.

19 www.triscend.com

Bus Clock

Waited BySelector

WrSel

DATAData Write[7:0]

Figure 13. A two-cycle write transaction to aCSL “soft” module.

DDaattaa RReeaadd TTrraannssaaccttiioonnss

During a data read transaction, the system re-ceives data from a CSL “soft” module. The systempresents both the read address and waits for theread data.

Figure 14 shows a single-cycle read transactionfrom a CSL “soft” module. The read address ispresented on the CSI socket interface. The ad-dress is decoded using one the selector functions.If the transaction is to its targeted address range,then the selector asserts its RDSEL signal. TheCSL “soft” module uses RDSEL to enable dataonto the Data Read output bus, part of the CSIsocket.

Bus Clock

RdSel

DATAData Read[7:0]

Figure 14. A single-cycle read transaction froma CSL “soft” module.

Figure 15 demonstrates a similar transaction, ex-cept that the CSL “soft” module requires two clockcycles to provide the read data. The CSL “soft”module's selector asserts the initial wait-state.When the selector detects that the system is ad-dressing its target address range, it asserts itsRDSEL signal and automatically asserts an initialwait-state.

Seeing a wait-state during the first bus cycle, thesystem holds its Address values. Correspondingly,the selector continues to assert its RDSEL output.Because the CSL “soft” module can present dataduring the second bus cycle, it does not assert itsWAITNEXT signal. The system, seeing no wait-states during the second bus cycle, continues on tothe next transaction. Consequently, the selectorde-asserts its RDSEL output after the second buscycle.

Bus Clock

Waited BySelector

RdSel

DATAData Read[7:0]

Figure 15. A two-cycle read transaction from aCSL “soft” module.

UUssiinngg WWAAIITTNNEEXXTT dduurriinngg aa ttrraannssaaccttiioonn

There are three general rules for asserting a wait-state during a bus transaction to a CSL “soft” mod-ule, depending on the “soft” module's responsetime.

1. If the “soft” module can respond within a singlebus cycle, no wait-states are inserted.

2. If the “soft” module can responds by the sec-ond bus cycle, the address selector is config-ured to insert a single wait-state.

3. If three or more bus cycles are required beforethe “soft” module can respond, an address se-lector is configured to insert the initial wait-stateand the “soft” module must assert theWAITNEXT signal to insert additional wait-states.

Figure 16 shows an example transaction where theselected “soft” module uses the WAITNEXT signalto insert wait-states. During the first bus cycle, theaddressed “soft” module's selector asserts itRDSEL output. In this example, the “soft” modulealways requires at least one wait-state, so the se-lector inserts the initial wait-state. The “soft” mod-ule is not ready to respond in the first bus cycle, sothe “soft” module asserts WAITNEXT, causing await state during the next bus cycle

During the second bus cycle, the system continuesproviding address. The selector continues assert-ing RDSEL. The “soft” module determines that itunable to respond during this cycle and continuesasserting WAITNEXT.

Finally, during the third bus cycle, the “soft” moduleis ready to respond. The “soft” module providesdata on the Read Data signals on the CSI socket.The “soft” module also de-asserts WAITNEXT,indicating that it is ready to supply data.


www.triscend.com 20

Bus Clock

RdSel

Waited BySelector By CSL

WaitNext

DATAData Read[7:0]

Figure 16. A multi-cycle transaction usingWAITNEXT to insert wait-states.

SSiiddee--bbaanndd SSiiggnnaallss

All of the signals on the CSI socket interface aredesigned to be processor independent. “Soft”modules designed using this interface can be re-used with future Triscend configurable system-on-chip families.

However, some signals are processor specific.The signals are called "side-band" signals. For theTriscend E5 family, these side-band signals include8032-specific functions.

Table 6. E5 Family Side-band Signals.

E5 Function 8032 SignalTimer 0 external input T0Timer 1 external input T1External I/O for Timer 2 T2Timer/Counter 2 capture/reloadtrigger or an additional externalinterrupt source if Timer 2 baud-rate generator unused

T2EX

External Interrupt 0 INT0External Interrupt 1 INT1High-Priority Interrupt HPINTSerial port receive data input.Used in modes 1, 2, and 3.

RXDIN

Serial port receiver output.Used in serial port mode 0 forshift clock.

RXDOUT

Serial port transmit data TXDApplication reset from CSL ma-trix (RSTC), inverted polarityfrom the original 8032

RST-

Signal from the 8032 to the CSLmatrix (CPURST). Indicatesthat the 8032 was reset for anyreason, including the watchdogtimer.

(no 8032equivalent

signal)

Output of the crystal oscillatoramplifier, distributed only to CSLfunctions.

XTAL

On a traditional 8032, some of the microcontroller'sPIO pins have shared functionality. For example,the Timer 0 External Input, T0, typically shares aPIO pin on Port 3 (P3.4). On the E5, however,these processor-specific signals can connect toany PIO pin and even to functions implementedentirely within the Configurable System Logic (CSL)matrix.

The side-band signals for the E5 CSoC devicefamily are shown in Table 6.

21 www.triscend.com

Configurable System Logic (CSL)

The Configurable System Logic (CSL) matrix pro-vides flexible, programmable resources to buildalmost any digital function. Because it is intimatelyconnected to the CSI bus, the CSL matrix is idealfor building any “soft” module functions required bythe MCU. The matrix consists of multiple CSLbanks. Each bank is a rectangular array of individ-ual CSL cells.

The number of CSL banks varies by part number.The highest-density E5 family device, the TE532,contains 25 CSL banks, arranged in a 5x5 array asshown in Figure 17 and Table 7. The smallestmember, the TE502, has just two CSL banks, ar-ranged in a 2x1 array.

TE505 (2x2)

TE512 (3x3)

TE520 (4x4)

TE532 (5x5)

TE502 (2x1)

Figure 17. The five member of the E5 CSoC devic family range in density from two CSL banks(256 CSL cells) up to 25 CSL banks (3,200 CSL cells).

Sideband Interface

CSLBank

CSLBank

CSLBank

CSLBank

CSLBank

CSLBank

CSLBank

CSLBank

CSLBank

Vertical Breakers

Horizontal Breakers

Figure 18. Vertical and horizontal breakers separate the individual CSL banks with ConfigurableSystem Interconnect (CSI) bus resources.


www.triscend.com 22

Table 7. CSL Banks by Device.

CSL BanksPartNumber Columns Rows Total

TotalCells

TE502 2 1 2 256TE505 2 2 4 512TE512 3 3 9 1,152TE520 4 4 16 2,048TE532 5 5 25 3,200

Vertical and horizontal breakers separate the indi-vidual CSL banks on a device, as shown in Figure18. Vertical breakers appear at the top of everyCSL bank. Horizontal breakers appear betweenadjacent columns of CSL banks. The breakerscontain Configurable System Interconnect (CSI)bus resources. The horizontal breakers distributeCSI bus address signals to the CSL banks. Thevertical breakers distribute the Selector input andoutput signals, breakpoint control signals, theglobal buffer signals, and the wait-state control sig-nals. The CSI read data return path is also locatedin the vertical breakers.

Signals from one CSL bank can cross into otherbanks via the breakers, though crossing a breakeradds delay to the signal.

Sideband signals originate and terminate in re-sources along the top edge of the device.

BBaannkk RReessoouurrcceess

Each CSL bank consists of 8 columns by 16 rowsof CSL cells, totaling 128 CSL cells per bank.Figure 19 shows the basic layout of the cells withina bank. Pairs of adjacent CSL cells share re-sources to build more complex cell functions. Theaddress selectors, located in the vertical breakerabove the bank, distribute any decoded address.There is one address selector per column of 16CSL cells.

Programmable interconnect surrounds the CSLcells. These programmable "wires" allow a signaloriginating from one CSL to communicate with oneor more CSL cells, even those in other CSL banks.Likewise, signals to and from the CSI bus are dis-tributed to and from individual CSL cells.

CSL Bank

Selectors

VerticalBreaker

AdjacentCSL Cells

Figure 19. A CSL bank consists of 8 columns by 16 rows of CSL cells, a 128 in total.

23 www.triscend.com

RoutingMatrix

RoutingMatrix

RoutingMatrix

RoutingMatrix

CSL Cell

CSL Cell

8 Short Segments

8 Short Segments

8 S

ho

rt S

egm

ents

8 S

ho

rt S

egm

ents

8 L

on

g L

ines

4 C

lock

/Glo

bal

Bu

ffer

s

4 C

lock

/Glo

bal

Bu

ffer

s

8 L

on

g L

ines

4 Clock/Global Buffer

8 Long Lines

Selector outputsfrom vertical breaker

Selector outputsfrom vertical breaker

Add

ress

out

puts

from

horiz

onta

l bre

ake

r

Carry,cascadedwide functionpath

Carry,cascadedwide functionpath

Figure 20. The general-purpose interconnect surrounds a pair of adjacent CSL cells.

RoutingMatrix

RoutingMatrix

RoutingMatrix

RoutingMatrix

CSL Cell

CSL Cell

8 Short Segments

8 Short Segments

8 S

ho

rt S

egm

ents

8 S

ho

rt S

egm

ents

8 L

on

g L

ines

4 C

lock

/Glo

bal

Bu

ffer

s

4 C

lock

/Glo

bal

Bu

ffer

s

8 L

on

g L

ines

CS

I Dat

a W

rite

CS

I Dat

a W

rite4 Clock/Global Buffer

OR

OR

CS

I Dat

a R

ead

8 Long Lines

4 Mux Chains

4 Mux Chains

Figure 21. CSI bus write data is available at each routing matrix. Read data returns to the CSI bus.


www.triscend.com 24

GGeenneerraall--ppuurrppoossee IInntteerrccoonnnneecctt

The general-purpose interconnect, shown in Figure20, distributes signals within a CSL bank. Metallines of various lengths and purposes connect toindividual CSL cells, to the horizontal and verticalbreakers, and to the distributed array of routingmatrices. Each routing matrix provides connec-tions between the various lines entering or exitingthe segment. The various interconnect resourcesare described below.

! 8 Short Segment lines in each vertical andhorizontal channel.

! 8 Long Lines in each vertical and horizontalchannel. These long lines traverse the width orbreadth of the CSL bank. The vertical long linesoptionally distribute the outputs from the Selec-tors located in the vertical breaker. The hori-zontal long lines optionally distribute addresssignals from CSI bus.

! Bus clock and 3 of 6 global buffer signallines in every vertical channel. The bus clocksignal is distributed globally to all resources onan E5 CSoC device. Within a CSL bank, anythree of the six global buffer signals are avail-able.

BBUF0BCLKBBUF1BBUF2BBUF3

GBUF0

GBUF1

GBUF2

GBUF3

GBUF4

GBUF5

Figure 22. The bus clock signal and any 3 ofthe 6 global buffer signals are avail-able within a CSL bank.

! A carry/cascade signal between adjacent pairsof CSL cells, for faster arithmetic functions andfor wide logic functions.

CCSSII BBuuss RReeaadd aanndd WWrriittee DDaattaa DDiissttrriibbuuttiioonn

Beyond the general-purpose signals, the program-mable interconnect also distributed data signals toand from the CSI bus.

! CSI Write Data is accessible at every routingmatrix, distributed throughout the CSL bank.

! 4 Multiplexer Chains for distributing bidirec-tional data across a CSL bank. The multiplexerchains behave much like a bidirectional, three-state bus but avoids the potential data-contention problems and associated powerconsumption of a three-state bus because allsignals are unidirectional.

! CSI Read Data paths gather the values of indi-vidual data lines from throughout the device.Ultimately, all the signal return to the CSI bus.The signals from individual bit lines are gath-ered via an OR-chain.

SSiiggnnaall--FFllooww DDiirreeccttiioonnaall PPrreeffeerreenncceess

Though the interconnect was designed to minimizeany directional signal-flow preferences, there arefew biases inspired by the architecture, as shownin Figure 23.

En

able

s, C

on

tro

l

Car

ry, c

asca

de

Clo

cks

Sel

ecto

r d

eco

des

Data

CSI Address

Figure 23. The interconnect architecture in-spires a few signal-flow biases.

Clock signals prefer the vertical channels, either totake advantage of the four clock buffers availablewithin a CSL bank or the direct connections be-tween the CSL cell's clock input and the verticallong lines.

Likewise, other control signals and enable signalsprefer vertical channels. Addresses decoded usingSelectors also prefer vertical channels becausevertical long lines distribute these signals from thevertical breakers.Wide arithmetic functions or wide logic functionsbenefit from the built-in carry/wide interconnect,which prefers a vertical orientation, from bottom totop. Other orientations are possible, though withdecreased performance.

Individual CSI bus address signals are distributedusing the horizontal long lines and consequentlyprefer horizontal channels.

The multiplexer chains, designed to distribute bidi-rectional data, traverse a CSL bank horizontally.As a result, data flow prefers the horizontal chan-nels.

25 www.triscend.com

CCSSLL CCeellll CCaappaabbiilliittiieess

A CSL cell, as shown in Figure 24, consists of aflip-flop plus combinatorial functions capable ofperforming various logic, arithmetic, or memoryoperations. Both these resources operate inde-pendently or in tandem, depending on the specificfunction implemented. An individual CSL cell iscapable of implementing the following types offunctions.

! Logic

! Arithmetic

! Memory

! Bus

! Sequential

Most logic functions are implemented using theCSL cell's four-input look-up table (LUT4). Anyfour-input, single-output function fits within a singlefour-input LUT, regardless of it logical complexity.A special mode allows two adjacent CSL to imple-ment a five-input LUT (LUT5) and some logic func-tions of up to nine inputs.The shaded multiplexers in Figure 24 representdata flow options, defined by the initialization dataloaded into the device at power-on or after assert-ing the RST- pin.

LLooggiicc FFuunnccttiioonnss

In logic mode, an individual CSL cell performs avariety of combinatorial functions of the availableinputs, as shown in Table 10. A single CSL cellperforms any possible combinatorial function offour or less inputs, regardless of complexity. Like-wise, two CSL cells working in tandem implementany possible function of five inputs. Two CSL cells

also implement some functions of between six tonine inputs, with limitations. A sequence of four- orfive-input functions, chained together, create widegate functions of practically any width. The per-formance of various logic functions is shown inTable 8

Table 8. Example logic functions andtheir performance.

FunctionCSLCells

Perform-ance

Four-input XNOR 1 < 5 nsCompare two 16-bitvalues for equality(X=Y)

8 < 20 ns

AArriitthhmmeettiicc FFuunnccttiioonnss

In arithmetic mode, a CSL cell performs simplearithmetic functions such as add, subtract, or mul-tiply. Various functions, as shown in Table 11, pro-vide common structures for building adders, sub-tracters, comparators, accumulators, incrementers,decrementers, binary counters, multipliers, andother arithmetic-based operations. Table 9 showsthe performance of various arithmetic functions.

Table 9. Example arithmetic functions and theirperformance.

FunctionCSLCells

Perform-ance

16-bit binary, loadableup counter

16 > 40 MHz

16-bit ad-der/subtracter (X-Y)

16 < 25 ns

16-bit comparator(X≥Y)

16 < 25 ns

CARRY/WIDE

D

EN

Q

S/R

Q

CI

DI

I3

I2

I1

I0

EN

CK

O

I3

I2

I1

I0

O

CO

ASYNC

LUT Flip-Flop

Programmed byinitialization data

Figure 24. A basic CSL cell of both combinatorial and sequential logic.


www.triscend.com 26

Table 10. Logic functions implemented in a CSL cell.

Class FunctionCSLCells Application

f(4)Any

4-inputlogic

function

1Any combinatorial logic function with four orless inputs. Includes any mixture of AND,NAND, OR, NOR, XOR, XNOR, and INVERT.

f(5)

Any5-inputlogic

function

2Any combinatorial logic function with five in-puts. Includes any mixture of AND, NAND,OR, NOR, XOR, XNOR, and INVERT.Logic

Somefunctionsof 6 to 9inputs

2Some combinatorial logic functions of betweensix to nine inputs. Includes a mixture of AND,NAND, OR, NOR, XOR, XNOR, and INVERT.

Table 11. Arithmetic functions implemented in a CSL cell.


ADD

1

0

+

+X

Y

LD

DI

CI

CO

1

A one-bit full adder where SUM=X+Y. Theoutput of the adder can be multiplexed withanother input via the load (LD) input. Usefulfor building adders, incrementers, accumula-tors, and binary up counters.

SUB

1

0

-

+

CO

CILD

Y

X

DI

1

A one-bit full subtracter where SUM=X-Y. Theoutput of the subtracter can be multiplexedwith another input via the load (LD) input.Useful for building subtracters, decrementers,comparators, and binary down counters.

ADDSUB

±

+

CO

CISUB

Y

X

1

A one-bit full adder/subtracter whereSUM=X±Y, depending on the SUB control.The SUB input controls whether the function isX+Y or X-Y. Useful for building ad-der/subtracters, incrementer/decrementers,and binary up/down counters.

Arithmetic

MULTCO

CI

X

Y

PS

1A one-bit multiply function. By combiningMULT functions with ADD functions, largemultipliers can be created.

27 www.triscend.com

MMeemmoorryy FFuunnccttiioonnss

In memory mode, a CSL cell performs variousmemory functions, including single- and dual-ported RAM, read-only memory (ROM), and an 8-bit serial-in/serial-out shift register. The smallamount of RAM inside each CSL cell is ideal forbuilding small register files and FIFOs. Should

larger quantities of RAM be required, the E5’s largesystem RAM block provides fast and efficient stor-age.

Table 12. Memory functions implemented in a CSL cell.


RAM16x1

16x1RAMA3

A2A1A0

DIWECK

1A 16-deep by one-bit wide, clocked write, ran-dom-access memory (RAM).

RAM32x1

32x1RAM

A4A3A2A1A0

DIWECK

2A 32-deep by one-bit wide, clocked write, ran-dom-access memory (RAM).

RAMDUAL

16x1Dual-Port

RAM

CK

A3A2A1A0

DAWEA

WEBB3B2B1B0

DB

ContentionDetection

2

A 16-deep by one-bit wide, clocked write, dual-port RAM supporting simultaneous read andwrite operations from both ports. Also in-cludes write contention circuitry to detect si-multaneous write operations to the same loca-tion with different data.

ROM16x1

16x1ROM

A3A2A1A0

1A 16-deep by one-bit wide read-only memory(ROM).

ROM32x1

32x1ROM

A4A3A2A1A0

2A 32-deep by one-bit wide read-only memory(ROM).

Memory

SHIFT8

EN

A2A1A0

DISH

CK

SDI

SDO

1An 8-bit serial-in/serial-out shift register withselectable output tap and shift/load control.


www.triscend.com 28

SSiinnggllee--PPoorrtt RRAAMM ((RRAAMM1166XX11,, RRAAMM3322XX11))

As a single-port RAM, a CSL cell provides

! Four address inputs for a 16x1 RAM block, fiveaddress inputs for a 32x1 block.

! A data input

! An active-High write enable input

! An invertible write clock input

The initial contents of the RAM can be pre-definedand loaded at power-up during initialization. Allwrite operations are synchronized to the clock in-put, simplifying the timing relationship of the data,address, and write-enable signal. Also, there areno hold time requirements for any of the RAM in-puts after the active clock edge.

Read operations are asynchronous and dependonly on the address inputs.

DDuuaall--PPoorrtt RRAAMM ((RRAAMMDDUUAALL))

In dual-port RAM mode, two CSL cells provide truedual-port capabilities, supporting simultaneousread and write operations from both ports. As adual-port RAM, two CSL cells offer

! Two, four-input address input ports

! Two data input ports

! Two active-High write enable input ports

! A single shared, invertible write clock input

! A daisy-chained error monitor that detects si-multaneous write operations to the same ad-dress with different data

The initial contents of the RAM can be pre-definedand loaded at power-up during initialization. Allwrite operations are synchronized to the clock in-put, simplifying the timing relationship of the data,address, and write-enable signal. Also, there areno hold time requirements for any of the RAM in-puts after the active clock edge.

Read operations are asynchronous and dependonly on the address inputs.

RROOMM ((RROOMM1166XX11,, RROOMM3322XX11))

The ROM function is available in two versions; a16-deep by 1-bit wide ROM (ROM16X1) and a 32-deep by 1-bit ROM (ROM32X1)

A 16-deep ROM provides four address lines to ad-dress the 16 memory locations. Likewise, a 32-deep ROM provides five address lines. The valueon the address lines directly affects the outputvalue.

A 16x1 ROM consumes a single CSL cell while a32x1 requires two CSL cells operating in tandem.

The ROM's initial contents are specified in theuser's design, loaded during initialization, and can-not be changed during operation.

88--bbiitt SShhiifftt RReeggiisstteerr ((SSHHIIFFTT88))

Another operating mode offered by a CSL cell is an8-bit, serial-in/serial-out shift register. Serial dataarrives on the SDI input. When Low, the shift/loadsignal, SH, loads data on DI into the shift registerlocation specified by the address lines, A[2:0]. Allother shifting halts.

When SH is High, the SDI data is shifted in the firstregister location. Likewise, all subsequent registervalues are shifted one position toward the most-significant location (Location 7). The value in loca-tion 7 appears on the SDO output. The addresslines, A[2:0] select the register location presentedon the asynchronous output, O.

The enable signal, EN, disables all shifting andloading operations when Low.

SSeeqquueennttiiaall FFuunnccttiioonnss

Each CSL cell contains a ‘D’-type flip-flop. The flip-flop provides the following controls

! An optional active-High clock enable input

! An invertible, edge-triggered clock input

! An optional asynchronous input to preload theflip-flop to set or clear the flip-flop, defined in theuser’s design.

During the initialization process, each flip-flop isloaded with a ‘1’ or ‘0’ as defined in the design.This value is protected against potential spuriouswrites until the end of the initialization process.

Table 13. Sequential Functionality.D EN CK ASYNC Q

Duringinitialization

INITV

X X X 1 ASYNCVX 0 X 0* QD 1* % 0* D

INITV = Initial value, loaded during initialization,defined in user's design.

ASYNCV = Asynchronous preload value, definedin user's design.

0* = Active Low, default value if left unconnected

1* = Active High, default value if left unconnected

29 www.triscend.com

Programmable Input/Output (PIO) Pins

Programmable input/output blocks (PIOs) interfaceexternal package pins to internal functions such asthe microcontroller, its peripherals, and the CSLmatrix. Each PIO connects to a bonding pad,which may or may not attach to an external pack-age pin. Each PIO can be configured an input, anoutput, or a bi-directional signal, as shown inFigure 25.

CCrreeaattiinngg aa PPIIOO PPoorrtt ffoorr tthhee MMiiccrrooccoonnttrroolllleerr

Unlike the original 8032, the Triscend E5 offersnearly unparalleled I/O flexibility. Each of the con-figurable system-on-chip's PIO pins optionally con-nects to the processor via the CSI bus or worksindependently in unassociated CSL logic functions.

Connecting a group of PIOs to the processor re-quires CSI socket resources, including connectionsto the Data Read and Data Write busses, plus oneor two address selectors.

The original 8032 has up to four byte-wide pro-grammable I/O ports. The external memory inter-face typically consumes two of the 8032's ports(Ports 0 and 2), leaving just two byte-wide ports or16 individual signals. Furthermore, some port sig-nals have shared functionality. For example, theTimer 1 external input (T1) shares a Port 3 pin(P3.5) on the original 8032. Compared to othermicrocontrollers, the Triscend E5 offers nearly un-paralleled I/O capabilities.

First, the E5 has a dedicated external memory in-terface, separate from the programmable I/O ports.Furthermore, there are no shared PIO pins, unlessso specified in the users design. Consequently, an

E5 design may have as many as 315 PIO pins,depending on the device and package offering.The user determines the number of ports address-able by the processor.

Process and design technologies have advancedsignificantly since the introduction of the original8032. Consequently, the Triscend configurablesystem-on-chip family offers advanced I/O capa-bilities not found in the original 8032. These fea-tures include, power-down operation, selectabledrive strength, optional input hysteresis, program-mable three-state operation, and low-voltage op-eration.

55--VVoolltt TToolleerraanntt II//OOss

The PIOs on the Triscend E5 are fully 5-volt toler-ant even though the I/O supply voltage is 3.3 volts.This allows 5 volt signals to connect directly to theE5 inputs without damage. In addition, the 3.3-voltVCC can be applied before or after 5 volt signalsare applied to the I/Os. This makes the E5 im-mune to power supply sequencing problems.

SSttoorraaggee EElleemmeennttss

There are three storage elements in each PIO:

1. An input flip-flop/latch

2. An output flip-flop

3. An output-enable flip-flop

The functionality of each storage element is de-fined in Table 1. Note that only the input registercan be used as a latch. Each is a 'D'-type elementand all share a common clock-enable and clock

QEN

D

Flip-Flop/Latch

Input

RegisteredInput

Clock

ClockEnable

InputHysteresis

PAD

BusMinder™

DEN

QOutputEnable

DriveStrength

DEN

QOutput

Delay

Zero HoldTime

Figure 25. Programmable Input/Output block (PIO).


www.triscend.com 30

control input. An individual flip-flop is either per-manently enabled or selectively enabled using thecommon clock-enable input.

Table 14. Flip-Flop/Input Latch Operation(no optional inversions).

Mode D ClkEna Clock Q

During initializationINITVValue

D 1* % DFlip-flop

X X 0 QX 1* 1 Q

Input LatchD 1* 0 D

Both X 0 X Q

X = don’t care

1* = logic High (default value)

%= rising clock edge (no clock inversions)

INITV = preloaded initialization value defined inuser’s design

The polarity of the common clock signal is individ-ual controlled for each flip-flop within a PIO.

A user-defined initial value of a register is loadedduring the configuration process.

PPIIOO IInnppuutt SSiiddee

Input signals flow into the device through twopaths, labeled FA and QA. FA is a direct logicalinput while QA is a registered input programmed aseither an edge-triggered flip-flop or a level-sensitivelatch.

OOppttiioonnaall IInnppuutt SSwwiittcchhiinngg HHyysstteerreessiiss

Each PIO input has optional input hysteresis.When enabled, there is about ±150mV of hystere-sis, centered around the input switching voltage,based on the I/O supply voltage (VIO).

RReeggiisstteerreedd IInnppuutt

QA is the registered input. Unlike the other storageelements, the input register can be configured ei-ther as an edge-triggered flip-flop or as a level-sensitive latch as shown in Table 1.

GGuuaarraanntteeeedd ZZeerroo HHoolldd TTiimmee oonn IInnppuutt RReeggiisstteerr

The data input to the input register can optionallybe delayed by several nanoseconds. With the de-lay enabled, the setup time of the input flip-flop isincreased to negate the clock distribution delay.This guarantees that the input register hold time isalways zero or negative, never a positive hold time.A positive hold time requirement could lead to un-reliable, temperature- or processing-dependentoperation.

The delay guarantees a zero hold time with respectto the clock provides by the bus clock buffer.

PPIIOO OOuuttppuutt SSiiddee

Output signals can be optionally inverted within thePIO, and can pass directly to the pad or be storedin an edge-triggered output flip-flop.

A logical Low on the Output-Enable signal forcesthe output into a high-impedance state. Conse-quently, a PIO functions as a three-state output orbi-directional I/O. Conversely, a logical High en-ables the output buffer. Under configuration con-trol, the Output and Output-Enable signals can beinverted. The polarity of these signals is independ-ently configured for each PIO. In addition, eachcan be tied High or Low independently.

The outputs on each PIO are full CMOS outputs.The switching threshold is a product of the I/Osupply voltage (VIO).

Although the E5’s output supply is 3.3 volts, eachoutput is capable of driving a standard 5-volt TTLoutput levels. Most 5-volt CMOS devices recog-nize HCT (TTL level) inputs.

An output can be configured as open-drain (open-collector) by tying the output path to ground anddriving the output-enabled signal, OE. However,the voltage applied to the pin should never exceedthe values defined for VIO.

SSeelleeccttaabbllee OOuuttppuutt DDrriivvee CCuurrrreenntt

Each PIO has selectable output drive current, ei-ther 4 mA or 12 mA. Reduced drive current resultsin lower power consumption, lower EMI emissionsand lower ground bounce.

OOtthheerr PPIIOO OOppttiioonnss

There are a number of other programmable op-tions available for PIO blocks.

BBuussMMiinnddeerr™™

The BusMinder feature allows each PIO to have anoptional

! Pull-up resistor (pulls undriven inputs High)

! Pull-down resistor (pulls undriven inputs Low)

! Weak follower (forces undriven inputs to the lastvalue that appeared on the bus)

Triscend E5 configurable system-on-chip devicesare fabricated on leading-edge CMOS processes.Like all CMOS devices, input pins should never beleft floating. An unused input might float unlesstied to High or Low. In addition, an input connectedto a bi-directional bus might float if the bus is three-stated (high impedance).

The BusMinder’s programmable pull-up/pull-downresistor and weak follower are useful for tying un-used or floating pins High or Low to minimizepower consumption and reduce noise sensitivity.

31 www.triscend.com

The configurable pull-up resistor is a p-channeltransistor that pulls to VCC. The configurable pull-down resistor is an n-channel transistor that pulls toGround. The value of these resistors is 50 kΩ to100 kΩ. This high value makes them unsuitable aswired-AND pull-up resistors.

The pull-up resistors for PIOs are active during theinitialization process. This pulls all as-yet-unprogrammed PIOs High, preventing them fromfloating. Devices connected to the PIO see a logi-cal One. Other devices driving into the PIO caneasily overdrive the weak pull-up resistor.

After initialization, voltage levels of unused pads,bonded or unbonded, must be valid logic levels, toreduce noise sensitivity and avoid excess current.Therefore, by default, unused pads are configuredwith the internal pull-up resistor active.

The weak follower is used on PIOs that connect toa bi-directional bus. Instead of pulling the floatinginput High or Low, the weak follower remembersthe last value that appeared on the bus before thebus signal was three-stated.

LLooww--PPoowweerr MMooddee

The Triscend E5 device can be placed into power-down mode by setting the PD bit (PCON.1) in thePower Control register. While in power-downmode, each PIO pin can optionally be configuredfor low-power operation. The PIO bit (PWDSEL.5)bit must be set before entering power-down modeto enable low-power mode.

OOuuttppuutt OOppttiioonnss

If enabled for low-power operation, a PIO output isdisabled during power-down mode. A disabled PIOoutput is forced into a high-impedance state. TheBusMinder function switches to weak followermode, regardless if configured for a pull-up or pull-down resistor or left floating. The weak followerfunction keeps the PIO at the voltage level last ap-plied to the pin. This helps to reduce overall powerconsumption.

IInnppuutt OOppttiioonnss

Likewise, a PIO input can be enabled for low-poweroperation. A PIO input is optionally forced Highduring power-down mode.

JJTTAAGG SSuuppppoorrtt

Embedded logic attached to the PIOs contains teststructures compatible with IEEE Standard 1149.1for boundary-scan testing, permitting easy chip andboard-level testing.

DDeeffaauulltt,, UUnnccoonnffiigguurreedd SSttaattee

Before configuration, all PIO pins function via theJTAG interface but with the following default condi-tions:

! The input hysteresis is turned on

! The output drive is 4 mA

! The BusMinder is a pull-up resistor

DDeeffaauulltt,, CCoonnffiigguurreedd SSttaattee

All unused but configured PIO blocks are pro-grammed as inputs with the soft BusMinder’s pull-up resistor enabled. This prevents unused PIOpins from floating.

EElleeccttrroo--ssttaattiicc DDiisscchhaarrggee ((EESSDD)) PPrrootteeccttiioonn

Each PIO has built-in ESD protection capable ofprotecting against a minimum discharge of 2,000volts, using the human body model.


www.triscend.com 32

Memory Interface Unit

The Memory Interface Unit (MIU) provides a flexi-ble, glueless interface between the E5 configurablesystem-on-chip and external memory, as shown inFigure 26. The MIU primarily provides access toan external memory device—typically a 256Kx8Flash PROM—which contains the E5's initializationdata and the user's program code. Other types ofmemory, such as static RAM or EPROM, can sub-stitute for the Flash PROM because the controlsignals are identical.

The MIU serves two purposes. First, it replacesthe original 8032's multiplexed address and dataports that consumed the 8032's port 0 and port 2.Instead, the MIU provides a more flexible demulti-plexed address and data bus. Second, it providesa convenient port for accessing external functionsfrom other peripheral functions, including the Con-figurable System Logic (CSL) matrix.

As shown in Figure 26, the MIU provides a directconnection between the 8032 microcontroller andthe external memory. By bypassing the internalCSI bus, the Triscend E5 maintains timing com-patibility with the original 8032 implementation.

The external memory timing is variable allowing theE5 to optimize or slow down accesses to fit theparticular AC characteristics of different memorydevices. The MIU can also interface with an exter-nal serial sequential-access PROM memory, simi-lar to those used to configure SRAM-based field-programmable gate arrays.

The address, data, and control pins of the MIU arealso controllable from other peripheral functions,including the Configurable System Logic (CSL)matrix, allowing access to external peripherals or

memory devices. The MIU requires minimal hand-shaking logic from within the CSL matrix.

The main features of the memory interface unitare:

! Support for a standard 256Kx8 external memoryinterface

! Support for expansion up to 4Gx8 of externalmemory through PIOs

! Programmable read and write timing control

! Bypass mode to support direct access by the8032 core

! External serial memory support

! Multi-chip expansion capabilities

FFuunnccttiioonnaall DDeessccrriippttiioonn

The MIU provides the interface between the inter-nal CSI bus and external memory. The MIUmonitors the internal bus to determine when exter-nal memory is accessed. During an external ac-cess, the MIU controls external memory and gen-erates the appropriate read, write, and enablestrobe signals.

The MIU interface timing is programmable. Threebits define the timing of each portion of externalcycles. Read cycles are split into two sections, asetup and an active portion, as shown in Figure 27.In order to support one cycle reads, the minimumsetup and width values are respectively 0 and 1.The leading edge of OE- is generated off the fallingedge of the clock. The trailing edge of OE- is gen-erated from the rising edge of the clock. In a one

Data Write

8032"Turbo"

Microcontroller

Address

Data Read

MemoryInterface

Unit

(MIU)

OtherPeripheralFunctions

Byp

ass

A[17:0]

D[7:0]

CE-

WE-

OE-

ExternalMemory

(FLASH)

CS

I B

us

Figure 26. The Memory Interface Unit (MIU) provides a glueless interface between the microcon-troller, its peripheral functions, and external memory.

33 www.triscend.com

cycle read, depending on the clock duty cycle, thesetup and width of OE- are roughly half a clockcycle each. Extra clock cycles can be added toeither the setup or the strobe width. The minimumsetup is ½ clocks and it can be extended to 7½clocks. Similarly, the pulse width of OE- can take aminimum of ½ clocks up to 7½ clocks. To summa-rize, a read cycle is programmable to between 25ns and 375 ns with a granularity of 25 ns, using a40 MHz system clock.

Write cycles are partitioned into three sections: asetup, a write pulse and a hold portion, as shown inFigure 29. The hold portion is optional. The setupand width are similar to the read case describedabove. Extra hold cycles can be added after thetrailing edge of the WE- signal to guarantee varioushold conditions. The fastest write access is per-formed in one clock cycle, with ½ clock for setupand ½ clock for write-pulse width. Additional clockcycles can be added to any portion of the write cy-cle through the MIU configuration register. Setupand pulse width can vary from ½ clock to 7 ½clocks. The hold portion varies from zero to 7clocks. To summarize, a write cycle is program-mable to between 25 ns and 550 ns with a granu-larity of 25 ns, using a 40MHz bus clock.

The following timing diagrams illustrate the optionsdescribed earlier.

BUSCLK

CE-

OE-

WE-

SETUP ACTIVE PARTOF CYCLE

Figure 27. Generalized read cycle using MIU.

BUSCLK

CE-

OE-

WE-

SETUP ACTIVE PARTOF CYCLE

Figure 28. One-cycle read operation using MIU.

BUSCLK

CE-

OE-

WE-

SETUP STROBE HOLD

D[7:0] VALID

Figure 29. Generalized write cycle using MIU.

BUSCLK

CE-

OE-

WE-

D[7:0] VALID VALID

SETUP STROBE

Figure 30. One-cycle write operationusing MIU.

WWaaiitt--ssttaattee GGeenneerraattiioonn

Generally, a wait signal is generated for every ex-ternal memory read access, except for a read froma fast external memory, with access time withinone clock cycle.

Memory writes operate differently. Because writedata and addresses are held in buffers, the MIUdoes not need to stall the CSI bus. A wait is gen-erated only if another memory access is requestedwhile the previous write is in progress.

Wait-states are also generated when the 8032 mi-crocontroller directly accesses external memory,bypassing the internal bus. These wait-states oc-cur because every bypass transaction is replicatedon the internal bus for debugging purposes. Thewait signal is synchronized correctly with the repli-cated transaction on the bus.

RReeqquueessttss AArrbbiittrraattiioonn

Three potential sources use the MIU as an internalsystem slave.


www.triscend.com 34

1. Any master can access the MIU via the CSIbus.

2. The microcontroller can bypass the CSI busand directly access the MIU.

3. The programmable address selectors cangenerate external memory requests.

EExxtteerrnnaall MMeemmoorryy RReeqquueesstt MMooddee

“Soft” modules implemented in the ConfigurableSystem Logic (CSL) matrix can borrow MIU re-sources to access external devices. Functions inthe CSL matrix can re-use the MIU's address anddata signals plus some control via the OE- andWE- pins. The CSL matrix can request a memorycycle by using a special mode of a Selector to gen-erate the chip enable (CE-) to the external device.The WE-, OE-, address and data signals are gen-erated through the MIU. The OE- and WE- signalsbehave similar to the general case. Their leadingedges are generated of the falling edge of theclock, and their trailing edges are generated of therising edge of the clock. Therefore, one cycle readsor writes are possible. Using the WAITNEXT sig-nal, the MIU knows if it has to extend the externalcommand (OE- or WE-) or if it should end the cur-rent cycle and generate a new one.

For write cycles, the setup time is always ½ clock.However, to improve margin at high clock rate, thesetup time can be extended by one full clock cycle.The hold time however is only guaranteed by thedelay on the address and data lines, requiring ex-ternal memory with 0ns hold time requirements. Ifdifferent timing is required by the application, thenthe OE- and WE- signals can be generated fromwithin the CSL matrix. These signals would thenconnect to external memory via a PIO pin.

IInniittiiaalliizzaattiioonn ooff tthhee MMIIUU

After a power-on reset or other device-wide reset,the MIU begins operation as a master on the CSIbus. The MIU is then ready to receive commandsvia the external memory bus. This is useful forslave-mode initialization. If the SLAVE- pin is heldHigh, then the MIU becomes a CSI bus slave dur-ing the initialization process.

During a power-on reset or other device-wide reset,the CE- signal is held High via an internal pull-up toprevent spurious writes.

MMIIUU RReeggiisstteerr DDeessccrriippttiioonn

The MIU and its different modes are programmedthrough 4 bytes of registers.

MMIIUU MMooddee RReeggiisstteerr

The MIU configuration register defines the currentoperating mode of the MIU.

SER_RD MASTER SLAVE

7 6 5 4 3 2 1 0

SER_WRDMA_RDDMA_WRReserved

Mnemonic: MIUMODE Address: FE30h

SLAVE, when set, indicates that the MIU is a slaveon the CSI bus. For most stand-alone applications,this is the mode used after configuration. Clearedby a Power-On or System Reset event.

MASTER, when set, indicates that the MIU is amaster on the internal system bus. This is the ini-tial state of the MIU upon power-up. Set by aPower-On or System Reset event.

SER_RD, when set, indicates that the MIU is con-figured to read configuration data from an externalserial sequential-access PROM. Cleared by apower-on reset or other device-wide reset.

SER_WR is used to program a FLASH- orEEPROM-based external serial sequential-accessPROM. Cleared by a power-on reset or other de-vice-wide reset.

DMA_RD is a reserved MIU mode used duringmanufacturing. Leave this bit cleared. Cleared bya power-on reset or other device-wide reset.

DMA_WR is a reserved MIU mode used duringmanufacturing. Leave this bit cleared. Cleared bya power-on reset or other device-wide reset.

NOTE: The MIU control registers are part of theE5’s “hidden” control register set. TheBLOCKSIZE bit in the DMAP3_CTLregister must be set in order to access theMIU control registers. The MIU registersare normally not modified by user appli-cation code.

MMIIUU TTiimmiinngg CCoonnttrrooll RReeggiisstteerrss

The MIU timing control register defines the timingof read and write control strobes issued by theMIU. The write hold time value WHT[2:0] fieldspans the two control bytes.

WSU2 WSU1 WSU0

7 6 5 4 3 2 1 0

WPW0WPW1WPW2WHT0WHT1

Mnemonic: MIUCTRL0 Address: FE31h

WSU[2:0] specifies the WE- setup time during amemory write cycle. It specifies the additionalnumber of clock cycles added to the minimumsetup time of ½ clock when generating a memorywrite cycle. The actual setup width is (WSU[2:0] +½) * (system clock period). These three bits areset to all ones by a power-on reset or other device-wide reset, defaulting to the slowest setting.

35 www.triscend.com

Table 15. Write Setup Time.

WSU2 WSU1 WSU0Bus Clock

Cycles0 0 0 0.50 0 1 1.50 1 0 2.50 1 1 3.51 0 0 4.51 0 1 5.51 1 0 6.5

1 1 17.5

(default)

WPW[2:0] specifies the pulse width of WE- duringa memory write sequence. The actual pulse widthis (WPW[2:0] + ½) * (system clock period). Thesethree bits are set to all ones by a power-on reset orother device-wide reset, defaulting to the slowestsetting.

Table 16. Write Pulse-Width Time.

WPW2 WPW1 WPW0Bus Clock

Cycles0 0 0 0.50 0 1 1.50 1 0 2.50 1 1 3.51 0 0 4.51 0 1 5.51 1 0 6.5

1 1 17.5

(default)

WHT[2:0] field specifies the width of the hold por-tion of a write cycle. The actual hold width isWHT[2:0] * (system clock period). These three bitsare set to all ones by a power-on reset or other de-vice-wide reset, defaulting to the slowest setting.NOTE: The WHT2 bit is part of the MIUCTRL1byte.

Table 17. Write Hold Time.

WHT2 WHT1 WHT0Bus Clock

Cycles0 0 0 00 0 1 10 1 0 20 1 1 31 0 0 41 0 1 51 1 0 6

1 1 17

(default)

RSU1 RSU0 WHT2

7 6 5 4 3 2 1 0

RSU2RPW0RPW1RPW2XMSU

Mnemonic: MIUCTRL1 Address: FE32h

RSU[2:0] specifies the additional number of clockcycles to add to the minimum setup time of a readcycle. The actual setup width is (RSU[2:0] + ½) *(bus clock period). These three bits are set to allones by a power-on reset or other device-wide re-set, defaulting to the slowest setting.

Table 18. Read Setup Time.

RSU2 RSU1 RSU0Bus Clock

Cycles0 0 0 0.50 0 1 1.50 1 0 2.50 1 1 3.51 0 0 4.51 0 1 5.51 1 0 6.5

1 1 17.5

(default)

RPW[2:0] specifies the pulse width of OE- during amemory read sequence. The actual pulse width is(RPW[2:0] + ½) * (system clock period). Thesethree bits are set to all ones by a power-on reset orother device-wide reset, defaulting to the slowestsetting.

Table 19. Read Pulse-Width Time.

RPW2 RPW1 RPW0Bus Clock

Cycles0 0 0 0.50 0 1 1.50 1 0 2.50 1 1 3.51 0 0 4.51 0 1 5.51 1 0 6.5

1 1 17.5

(default)

XMSU enables an additional clock cycle for setupin expansion cycles. This bit is cleared by a power-on reset or other device-wide reset.

MMIIUU SSeerriiaall MMooddee CCoonnttrrooll RReeggiisstteerr

This register provides control over serial-mode ini-tialization and over device programming for an ex-ternal, FLASH- or EEPROM-based, sequential-access serial PROM.

CE- SER_EN-RESET_

OE-

7 6 5 4 3 2 1 0

CLKSDOUTSDOUT_

EN-CLKDIVSDIN

Mnemonic: MIUSCTL Address: FE33 h

RESET_OE- drives the RESET/OE- enable pin ofthe external serial memory via the MIU's OE- pin.This bit is set by a power-on reset or other device-wide reset.


www.triscend.com 36

SER_EN- drives the write-enable input of an exter-nal FLASH- or EEPROM-based serial PROM forprogramming. This bit is set by a power-on resetor other device-wide reset.

CE- drives the chip-enable input of the externalserial PROM. This bit is set by a power-on reset orother device-wide reset.

SDOUT is the external serial memory data. Onlyused when programming an in-system program-mable, external, serial PROM. Unaffected by areset.

SDOUT_EN- is the external serial memory writedata output enable. In serial write mode, this bitprovides direct control over the three-state enableline of the output data buffers. Cleared by a power-on reset or other device-wide reset.

CLKDIV controls the speed of the serial clock inserial read mode only. When cleared, SCLK =BUSCLK/4. When set, SCLK=BUSCLK/64. Thisbe is set by default by a power-on reset or otherdevice-wide reset. The default is the slower mode.

SDIN is the serial memory read data. In serialwrite mode only, this bit corresponds to D0 of theexternal data bus. It enables software to read theacknowledge status while programming the serialmemory. This bit is read-only.

Address Mappers

The address mappers translate the 8032 micro-controller’s accesses to data, program or SFR ad-dress spaces into addresses for the Triscend CSIbus. Because of its architecture, an 8032 micro-

controller supports multiple address spaces, asshown in Figure 31.

The 8032 microcontrollers has two separate, ex-ternal 64K bytes address spaces: program anddata. Program memory holds instructions and ar-guments used during code fetching while datamemory stores variables and other data for appli-cations.

The shaded blocks Figure 31—external programmemory, external data memory and user-selectedSFR registers—can be directed onto the TriscendE5’s CSI bus. The MCU’s indirect and direct inter-nal RAM spaces can not be mapped outside the8032 microcontroller. The internally implementedSFRs—ACC, B register, power, timers, serialchannel control, etc.—are not mapped outside the8032 MCU to avoid software incompatibilities.

Address mappers translate the microcontroller’s 8-or 16-bit logical address to a 32-bit physical ad-dress on the CSI bus. Each mapper monitors mi-crocontroller accesses to a particular type of ad-dress space such as program, data or externalSFR address space.

Mappers respond to accesses within a selectablezone of logical addresses. The zones refer to arange of addresses. The zone size is a power oftwo with a minimum size of 256 bytes and a maxi-mum of 64K bytes. A zone starts on any logicaladdress boundary that is a multiple of its size.When an address match occurs between an 8032address and an address mapper zone, the MCU‘slogical address is translated to a physical CSI busaddress.

A[7:0]A[15:8]

8032 Logical Address

ZONE

BLOCK SIZE

ENABLE

=

A[31:0]

CSI Bus Physical Address

Mask = 2BLOCK_SIZE - 1

Target Address[23:0]

Translate

Generated Mask

Figure 32. Address mapper conceptual blockdiagram.

Figure 32 shows a generalized block diagram ofhow an address mapper translates an 8032 logicaddress into a physical address displayed on theCSI bus.

0xFFFF 0xFFFF

0

ExternalProgramMemory

0

ExternalData

Memory(XDATA)

0xFF 0xFF

0x80

IndirectInternal

RAM0x80

Internal andExported

SFRs

0x1F

0

DirectInternal

RAM

Figure 31. 8032 microcontroller addressspaces.

37 www.triscend.com

When the MCU presents an address, the appropri-ate mapper tracks the type of operation. A codemapper only responds to code accesses, a datamapper only responds to data accesses, and soon. The block size defines how many lower ad-dress bits are ignored when comparing the MCU’slogic address and the target address zone. Be-cause all zones must be equal to 256 bytes or

larger, the lower eight bits of the generated maskcan be ignored during the comparison. The map-per then compares the upper 8 bits of the logicaladdress with the 8 bits of the zone target addressand masks off any locations indicated with theBLOCK_SIZE value. If the mapper is enabled andthe two addresses compare, then the mapper pre-sents the translated address on the CSI bus. The

PrimaryInitializationCode ROM

0

0xFFFF

InternalRAM

0x1_0000

0x1_FFFF

Config. Reg.Unit (CRU)

0x2_0000

0x2_FFFF

CPU DebugRegisters

0x3_0000

0x3_FFFF

InitializationMemory

0x4_0000

0x7_FFFF

Reserved

0x8_0000

0x9_FFFF

CSL-based"Soft"

ModuleRegisters

decoded viaSelectors

0x10_0000

0x7F_FFFF

0xFF_FFFF

0x80_0000

DMAP0DMAP1DMAP2

DMAP3

DMAP4DMAP5

CMAP0CMAP1

CMAP2

0

0xFFFF CRU

XDATA RAM

"Soft"Modules

User Code

0

0xFFFF

Data Mappers

Code Mappers

0xFF

0x80

xdata

code

sfr

XMAP

SFR ExportMapper

User Code

Init. Code,Data, +Header

32-bitPhysicalMemory

8032 LogicalMemory Spaces

Primary initializationcode is only visibleafter power-on or RST-

DMAP5 availablefor user applications

CMAP2 availablefor user applications

Initialization code, data, andheader always in last 256Kbytes, aligned to 16Kboundary

FastChip able to export someSFR locations

0

0x3_FFFF InitializationCode, Data, +

Header

User Code

ExternalMemory

Secondary initializationprogram copies initializationdata from external memory intoinitialization memory within E5,after power-on or RST-

Example memory mapafter initialization

Example memory mapafter initialization

Mappers shown bypriority, top to bottom

Mappers shown bypriority, top to bottom

Single code-bankapplications fit in a 256Kx8memory. Initialization codealways appears at the top ofmemory, code at the bottom.

Mem

ory

Inte

rfac

e U

nit

SFRs

Similar to original8051/52 Physical memory map automatically created by FastChip

CMAP1 points tothe MIU if operating

from Flash. Elsepoints to internal

RAM.

Figure 33. The Triscend FastChip development system uses the internal code and data mappersto automatically create a 16M-byte memory map.


www.triscend.com 38

lower physical address bits consists of the maskedbits from the logical address, A[15:0]. Because allzones are 256 bytes or larger, the lower-byte of thelogic address, A[7:0], always maps directly to thetranslated address. The upper bits of the trans-lated address are the unmasked values from themapper’s 24-bit target address value.

If the logical address does not match the mapperstarget zone, then the next-highest priority mapperexamines the logical address. This process re-peats among other mappers of the same type—i.e.code or data—until a match is found. The lowest-priority mapper is always guaranteed to match.

The dedicated resources on the CSI bus only de-code 24 address lines, A[23:0]. The higher orderaddress lines, A[31:24] can carry diagnostics in-formation for debugging purposes.

The mapper values are defined in the configurationregisters. In general, each mapper has

! 8 bits of zone address, the value to matchagainst the expected logical value on A[15:8],

! 5 bits for block size, specified as the log basetwo of zone size in bytes

! 24 bits, which form the upper bits of the CSIphysical address values. When a match oc-curs, this value is placed on the CSI physicaladdress lines A[31:8], and

! one enable bit.

The block size results in a mask used during ad-dress matching. The block size is specified as thelog base two of the desired address zone size, inbytes. The mask is a result of the following calcu-lation.

12 _ −= SizeBlockMaskThe lower 8 bits of the logical address are not partof the comparison. A block size must be in therange between 256 and 64K. Consequently, theblock size value must be between 8 and 16, inclu-sive.

Various system resources occupy non-contiguousaddress spaces in the 4G-byte address spaceavailable through the CSI bus. The Triscend Fast-Chip development system automatically creates a16M-byte memory map as shown in Table 20 andFigure 33. The memory map is 16M bytes insteadof the full 4G bytes because the upper eight bits ofthe physical address are assigned to the valuesshown in Table 23 to aid in debugging.

CCooddee mmaappppeerrss

Code mappers perform address translations oncode fetches. There are three code mappers, in-cluding a dedicated code mapper for the initializa-tion program stored in on-chip ROM plus two fullyprogrammable code mappers. The code mappersare listed in Table 21.

Table 21. Code Mappers.Mapper Priority Enable

C2 1 OptionalC1 2 Optional

C0 (ROM) 3 Always Enabled

Table 20. Addresses Allocated to System Resources.

CSI physicaladdress space

8032Address

zone (bytes) Description Notes0 – 0xFFFF 1K Internal ROM Accessible following a system reset

0x1_0000 –0x1_FFFF

Depends ondevice

Internal XDATA RAMTE502=8K, TE505=16K,TE512=16K, TE520=40K,TE532=64K

0x2_0000 –0x02_FFFF

256 or4K

CRU – system configurationregisters

0x3_0000 –0x7_FFFF

N.A. Reserved Debugger access only

0x10_0000 –0x7F_FFFF

User-defined(*)

CSL “soft” modules, externaldevices, external memories,

and exported SFRs.

External devices or memories otherthan the one connected to CE- out-put pin should use this addressspace also.

0x80_0000 –0xFF_FFFF

<= 64K External Memory Connected via the MIU port

39 www.triscend.com

CC00 –– RROOMM ccooddee mmaappppeerr

The C0 mapper has the lowest priority. The inter-nal ROM is always accessible by the microcontrol-ler following a System Reset event. The ROM sizeis fixed at 1K byte, implemented with 64 copies thatare available in the program space. The copiesare repeated at every 1K byte boundary in codespace.

At the end of the initialization program, the othertwo code mappers, C1 and C2, can be pro-grammed to override the ROM code mapper.

The C0 mapper has two programmable registers:CMAP0_TAR and CMAP0_ALT, both residing inthe CRU. During a C0 address-matching event,the content of the CMAP0_TAR or CMAP0_ALTregister is placed on the A[31:24] physical CSI busaddress lines whenever an operand or an op-codefetch occurs, respectively. This feature is useful indebugging sessions to discriminate between op-code or operand fetches. C0 is always enabled.

CC00 OOppeerraanndd TTaarrggeett AAddddrreessss ((RROOMM mmaappppeerr))

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: CMAP0_TAR Address: FF00h

CC00 OOpp--CCooddee TTaarrggeett AAddddrreessss ((RROOMM MMaappppeerr))

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: CMAP0_ALT Address: FF01h

CC11,, CC22 –– FFuullllyy pprrooggrraammmmaabbllee ccooddee mmaappppeerrss

Code mapper C2 has the highest priority in case ofan address overlap with other code mappers. C1and C2 can be individually enabled. Following asystem reset, mappers C1 and C2 are disabled.Mapper C0 is always enabled. The Triscend ini-tialization program assigns application dependentvalues to these mappers. The user can modifythese assignments by writing different values to thecorresponding mapper registers.

CC11 TTaarrggeett AAddddrreessss ((LLooww BByyttee))

A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: CMAP1_TAR_0 Address: FF02h

CC11 TTaarrggeett AAddddrreessss ((MMiidd BByyttee))

A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0


CC11 OOppeerraanndd TTaarrggeett AAddddrreessss

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0


CC11 OOpp--CCooddee TTaarrggeett AAddddrreessss

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: CMAP1_ALT Address: FF07h

CC11 ZZoonnee SSoouurrccee AAddddrreessss

A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: CMAP1_SRC Address: FF05h

CC11 CCoonnttrrooll

- SIZE4 SIZE3 SIZE2 SIZE1 SIZE0- ENBL

7 6 5 4 3 2 1 0

Mnemonic: CMAP1_CTL Address: FF06h

CC22 TTaarrggeett AAddddrreessss ((LLooww BByyttee))

A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0


CC22 TTaarrggeett AAddddrreessss ((MMiidd BByyttee))

A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0


CC22 OOppeerraanndd TTaarrggeett AAddddrreessss

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: CMAP2_TAR_2 Address: FF0Ah

CC22 OOpp--CCooddee TTaarrggeett AAddddrreessss

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: CMAP2_ALT Address: FF0Dh

CC22 ZZoonnee SSoouurrccee AAddddrreessss

A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: CMAP2_SRC Address: FF0Bh


www.triscend.com 40

CC22 CCoonnttrrooll


7 6 5 4 3 2 1 0

Mnemonic: CMAP2_CTL Address: FF0Ch

DDaattaa mmaappppeerrss

Data mappers perform address translations ondata access instructions. There are six data map-pers as shown in Table 22. D0 maps accesses tothe internal system SRAM. D1, D2, D4, and D5are fully programmable and D3 maps the CRUconfiguration registers.

Table 22. Data Mappers.Mapper Priority Enable

D3 (CRU) 1 Always EnabledD5 2 OptionalD4 3 OptionalD2 4 OptionalD1 5 Optional

D0 (RAM) 6 Always Enabled

DD00 –– RRAAMM ddaattaa mmaappppeerr

The D0 has the lowest data mapping priority. Theinternal system RAM is always accessible by themicrocontroller in data space following a SystemReset. The size and configuration of the internalsystem RAM is device dependent.

For example, the RAM in the TE520 has a fixedsize of 40K bytes. The bottom 32K bytes reside indata locations 0000h – 7FFFh. Four copies of thetop 8K bytes appear at data locations 8000h,A000h, C000h and E000h, unless another datamapper is enabled and re-uses these locations.

If enabled, data mappers D1 and D2 override RAMdata space. The D3 mapper, used to access theconfiguration registers (CRU) always overrides theother mappers, as explained below.

The D0 mapper has one programmable CRU reg-ister, DMAP0_TAR. The content of DMAP0_TARis placed on the A[31:24] physical CSI bus addresslines when a D0 matching event occurs. D0 is al-ways enabled.

DD00 TTaarrggeett AAddddrreessss ((RRAAMM mmaappppeerr))

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: DMAP0_TAR Address: FF0Eh

DD11,, DD22,, DD44,, DD55 –– FFuullllyy pprrooggrraammmmaabbllee ddaattaa mmaapp--ppeerrss

Data mapper D5 has higher priority in case of anaddress overlap with D4, D3, D2, D1 or D0. Map-pers D5, D4, D2, and D1 can be individually en-abled and are disabled after a System Reset event.

The Triscend initialization program assigns appli-cation dependent values to these mappers. Theuser can modify these assignments by writing dif-ferent values to the corresponding mapper regis-ters.

DD11 TTaarrggeett AAddddrreessss ((LLooww BByyttee))

A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: DMAP1_TAR_0 Address: FF0Fh

DD11 TTaarrggeett AAddddrreessss ((MMiidd BByyttee))

A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0

Mnemonic: DMAP1_TAR_1 Address: FF10h

DD11 TTaarrggeett AAddddrreessss ((HHiigghh BByyttee))

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0


DD11 ZZoonnee SSoouurrccee AAddddrreessss

A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: DMAP1_SRC Address: FF12h

DD11 CCoonnttrrooll


7 6 5 4 3 2 1 0

Mnemonic: DMAP1_CTL Address: FF13h


A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0



A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0



A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0


41 www.triscend.com


A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0


DD22 CCoonnttrrooll


7 6 5 4 3 2 1 0



A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0



A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0



A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0



A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0


DD44 CCoonnttrrooll


7 6 5 4 3 2 1 0



A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0



A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0



A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0



A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0


DD55 CCoonnttrrooll


7 6 5 4 3 2 1 0


DD33 –– CCRRUU ddaattaa mmaappppeerr

Data mapper D3 has the highest data mappingpriority. The configuration registers (CRU) are al-ways accessible by the microcontroller. D3 hastwo selectable sizes of 4K and 256 bytes. Follow-ing a system reset, the D3 block size is set to 4Kbytes and occupies the upper 4K bytes of the logi-cal data space, between addresses F000h andFFFFh, inclusive. At the end of the initializationprogram, the D3 data mapper zone is reduced to256 bytes to conserve address space.

D3 start address must be aligned to 4K addressboundaries. All mapper registers are accessiblethrough D3. The D3 mapper is always enabled.

DD33 TTaarrggeett AAddddrreessss

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: DMAP3_TAR Address: FF19h


- - - - A15 A14 A13 A12

7 6 5 4 3 2 1 0


DD33 CCoonnttrrooll

- - - - -- -

7 6 5 4 3 2 1 0

BLOCKSIZE

Mnemonic: DMAP3_CTL Address: FF1Bh

When set, BLOCKSIZE defines the D3 mapperblock size to 4K bytes. The BLOCKSIZE bit is setautomatically at power-up. When cleared, theblock size is reduced to 256 bytes.


www.triscend.com 42

SSFFRR eexxppoorrtt mmaappppeerr

A Triscend configurable system-on-chip user cancreate custom microcontroller “soft” modules usingthe on-chip Configurable System Logic (CSL) ma-trix. These “soft” modules can be mapped into the8032’s external data memory (XDATA) or into SFRspace. If a CSL “soft” module is mapped into SFRspace, then any control registers implemented inthe CSL replace locations within the 8032’s SFRmemory. The fully programmable SFR exportmapper supplies a 32-bit address on the CSI buswhenever an external SFR access is detected.Following a System Reset event, this mapper isdisabled. The SFR export mapper has a specialprogrammable register called XMAP_ALT. Thecontent of XMAP_ALT or XMAP_TAR_2 is placedon the A31-A24 CSI bus address lines when alatch or a pin instruction occurs, respectively, dur-ing an external SFR access event. This feature canbe useful in debugging sessions to discriminatebetween various SFR instructions.

Overall, there are 128 SFR-addressable locationsin an 8032 microcontroller. Table 30 describes theSFRs within the MCU's scratchpad RAM. TheTriscend FastChip development software preventsattempts to place CSL “soft” modules on internalSFR addresses already used by the MCU.

The translated address, when accessing an ex-ported SFRs, consists of the XMAP_TAR_2 orXMAP_ALT register, the XMAP_TAR_1 register,and the XMAP_TAR_0 register appended to theA[7:0] address from the 8032 MCU.

“Soft” modules with exported SFR registers canalso be accessed via 8032 external-memory refer-ences, using the values loaded into the data map-pers. Placing “soft” module registers in the 8032’sSFR address space allows faster and simpler ac-cess using direct reference instructions. Thismethod also enables the application code to usebit-manipulating instructions on these registers.

Application code usually never modifies the SFRexport mapper registers. The register values areset during initialization.

SSFFRR EExxppoorrtt TTaarrggeett AAddddrreessss ((LLooww BByyttee))

A15 A14 A13 A12 A11 A10 A9 A8

7 6 5 4 3 2 1 0

Mnemonic: XMAP_TAR_0 Address: FE20h

SSFFRR EExxppoorrtt TTaarrggeett AAddddrreessss ((MMiidd BByyttee))

A23 A22 A21 A20 A19 A18 A17 A16

7 6 5 4 3 2 1 0


SSFFRR EExxppoorrtt TTaarrggeett AAddddrreessss ((LLaattcchh IInnssttrruuccttiioonn))

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0


SSFFRR EExxppoorrtt TTaarrggeett AAddddrreessss ((PPiinn IInnssttrruuccttiioonn))

A31 A30 A29 A28 A27 A26 A25 A24

7 6 5 4 3 2 1 0

Mnemonic: XMAP_ALT Address: FE24h

DDeeffaauulltt VVaalluueess ffoorr HHiigghheerr--OOrrddeerr AAddddrreessss MMaapp--ppeerrss

Table 23 shows the default assignment for higheraddress bits in each of the mappers. These valuesare loaded into the mapper registers during theinitialization process.

Table 23. Default Values for Higher-Order Ad-dress Mapper Registers.

TransactionType Register Name

DefaultValue

A[31:24]C2 OperandFetch

CMAP2_TAR_2 30h

C2 Op-CodeFetch

CMAP2_ALT 50h

C1 OperandFetch

CMAP1_TAR_2 28h

C1 Op-CodeFetch

CMAP1_ALT 48h

C0 OperandFetch(Init. ROM)

CMAP0_TAR_2 20h

C0 Op-CodeFetch(Init. ROM)

CMAP0_ALT 40h

D3 Data(CRU Regis-ters)

DMAP3_TAR_2 98h

D5 Data DMAP5_TAR_2 A8hD4 Data DMAP4_TAR_2 A0hD2 Data DMAP2_TAR_2 90hD1 Data DMAP1_TAR_2 88hD0 Data DMAP0_TAR_2 80hSFR Latch XMAP_ALT E0hSFR Pin XMAP_TAR_2 C0h

The Triscend FastChip development system usesthese default values when assigning the 32-bitphysical addresses for the CSL address selectors.These values and the mapper registers themselvesallow CSL address selectors to selectively respondto different instruction types.

For example, if a Flash memory device is con-nected to the MIU, some addresses can be ac-cessed as code or data segments. During normal

43 www.triscend.com

operation, the Flash segment is typically used tostore code. However, during a programming ses-sion, the Flash memory is regarded as a datasegment. This differentiation between code anddata using high order address lines distinguishesbetween code and data accesses to the samephysical address.

In another example, assume that an address se-lector is used to enable off-chip ROM for externalcode storage. Code mapper C1 might point theROM. The selector would need to respond to bothoperand and op-code fetches. BecauseCMAP1_TAR_2 = 00101000b and CMAP1_ALT =000010000b, FastChip will program the upper byteof the selector's MASK register with 0010000,making the selector respond to both operands andop-code fetches.

The mapper values are also used during debug-ging allowing the hardware breakpoint unit to dis-tinguish between operand and op-code fetches

The distinction between SFR pin and SFR latchtransactions is required only if the designer selects8032-compatible PIO ports from Triscend "soft"

module library. The 8032 microcontroller has in-structions that treat 8032 PIO ports differently thantheir respective SFR. In applications, there is noneed for CSL address selectors to distinguish be-tween SFR latch and SFR pin instructions.

System Debugger

A PC acting as an external tester or debugger caninterface with the Triscend E5 configurable system-on-chip via its JTAG port, using a cable connectedbetween the PC parallel port and the target board,as shown in Figure 34.

The JTAG unit can access all addressable systemresources by becoming the bus master on the in-ternal CSI bus. Serving as a bus master, the JTAGunit converts serial bitstreams into parallel registerswhose contents are placed on the address, dataand command buses to emulate CSI bus transac-tions. A JTAG master also directly accesses inter-nal MCU registers and CSL configuration data withvisibility to functions not accessible from applicationprograms.

Debug Host System

Fre

eze

Inte

rrup

t

Rese

t

Inte

rrup

t

JTA

G

Inte

rface

Configurable System-on-Chip

UserCode

External Memory

InitializationData

CS

I BU

S(a

dd

ess,

dat

a,co

ntr

ol,

arb

itra

tio

n)

MIU

Bus Reset

DMA Req

DMA AckDMA

Controller

JTAGController

InternalSRAM

8032"Turbo"

MCU

BreakpointLogic

CSL LogicClockDisables

Figure 34. System debugging block diagram.


www.triscend.com 44

Furthermore, the JTAG unit can hold the MCU inreset by asserting the J_RESET command or holdthe entire system in reset using the FORCE_BRSTand FORCE_NOBRST. The JTAG unit also inter-acts with the MCU using an interrupt handshakemechanism (J_INTR). For additional details, referto the “Reset Conditions” section.

The JTAG unit serves as a bus slave when inter-acting with the DMA controller. It first becomesmaster on the CSI bus, programs the DMA unit totransfer data to or from the JTAG unit, and thenrelinquishes the CSI bus to the DMA controller.After configuring the DMA, the JTAG unit interfaceswith the DMA controller as a slave device using theDMA's request and acknowledge signals. There isconsiderably less overhead in this type of datatransactions since the JTAG unit does not need toprovide address or control information during DMAoperations.

Serving as a bus master, the JTAG unit is able toset breakpoint events within the breakpoint unit,which is also a slave connected on the CSI bus.The breakpoint unit supports two independentbreakpoint conditions. The breakpoint unit moni-tors user-specified combinations of address, data,control or DMA signals as breakpoint events. Theuser can also count logic conditions occurring in-side the CSL as breakpoint events. A breakpointspecification can count up to 64K-1 incidents as thematching condition for a break event.

Once a breakpoint condition occurs, then depend-ing on its current configuration, the MCU freezes atthe end of the current instruction or receives a

breakpoint interrupt and branches to execute de-bugger interrupt routines. Following a breakpointfreeze, CSL clocks or global signals can beblocked to aid system debugging. The TriscendFastChip software enables the user to specifywhich CSL clocks or global signals are affectedfollowing a breakpoint freeze.

During a CPU freeze period, the JTAG unit can pollany addressable location residing inside or outsidethe CSoC and send all requested information to thehost PC for further display and analysis.

At the end of the debugging session, JTAG clearsthe breakpoint “freeze MCU” condition and the8032 “Turbo” microcontroller resumes code execu-tion from where it left off. Alternatively, the JTAGunit can restart code execution from 0000h by is-suing a J_RESET command to the MCU.

At any point in time, the JTAG unit can instruct theMCU to enter a single-step operation and sendpertinent display information to the host PC.

The JTAG port can also be used to initialize theCSoC or to update external memory devices con-nected to the MIU port. Using external Flashmemory, the JTAG unit downloads a Flash-programming algorithm to the CSoC’s internalRAM. It then interacts with the internal MCU, al-lowing the processor to control the actual program /erase / verify algorithms while the JTAG port sup-plies new data for programming or new series ofcommands required by the MCU.

45 www.triscend.com

Configuration Register Unit (CRU)

The Configuration Register Unit (CRU) containsthe control registers for functions within the Tris-cend E5 configurable system-on-chip. For mostapplications, the CRU registers occupy the upper256 bytes of external data space.

Table 24 shows the functions controlled by theCRU registers. Unused locations have no functionand are not RAM locations.

System Initialization

Like most processors, the Triscend E5 requiresinitialization data to configure programmable op-tions available within the device before it becomesfunctional. The Triscend E5 offers four differentsystem initialization options to best fit various targetapplications, as shown in Table 25. Both activeand passive initialization methods are available.

In active initialization modes, the Triscend E5 pro-vides the control signals, directing data transfersand controlling external devices.

In passive modes, an external controller directsdata transfers.

Table 25. Initialization Modes.

InitializationMode Method Data Source

Parallel ActiveByte-wide parallelmemory (FLASH)

Serial ActiveSequential-accessserial PROM

Secure ActiveBattery-backed in-ternal SRAM

JTAG PassiveDownloaded by in-telligent host throughJTAG port

Slave Passive

Downloaded byother controllerthrough bus inter-face.

Table 24. Configuration Register Unit (CRU).

FF88h DMAP5_SRC DMAP5_CTL

FF80h DMAP4_TAR_0[7:0]

DMAP4_TAR_1[15:8]

DMAP4_TAR_2[23:16] DMAP4_SRC DMAP4_CTL DMAP5_TAR_0

[7:0]DMAP5_TAR_1

[15:8]DMAP5_TAR_2

[23:16]

FF78h

FF70h

FF68h

FF60h PROTECT SECURITY PWDSEL PORCTRL

FF58h

FF50h

FF48h DMACRC_0[7:0]

DMACRC_1[15:8]

FF40h DMACADR1_1[15:8]

DMACADR1_2[23:16]

DMACADR1_3[31:24]

DMACCNT1_0[7:0]

DMACCNT1_1[15:8]

DMACCNT1_2[23:16]

DMAPREQ1_0[7:0]

DMAPREQ1_1[15:8]

FF38h DMASCNT1_0[7:0]

DMASCNT1_1[15:8]

DMASCNT1_2[23:16]

DMACTRL1_0[7:0]

DMACTRL1_1[15:8] DMAEINT1 DMAINT1 DMACADR1_0

[7:0]

FF30h DMACCNT0_1[15:8]

DMACCNT0_2[23:16]

DMAPREQ0_0[7:0]

DMAPREQ0_1[15:8]

DMASADR1_0[7:0]

DMASADR1_1[15:8]

DMASADR1_2[23:16]

DMASADR1_3[31:24]

FF28h DMACTRL0_1[15:8] DMAEINT0 DMAINT0 DMACADR0_0

[7:0]DMACADR0_1

[15:8]DMACADR0_2

[23:16]DMACADR0_3

[31:24]DMACCNT0_0

[7:0]

FF20h DMASADR0_0[7:0]

DMASADR0_1[15:8]

DMASADR0_2[23:16]

DMASADR0_3[31:24]

DMASCNT0_0[7:0]

DMASCNT0_1[15:8]

DMASCNT0_2[23:16]

DMACTRL0_0[7:0]

FF18h DMAP2_CTL DMAP3_TAR DMAP3_SRC DMAP3_CTL

FF10h DMAP1_TAR_1[15:8]

DMAP1_TAR_2[23:16] DMAP1_SRC DMAP1_CTL DMAP2_TAR_0

[7:0]DMAP2_TAR_1

[15:8]DMAP2_TAR_2

[23:16] DMAP2_SRC

FF08h CMAP2_TAR_0[7:0]

CMAP2_TAR_1[15:8]

CMAP2_TAR_2[23:16] CMAP2_SRC CMAP2_CTL CMAP2_ALT DMAP0_TAR DMAP1_TAR_0

[7:0]

FF00h CMAP0_TAR CMAP0_ALT CMAP1_TAR_0[7:0]

CMAP1_TAR_1[15:8]

CMAP1_TAR_2[23:16] CMAP1_SRC CMAP1_CTL CMAP1_ALT

Unused location, not RAM.


www.triscend.com 46

PPaarraalllleell MMooddee

Parallel mode initialization, as shown in Figure 35,enables the user to store and execute applicationprograms from a standard, byte-wide externalmemory. System configuration is also stored in theexternal memory. System initialization time is muchfaster relative to serial configuration because userapplication programs are typically not downloadedto internal system RAM.

The MIU signals are:

D[7:0] – the eight-bit data bus from the externalmemory.

A[17:0] – the lower 18 bits of the address bus. Ifadditional address bits are required, the upper ad-dress lines—A18 and beyond—can be enabled inthe user’s design.

WE- - write enable signal provided to writeablememories such as Flash, EEPROM, and SRAM

OE- - enables the data output from the externalmemory during a read operation.

CE- - chip enable to the external memory.

Triscend E5CSoC

A[17:0] D[7:0] WE- OE- CE-

SLAVE-

PMOD VSYS

Memory Interface Unit (MIU)

A[x:18]

CE-External Parallel Memory

OE-WE-D[7:0]A[x:0]

VCC

(op

tion

al)

Up

pe

r A

dd

ress

Applic

atio

n D

ependent

(op

tion

al)

CE-

Figure 35. Parallel-mode initialization.

PMOD is optionally pulled up to VCC. If left un-connected, PMOD powers on with a weak pull-upresistor, pulling the pin High during the initializationphase.

Address lines A[17:0] sufficiently address up to256K bytes of external memory. If a larger mem-ory device is used, additional optional address linesserve as high-order address lines. Even thoughthe 8032 can only directly access 64K bytes ofcode space, the Triscend E5 provides more codespace by using code mappers that dynamicallychange the 8032’s base address. The externalparallel memory can also contain data arrays suchas look-up tables. Using data mappers, the exter-

nal memory can also be mapped to the externaldata memory of the processor.

Once the system initialization is complete, the 8032microcontroller starts executing application codefrom location 0000h, which is mapped to the exter-nal memory. Parallel mode requires that at leastsome application code reside in external memory.At the beginning of application program execution,code mapper C1 maps locations 0000H – 7FFFHof program space into the external memory. Theuser application code must initialize the data map-pers and code mappers.

During the parallel initialization phase, all PIO andMIU pins that do not participate in the parallelmemory interface, are pulled High by weak pull-upresistors. These pins are properly initialized to theiruser-defined configurations at the end of initializa-tion.

SSeerriiaall IInniittiiaalliizzaattiioonn

In serial initialization mode, the initialization dataand user code are stored in a sequential-accessserial PROM, similar to the devices used to pro-gram FPGA devices. Sequential-access serialPROMs are distinct from I2C- or SPI-format serialPROMs, as they are not addressable and are typi-cally much higher density.

Serial initialization mode frees most of the memoryinterface unit (MIU) pins so that they can be usedas PIO pins in the user's design. Figure 36 showsthe connections between the Triscend E5 configur-able system-on-chip and the serial memory.

Triscend E5CSoC

A0/SCLK D0/SDIN OE- CE-

SLAVE-

PMOD VSYS


CE-

External Sequential-AccessSerial PROM

OE-/RESETDATACLK CE-

Applic

atio

n D

ependent

CE-

VPP

VCC

VCC CEO-

to cascade serial PROMs

Figure 36. Serial-mode initialization.

The serial memory interface requires only four in-terface signals.

D0/SDIN - serial data bit from the serial PROM.

47 www.triscend.com

A0/SCLK - serial-clock supplied to the serialPROM.

OE-/SRST - resets the serial memory to its startinglocation when High and enables the serial dataoutput when Low.

CE- - serial chip enable.

The PMOD input pin must tied Low, indicating Se-rial Mode initialization. Tying the SLAVE- pin Highensures that the system starts up in a single chipmode, configuring itself rather than relying on an-other intelligent controller to provide initializationdata.

Following a power-on reset or a system reset, theCSoC detects Serial Mode and starts downloadinginitialization bitstream into the CSL. After the sys-tem initialization phase, the application program isserially loaded into the internal RAM.

Serial mode requires that application code reside inthe internal RAM. Once the user program is resi-dent in the system RAM, the 8032 "Turbo" micro-controller starts executing user code from location0000h, which is mapped to the internal systemRAM. At the beginning of user program execution,code mapper C1 maps the entire 64K bytes of pro-gram space into the internal system RAM. How-ever, the data mapper values must be handled byapplication code.

During the serial download phase, all PIO and MIUpins not active during the serial initialization proc-ess are pulled High by weak pull-up resistors. Afterinitialization, these pins perform as described in thelogic design.

JJTTAAGG IInniittiiaalliizzaattiioonn

The JTAG mode initializes the Triscend E5 usingan external tester, personal computer (PC), orother intelligent host. The JTAG port is also usefulfor debugging application code or to program ex-ternal memory devices via the MIU port. When aPC acts as a host, the JTAG unit is controlled by aseries of commands entered from the TriscendFastChip development system or third-party hard-ware debugger.

Triscend E5CSoC

A[17:0] D[7:0] WE- OE- CE-

SLAVE-

PMOD VSYS

TMSTDOTDI TCK


JTAG Unit

A[x:18]

CE-

External Tester orHost PC

External Parallel Memory(Optional)

OE-WE-D[7:0]A[x:0]

VCC

(op

tion

al)

Up

pe

r A

dd

ress

Applic

atio

n D

ependent

CE-

Figure 37. A JTAG interface to the Triscend E5.

External memories are not required in JTAG con-figuration mode. The JTAG link can directly initial-ize the CSL matrix, download the necessary appli-cation code into the internal RAM, assign values tothe data and code mappers and direct the 8032microcontroller to execute code from the internalsystem RAM.

Since the JTAG unit can serve as a system debug-ger in this operating mode, any type of externalmemory device is allowed.

Figure 37 depicts a typical JTAG interface to aTriscend E5. In the figure, the CSoC is alreadyconnected to an external parallel memory. TheJTAG port is compliant with IEEE standard 1149.1.The four JTAG pins are dedicated only to the JTAGfunction.

TCK – Test clock input. If unused should be tiedhigh.

TMS – Test mode select input. If unused shouldbe tied high.

TDI – Test data input. If unused should be tiedhigh.

TDO – Test data output.

The JTAG unit also serves as a master on the CSIbus and can read and write every addressable en-tity in the system.

The JTAG port optionally controls the 8032 "Turbo"microcontroller by setting breakpoint events thatfreeze the MCU. Once the processor is frozen, theJTAG unit can single-step the processor, examinethe internal registers of the processor, and thenresume the processor operation.


www.triscend.com 48

With the help of the microcontroller, the JTAG portcan also program an external Flash memory. Inthe Flash programming mode, the JTAG unitdownloads program / erase / verify algorithms intothe internal RAM. The new Flash programmingdata can also be stored in the internal RAM. Afterthe code and data mappers are properly definedvia the JTAG port, the 8032 microcontroller canexecute the program / erase / verify algorithms re-quired to write new data into an external Flashmemory device. The processor interacts with theJTAG unit through flags and shared variables or viainterrupts.

SSllaavvee MMooddee

In slave mode, the initialization data is downloadedinto the CSoC via a byte-wide, memory-mappedinterface, as shown in Figure 38. An external con-troller, microprocessor, or a master Triscend E5device selects the slave CSoC by asserting theCE- signal. Up to 18 address inputs are required toinitialize a single device. The address bus is ex-pandable up to 32 bits if required by the applica-tion. The external controller presents address anddata, then strobes the WE- signal.

The master controller and the slave CSoC shouldoperate from the same external clock signal.

Once initialized, the master controller removes theslave's internal reset by setting the SRST_DIS bitin the slave's MISC configuration register. The8032 microcontroller within the slave then beginsoperation. However, a slave microcontroller is notallowed to perform external code fetches. How-ever, it can execute instructions downloaded by themaster controller into the slave's internal systemRAM.

Triscend E5CSoC

(Slave Mode)

A[17:0] D[7:0] WE- OE- CE-

SLAVE-

PMOD VSYS


A[x:18]

CE-

External Controller orMaster E5 CSoC

OE-WE-D[7:0]A[x:0]

(optio

nal)

Up

pe

r A

dd

ress

Ap

plic

atio

n D

ep

en

de

nt

(optio

nal)

CE-

VCC

Figure 38. A slave mode interface to a TriscendE5 CSoC.

''SStteeaalltthh'' MMooddee

The CSoC has a security register allowing users toblock external accesses through the MIU port or toprevent JTAG from executing CSI transactions.This mode is most useful when the CSoC's internalcontents are battery-backed when power is re-moved. In this mode, the initialization data is firstdownloaded into the CSoC and the applicationcode stored and executed from internal systemRAM. Then the security bit is set, making theCSoC's operation invisible to external probes.

When power is re-applied after the CSoC was insecure mode and its contents battery backed, thenthe CSoC begins executing from internal SRAM.

Blocking MIU accesses forces the 8032 "Turbo"microcontroller to execute code only from the inter-nal RAM. The executed program is prevented fromfetching external code or data through the MIUport. Hackers cannot track the program flow sincethe MIU port is disabled.

Blocking JTAG transactions on the CSI bus is es-sential to prevent an external tester from readingconfiguration and code stored inside the CSoC.When JTAG security is set, boundary scan opera-tions are still functional but bus transactionsthrough the JTAG unit are not functional. However,the security status bit can be read through theJTAG port.

System Reset events have no effect on the CSoConce it has been secured. However, the applica-tion reset sideband signal, RSTC, remains fullyfunctional in a secured CSoC. Following a RSTCpulse, the CPU restarts its operation from programlocation 0000H regardless of the security mode.All MCU Reset events remain functional.

Once set, these security bits can only be cleared byturning off the power. If the MIU security bit is set,the VSYS system voltage monitor level is ignoredand the CSoC will not access an external memoryvia the MIU port.

SSeeccuurree MMooddee TTiimmeedd AAcccceessss

Mnemonic: PROTECT Address: FF60h

The Secure Mode Timed Access (PROTECT) reg-ister controls the access to the E5's secure modebits. A separate timed access register (TA) con-trols the protected bits within the 8032 "Turbo" mi-crocontroller. To access protected bits, the usermust first write AAh to the PROTECT register.This must be immediately followed by a write of55h to PROTECT. This opens a window for threemachine cycles, during which time software canwrite to these protected bits.

The PROTECT returns FFh when read, but thisregister is rarely read.

49 www.triscend.com

There is unrestricted write access to this register, aread is not required.

SSeeccuurree MMooddee CCoonnttrrooll

- - - - - - MIU JTAG

7 6 5 4 3 2 1 0

Mnemonic: SECURITY Address: FF61h

SECURITY.7-2 are reserved bits and return a 0when read.

MIU, when set, prevents any access through theMIU port, including any microcontroller code fetchto external memory. Once set, this bit can only becleared by turning off the power.

JTAG, when set, prevents any access through theJTAG port. Once set, this bit can only be clearedby turning off the power.

A write cycle to the security register must be pre-ceded by two data-specific, back-to-back write op-erations to the Protect register. A write operationto the Protect register with a data pattern of AAhmust be followed by a write operation to the Protectregister with a data value of 55h. Any write cycledirected at a different CSI location or containing adifferent data pattern would reset the write protectmechanism. After both write cycles are detected inthe right order and match the above-specified datapatterns, a write to the Security register is enabledfor a single write cycle.

The JTAG secure and MIU secure bits are activehigh. Once set they can only be cleared by turningoff the power. The 8032 microcontroller can al-ways read the security register to determine or ver-ify that the part is secured.

SSiizzee ooff IInniittiiaalliizzaattiioonn DDaattaa

The size of the initialization data file depends onwhich E5 family device is used in the applicationand the initialization method used.

IInniittiiaalliizzaattiioonn DDaattaa SSiizzee

Each device has a predefined number of rows andcolumns of initialization information as shown inTable 26. The total data size is the product of thenumber of rows and columns.

Table 26. Initialization Data Size.Device Columns Rows Total BytesTE502 102 120 12,240TE505 102 208 21,216TE512 144 296 42,624TE520 186 384 71,424TE532 228 472 107,616

PPaarraalllleell MMooddee SSeeccoonnddaarryy IInniittiiaalliizzaattiioonn PPrrooggrraamm

The secondary initialization program loads an E5device with the initialization data. The initializationprogram consists of 8032 instructions. The totalsize of the secondary initialization data image forparallel mode operation consists of

! 967 bytes of 8032 instruction code to load theinitialization data into the E5 device

! 19 bytes of initialization data header and footerinformation

! the initialization data file from Table 26

! 94 bytes of 8032 instruction code to set up thedata and code mappers after loading the initiali-zation data.

Because the secondary initialization program al-ways resides within the top 256 Kbytes of externalmemory, aligned to a 16K boundary, the absolutesize of the data is larger than actual data file.Table 27 shows the total size of the secondary ini-tialization data, including the initialization program,and the memory requirements once the initializa-tion data is aligned to a 16 Kbyte boundary.

Table 27. Parallel Mode Memory Requirements.

DeviceSecondary Init.

Data SizeTotal MemoryRequirements

TE502 13,320 16KTE505 22,296 32KTE512 43,704 48KTE520 72,504 80KTE532 108,696 112K

TTiimmee ttoo IInniittiiaalliizzee aann EE55 CCSSooCC DDeevviiccee

PPaarraalllleell IInniittiiaalliizzaattiioonn

The time to initialize an E5 device depends on thedevice used and the frequency of the bus clock.After power-on or after RST- is asserted, the E5device begins initialization clocked from the internalring oscillator. The frequency of the internal ringoscillator is minimum of 5 MHz and a maximum of20 MHz. During the initialization process, the busclock source can be switched over to an externalclock source or to the crystal oscillator amplifier,both of which operate up to 25 or 40 MHz, de-pending on the speed grade.

Table 28 shows the initialization time using variousfrequency bus clock inputs. If bus clock is clockedfrom the crystal oscillator amplifier, allow an addi-tional 5 ms for crystal settling time. If using thespecial 32 kHz mode for the crystal oscillator am-plifier, allow 200 ms settling time.


www.triscend.com 50

Table 28. Estimated Parallel Initialization Timesat Various Bus Clock Frequencies.

Bus Clock FrequencyDevice 1 MHz 5 MHz 25 MHz 40 MHzTE502 94 ms 19 ms 4.5 ms 3.1 msTE505 112 ms 23 ms 5.2 ms 3.6 msTE512 181 ms 37 ms 8.0 ms 5.3 msTE520 265 ms 54 ms 11.4 ms 7.4 msTE532 364 ms 73 ms 15.3 ms 9.9 ms

VVSSYYSS CCoonnttrrooll

A power-on reset or other device-wide resetcauses the Triscend E5 to start the initializationprocess as shown in Table 39. The VSYS input pindirects the system initialization state machine howto behave should the initialization process fail tofind valid external initialization data.

If the VSYS pin is held High through the initializa-tion phase and no valid configuration pattern isfound, then the CSoC automatically powers downto conserve power. Another Power-On Reset orSystem Reset event is required to restart the ini-tialization process.

However, if VSYS is sampled Low during the ini-tialization process, the CSoC will attempt to re-startthe initialization process following a failed initializa-tion attempt. The initialization mode, whether serialor parallel, is determined from the PMOD pin. IfVSYS is tied to GND, the CSoC will attempt recon-figuring itself indefinitely until it finds valid initializa-tion data. This option might be useful when thesystem operates in noisy environments.

In applications using a system supervisory chip, a“VCC good” output from the supervisory device canconnect to VSYS, ensuring that initialization onlytakes place when VCC is within the proper operat-ing voltage range.

If the MIU security bit is set, the VSYS level is ig-nored and the CSoC will not access an externalmemory via the MIU port.

Clocking and Global Signal Distribution

The Triscend E5 configurable system-on-chip pro-vides powerful, flexible clocking resources. A sys-tem-wide bus clock (BCLK) provides clocking tomost of the E5 device. In addition, six global buff-ers supply additional clocks or high-fanout signalsfor the CSL matrix.

SSyysstteemm cclloocckk sseelleecctt ((BBCCLLKK))

The system clock, called BCLK, supplies the clockto the 8032 “Turbo” microcontroller, its dedicatedresources, and to the CSI bus. Additionally, BCLKis distributed globally to the CSL matrix and to thePIO pins.

There are three potential user-defined sources forBCLK.

1. An internal ring oscillator operates at frequen-cies ranging between 5 MHz to 20 MHz, asshown in Figure 39. The ring oscillator fre-quency is temperature, voltage, and processdependent. The internal ring oscillator can beshut off during power-down mode by settingthe OSC bit (PWDSEL.3).

XTALINLeaveunconnected

BCLK

OSCPWDSEL.3

Internal RingOscillator

(~5 - 20 MHz)

Figure 39. Internal ring oscillator.

2. A crystal oscillator amplifier—connected inter-nally between the BCLK/XTAL and XTALOUTpins—supports 32 kHz operation and frequen-cies from 2 MHz up to 40 MHz, as shown inFigure 40. A crystal and the external circuitrylisted in Table 29 generate the desired fre-quency. The crystal oscillator amplifier alsosupports ceramic resonators. The crystal os-cillator output can be turned off during power-down mode by setting the XTAL bit(PWDSEL.4). Frequencies above 24 MHz re-quire the crystal to operate in the third over-tone. The crystal operates in its fundamentalmode at lower frequencies.

Table 29. Crystal Oscillator ExternalComponent Values.

CrystalFrequency

Range

SuggestedExternal

Resistor (R1)

ExternalCapacitor

(C1 and C2)32 kHz 10 MΩ 10 pF

2 MHz—24 MHz(fundamental) 1 MΩ 10 pF

24 MHz—40 MHz(third overtone) 4.7 kΩ 10 pF

C1

C2

XTAL

XTALIN

BCLK/XTALBCLK

XTALPWDSEL.4

R1

Figure 40. Crystal oscillator input.

51 www.triscend.com

3. A user-provided logic signal supplies the oper-ating clock frequency when applied to theXTAL input pin. The XTALOUT pin should beleft unconnected, as shown in Figure 41.

BCLK/XTAL

XTALIN

Clock input signal

Leaveunconnected

Figure 41. Clock input from external system.

The device always powers up using the internaloscillator, which serves as the system clock duringthe system initialization phase. The systemswitches over to the user selected clock sourcesometime before the MCU starts executing the ap-plication program. In most applications, the user-defined clock source is the crystal-oscillator clock(XTAL).

Two copies of the selected clock source propagatein the CSoC. The BCLK signal is shared by alldedicated resources connected to the CSI bus,including the MCU, DMA, mappers, programmablesystem decoders, etc. The CSL_BCLK propagatesinto the CSL matrix and optionally connects to pro-grammable CSL “soft” modules and PIO pins.

Usually, the system clock source is selected at de-sign time and unchanged by software. However,application code may need to modify the selectionif the crystal oscillator is turned off during power-down mode. See "Power-On Reset Control" formore information.

SSyysstteemm CClloocckk SSeelleecctt RReeggiisstteerr

- - - - - -SCPU_

ENABCLKSEL

7 6 5 4 3 2 1 0

Mnemonic: MISC Address: FE81h

MISC.7-2 are reserved locations that return 0 whenread.

SCPU_ENA, when set, releases the CPU resetcaused when the SLAVE- input is Low. Used onlyin Slave mode applications.

BCLKSEL, when set, selects the crystal oscillatoror an incoming, external clock source on the XTALinput pin. When cleared, then the internal ring os-cillator provides the system clock. When theSLAVE- pin is Low, the BCLKSEL bit is forced to 1.

SSiixx GGlloobbaall BBuuffffeerrss

In addition to system clock, there are six globalsignals available from within the CSL matrix. Thesix signals, GBUF[5:0], are buffered and provide ahigh-speed, low skew distribution path for addi-tional clocks or high-fanout signals.

CClloocckk aanndd GGlloobbaall SSiiggnnaall SSttooppppiinngg

The system clock and the outputs from the sixglobal buffers can be optionally stopped duringpower-down and debugging sessions.

BBuuss CClloocckk SSttooppppiinngg aanndd SSiinnggllee--SStteeppppiinngg

When stopped by a breakpoint event, the MCUcompletes the current instructions before stoppingthe bus clock, BCLK.

GGlloobbaall BBuuffffeerr SSttoopp VVaalluuee

The six global buffers have a selectable valuewhen stopped. During design, each global buffer isoptionally configured to one of the following func-tions.

1. Actively drive the global buffer, regardless of astop event.

2. Latch the last state of the global buffer anddrive the resulting value.

3. Force the buffer output Low.

8032 “Turbo” MicrocontrollerArchitecture

The 8032 "Turbo" microcontroller, embedded in theTriscend E5, is based on the standard 8032 device.The E5 is built around an 8-bit ALU that uses inter-nal registers for temporary storage and to controlperipheral devices. It executes the standard 8032instruction set. A brief description of the internalblocks follows.

AALLUU

The ALU is the heart of the 8032 microcontrollerand performs arithmetic and logical functions. Italso makes decisions for jump instructions, andcalculates jump addresses. The ALU is not directlyuser accessible, but the instruction decoder readsthe op-code, decodes it, and sequences the datathrough the ALU and its associated registers togenerate the required result. The ALU primarilyuses the ACC, which is a Special Function Register(SFR) on the chip. Another SFR, the B Register, isalso used in Multiply and Divide instructions. TheALU generates several status signals that arestored in the Program Status Word register (PSW).

AAccccuummuullaattoorr

The Accumulator (ACC) is the primary registerused in arithmetic, logical and data transfer opera-tions in the configurable system-on-chip. Since theAccumulator is directly accessible by the micro-controller, most of the high-speed instructions usethe ACC as one argument.


www.triscend.com 52

BB RReeggiisstteerr

This 8-bit register is used as the second argumentin the MUL and DIV instructions. For all other in-structions, it is simply a general-purpose register.

PPrrooggrraamm SSttaattuuss WWoorrdd

This is an 8-bit SFR that stores the status bits ofthe ALU. It holds the Carry flag, the Auxiliary Carryflag, General purpose flags, the Register BankSelect, the Overflow flag, and the Parity flag.

DDaattaa PPooiinntteerrss

MOVX instructions use the Data Pointers to trans-fer data to and from Data locations. These point-ers hold the address of the memory location towhich data is transferred. Because data can bemoved to and from external memory, the configur-able system-on-chip provides two separate DataPointers. The user can switch between either ofthe two Data Pointers with minimum softwareoverhead, greatly increasing system throughput.

SSccrraattcchh--ppaadd RRAAMM

The 8032 has a 256-byte scratchpad RAM withinthe microcontroller. Scratchpad RAM is useful fortemporary storage during program execution. Cer-tain sections of this RAM are bit addressable, anddirectly addressed by the 8032’s powerful Booleaninstructions.

SSttaacckk PPooiinntteerr

The 8032 has an 8-bit Stack Pointer that points tothe top of the Stack. The stack resides in thescratchpad RAM in the processor. Consequently,the size of the stack is limited by the size of thisRAM.

TTiimmeerrss//CCoouunntteerrss

The configurable system-on-chip has three 16-bitTimer/Counters. Each timer inhabits two SFR lo-cations that software can read or write. Other SFRlocations, associated with the timers, control theirmode and operation.

SSeerriiaall PPoorrtt

The 8032 microcontroller provides one serial I/Oport that operates in both synchronous and asyn-chronous modes. The serial port inhabits severalSFR locations.

MMeemmoorryy OOrrggaanniizzaattiioonn

The 8032, a classic Harvard architecture device,separates the memory into two sections, the pro-gram memory and the data memory. The programmemory stores the instruction op-codes, while thedata memory stores data values or accessesmemory-mapped devices.

PPrrooggrraamm MMeemmoorryy

The 8032 supports up to 64K bytes of programmemory. This memory space is either stored ex-ternally—typically in FLASH memory—or internallyusing the E5’s internal system RAM. All instruc-tions are fetched for execution from this memoryarea. The MOVC instruction also accesses thismemory region.

DDaattaa MMeemmoorryy

The 8032 supports up to 64K bytes of data mem-ory. This memory region is accessed by the MOVXinstructions. In addition, the 8032 microcontrollerhas 256 bytes of scratchpad RAM, plus can accessan additional 8K bytes to 64K bytes of internalsystem RAM—the memory size depends on thespecific device. Scratchpad RAM locations areaccessed either by direct addressing or by indirectaddressing. The microcontroller’s Special FunctionRegisters (SFRs) can only be accessed by directaddressing.

RReeggiisstteerr MMaapp

The 8032 has separate program and data memoryareas. The on-chip 256-byte scratchpad RAM is inaddition to the on-chip system RAM and any exter-nal memory. There are also several SFRs ac-cessed by software. The SFRs are only accessiblethrough direct addressing, while the on-chipscratchpad RAM is accessible through either director indirect addressing.

Since the scratchpad RAM, shown in Figure 42, isonly 256 bytes deep, it can be used only when datacontents are small. Larger amounts of data shouldbe stored either in the internal system RAM or inexternal data memory. However, on-chip systemRAM has faster access times than external RAM.There are several other special-purpose areaswithin the scratchpad RAM. These are describedas follows.

53 www.triscend.com

WWoorrkkiinngg RReeggiisstteerrss

There are four sets of working registers, each con-sisting of eight 8-bit registers. These are namedBanks 0, 1, 2, and 3. Individual registers withinthese banks are directly accessed by separate in-structions. These individual registers are namedas R0, R1, R2, R3, R4, R5, R6 and R7. However,the 8032 operates with only one particular bank ata time. One of the four banks is selected by settingthe RS1-RS0 bits in the PSW. The R0 and R1registers store the address for indirect accessing.

BBiitt AAddddrreessssaabbllee LLooccaattiioonnss

The scratchpad RAM area from location 20h to 2Fhis both byte- and bit-addressable. A bit within thisregion is individually addressed using the appropri-ate instruction. In addition, some of the SFRs arealso bit addressable. The instruction decoder is

able to distinguish a bit access from a byte accessby the type of the instruction itself. An SFR whoseaddress ends in a 0 or 8 is bit addressable.

SSttaacckk

The scratchpad RAM can be used for the stack.This area is selected using the Stack Pointer (SP),which stores the address of the top of the stack.Whenever a jump, call, or interrupt is invoked, thereturn address is placed on the stack. There is norestriction as to where the stack can begin in theRAM. By default however, the Stack Pointer con-tains 07h at reset, though the user can change thisto any desired value. The SP points to the lastused location. Therefore, the SP is incrementedand then address pushed onto the stack. Con-versely, while popping from the stack, the contentsare first read, and then the SP is decremented.

FFh

80h

Scratchpad RAM (Indirect Only)

SFR (Direct Only)7Fh

30h

Direct RAM

2Fh 7F 7E 7D 7C 7B 7A 79 782Eh 77 76 75 74 73 72 71 702Dh 6F 6E 6D 6C 6B 6A 69 682Ch 67 66 65 64 63 62 61 602Bh 5F 5E 5D 5C 5B 5A 59 582Ah 57 56 55 54 53 52 51 5029h 4F 4E 4D 4C 4B 4A 49 4828h 47 46 45 44 43 42 41 4027h 3F 3E 3D 3C 3B 3A 39 3826h 37 36 35 34 33 32 31 3025h 2F 2E 2D 2C 2B 2A 29 2824h 27 26 25 24 23 22 21 2023h 1F 1E 1D 1C 1B 1A 19 1822h 17 16 15 14 13 12 11 1021h 0F 0E 0D 0C 0B 0A 09 0820h 07 06 05 04 03 02 01 001Fh

18hBank 3

17h

10hBank 2

0Fh

08hBank 1

07h

00hBank 0

Figure 42. Scratchpad Register Addressing.


www.triscend.com 54

SSppeecciiaall FFuunnccttiioonn RReeggiisstteerrss

The 8032 uses Special Function Registers (SFRs)to control and monitor peripherals and their modes.

The SFRs reside in the locations 80-FFh and areaccessed by direct addressing only. Some of theSFRs are bit addressable. This allows a programto modify a particular bit without changing the oth-ers. The bit-addressable SFRs are those with ad-dresses that end in 0 or 8. The 8032 "Turbo" mi-crocontroller contains all the SFRs present in theoriginal 8032. However some previously unusedSFRs locations are added. The list of the SFRs isshown in Table 30 with eight locations per row.Empty locations indicate that these are no SFRregisters at these locations. When a bit or registeris not implemented, it returns a High when read.

A brief description of the SFRs now follows.

SSttaacckk PPooiinntteerr

SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0

7 6 5 4 3 2 1 0

Mnemonic: SP Address: 81h

The Stack Pointer points to the current top of thestack, located in the scratchpad RAM.

The SP SFR is set to 07h on any reset.

There is unrestricted read/write access to this SFR.

DDaattaa PPooiinntteerr ((LLooww BByyttee))

DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0

7 6 5 4 3 2 1 0

Mnemonic: DPL Address: 82h

This is the low byte of the standard 8032 16-bitdata pointer. The DPL is reset to 00h by a reset.


DDaattaa PPooiinntteerr ((HHiigghh BByyttee))

DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0

7 6 5 4 3 2 1 0

Mnemonic: DPH Address: 83h

This is the high byte of the standard 8032 16-bitdata pointer.

The DPH SFR is reset to 00h by a reset.


SSeeccoonndd DDaattaa PPooiinntteerr ((LLooww BByyttee))

DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0

7 6 5 4 3 2 1 0

Mnemonic: DPL1 Address: 84h

This is the low byte of the additional 16-bit datapointer added to the Triscend configurable system-on-chip. The user can switch between DPL/DPHand DPL1/DPH1 simply by setting the DPS bit(DPS.0) in the Data Pointer Select register. The

Table 30. Special Function Register (SFR) Locations.F8h EIPF0h BE8h EIEE0h ACCD8h WDCOND0h PSWC8h T2CON T2MOD RCAP2L RCAP2H TL2 TH2C0h TAB8h IP SADENB0h P3*A8h IE SADDRA0h P2*98h SCON SBUF90h P1*88h TCON TMOD TL0 TL1 TH0 TH1 CKCON80h P0* SP DPL DPH DPL1 DPH1 DPS PCON

indicates a bit-addressable location.

indicates an unused SFR register location, available for use by a “soft” module

Px* — the PIO ports P0 through P3 are implemented in CSL logic. Their SFR locations are exported. There arespecial precautions when exporting the P2 port (see Register Indirect Addressing section).

55 www.triscend.com

instructions using DPTR will then access DPL1 andDPH1 in place of DPL and DPH. If DPL1/DPH1 arenot used, then they can be used an conventionalregister locations.

The DPL1 SFR is reset to 00h by a reset.


SSeeccoonndd DDaattaa PPooiinntteerr ((HHiigghh BByyttee))

DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0

7 6 5 4 3 2 1 0

Mnemonic: DPH1 Address: 85h

This is the high byte of the additional 16-bit datapointer added to the Triscend configurable system-on-chip. The user can switch between DPL/DPHand DPL1/DPH1 simply by setting DPS = 1. Theinstructions using DPTR will then access DPL1 andDPH1 in place of DPL and DPH. If DPL1/DPH1 arenot used as a data pointer, then they can be usedas conventional register locations.

The DPH1 SFR is reset to 00h by a reset.


DDaattaa PPooiinntteerr SSeelleecctt

RESERVED (Reads = 0) DPS.0

7 6 5 4 3 2 1 0

Mnemonic: DPS Address: 86h

DPS.0 selects either the DPL/DPH pair or theDPL1/DPH1 pair as the active Data Pointer. Whenset to 1, DPL1/DPH1 is selected, else DPL/DPH isselected.

DPS.1-7 are reserved but will read 0.

The DPS SFR is reset to 00h by a reset and se-lects the standard DPTR by default.


PPoowweerr CCoonnttrrooll

SMOD SMOD0 - - GF1 GF0 PD IDL

7 6 5 4 3 2 1 0

Mnemonic: PCON Address: 87h

SMOD, when set, doubles the serial baud ratewhen the serial port is in Modes 1, 2, and 3.

SMOD0 is the Framing Error Detection Enable.When SMOD0 is set to 1, then SCON.7 indicates aFrame Error and acts as the FE flag. WhenSMOD0 is 0, then SCON.7 behaves as a standard8032 function.

GF1-0 are two general-purpose user flag bits.

Setting the PD bit causes the configurable system-on-chip to go into the power-down mode. In thismode, all the clocks are stopped and program exe-cution is halted. While in power-down mode, addi-

tional low-power options are enabled, controlled bythe PWDSEL. See "Clocking and Global SignalDistribution" for more details.

Setting the IDL bit causes the 8032 "Turbo" micro-controller to go into the IDLE mode. In this mode,the clock to the microcontroller is stopped, haltingprogram execution. However, the clock to the se-rial, timer and interrupt blocks is not stopped, andthese blocks continue operating unhindered.

The PCON SFR is reset to 00110000b by a reset.


TTiimmeerr CCoonnttrrooll

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

7 6 5 4 3 2 1 0

Mnemonic: TCON Address: 88h

TF1 is the Timer 1 overflow flag. This bit is setwhen Timer 1 overflows and is cleared automati-cally when the program executes a Timer 1 inter-rupt service routine. Software can also set or clearthis bit.

TR1 is the Timer 1 run control bit. This bit is set orcleared by software to turn Timer 1 on or off.

TF0 is the Timer 0 overflow flag. This bit is setwhen Timer 0 overflows and is cleared automati-cally when the program executes a timer 0 interruptservice routine. Software can also set or clear thisbit.

TR0 is the Timer 0 run control bit. This bit is set orcleared by software to turn Timer 0 on or off.

IE1 is the Interrupt 1 edge-detect flag. It is set byhardware when an edge/level is detected on theINT1 sideband signal. This bit is cleared by hard-ware when the service routine is vectored to only ifthe interrupt was edge triggered. Otherwise, ittracks the value that appears on the INIT1 side-band signal.

NOTE: The polarity of the external interrupt sig-nals, INT0 and INT1, are opposite that ofthe original 8032. In the original 8032,these signals are falling-edge triggeredor active-Low level. In the E5 family,these signals are rising-edge triggered oractive-High level.

IT1 is the Interrupt 1 type control bit. It is set bysoftware to specify a rising-edge trigger, cleared tospecify an active-High level-triggered external in-put.

IE0 is the Interrupt 0 edge-detect flag. It is set byhardware when an edge/level is detected on theINT0 sideband signal. This bit is cleared by hard-ware when the service routine is vectored to only ifthe interrupt was edge triggered. Otherwise, it


www.triscend.com 56

tracks the value that appears the INIT0 sidebandsignal.

IT0 is the Interrupt 0 type control bit. It is set bysoftware to specify a rising-edge trigger, cleared tospecify an active-High level-triggered external in-put.

The TCON SFR is reset to 00h by a reset.


TTiimmeerr MMooddee CCoonnttrrooll

GATE C/T M1 M0 GATE C/T M1 M0

7 6 5 4 3 2 1 0

Timer 1 Timer 0

Mnemonic: TMOD Address: 89h

GATE is the Gating control bit. When this bit is set,Timer/counter x is enabled only while INTx pin ishigh and TRx control bit is set. When GATE iscleared, the TRx bit (TR0 for Timer 0, TR1 forTimer 1) enables the timer when set.

C/T is the Timer or Counter Select bit. Whencleared, the timer increments on internal clocks.When set, the timer counts high-to-low edges ofthe Tx (T0 for Timer 0, T1 for Timer 1) sidebandsignal.

Table 31. Timer 0 and Timer 1Mode Select Bits.

M1 M0 Mode0 0 Mode 0: 8-bits with 5-bit pre-scaler.0 1 Mode 1: 16-bits, no pre-scaler.

1 0Mode 2: 8-bits with auto-reload fromTHx

1 1

Mode 3: (Timer 0) TL0 is an 8-bittimer/counter controlled by the Timer 0control bits. TH0 is a 8-bit timer onlycontrolled by Timer 1 control bits.(Timer 1) Timer/counter is stopped.

M1 and M0 are the Mode Select bits. They controlthe operation of the Timer/Counter as defined inTable 31.

The TMOD is reset to 00h by a reset.


TTiimmeerr 00 LLSSBB

Mnemonic: TL0 Address: 8Ah

TL0.7-0 is the least-significant byte of Timer 0.

The TL0 SFR is set to 00h on any reset.



Mnemonic: TL1 Address: 8Bh

TL1.7-0 is the least-significant byte of Timer 1.



TTiimmeerr 00 MMSSBB

Mnemonic: TH0 Address: 8Ch

TH0.7-0 is the most-significant byte of Timer 0.

The TH0 SFR is set to 00h on any reset.



Mnemonic: TH1 Address: 8Dh

TH1.7-0 is the most-significant byte of Timer 1.



CClloocckk CCoonnttrrooll

WD1 WD0 T2M T1M T0M - - -

7 6 5 4 3 2 1 0

Mnemonic: CKCON Address: 8Eh

WD1-0 are the Watchdog timer mode select bits.These bits determine the time-out period for thewatchdog timer. For all four of the time-out op-tions, the reset time-out is 512 clocks after the in-terrupt time-out period, as shown in Table 32.

Table 32. Watchdog Timer Modes.

WD1 WD0Interrupttime-out

Resettime-out

0 0 217 217 + 512

0 1 220 220 + 512

1 0 223 223 + 512

1 1 226 226 + 512

T2M is the Timer 2 clock select bit. When T2M isset to 1, Timer 2 uses a divide-by-4 clock. Whenset to 0, Timer 2 uses an 8032-compatible divide-by-12 clock.



CKCON.2-0 are reserved.

The CKCON SFR is set to 00h on any reset.


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SSeerriiaall PPoorrtt CCoonnttrrooll

SM0/FE SM1 SM2 REN TB8 RB8 TI RI

7 6 5 4 3 2 1 0

Mnemonic: SCON Address: 98h

SM0/FE performs as either Serial port, Mode 0 bitor as the Framing Error Flag. The SMOD0 bit inPCON SFR determines whether this bit acts asSM0 or as FE. The operation of SM0 is describedin Table 33.

When used as FE, this bit is set to indicate an in-valid stop bit. Software must clear the FE condition.

SM1 is the Serial port Mode bit 1.

SM2 is the Serial port Mode bit 2, which controlsmultiple MCU communication. Setting this bit en-ables the multiprocessor communication feature inMode 2 and 3. In Mode 2 or 3, if SM2 is set, thenRI is not activated if the received 9th data bit (RB8)is 0. In Mode 1, if SM2 = 1, then RI is only acti-vated if a valid stop bit is received. In Mode 0, theSM2 bit controls the serial port clock. If cleared,then the serial port runs at 1/12 the system clockfrequency, providing compatibility with the standard8032. When set, the serial clock is 1/4 the systemclock frequency, resulting in faster synchronousserial communication.

Table 33. Serial Mode Control Values.

SM0 SM1 ModeDescrip-

tion Length Baud rate

0 0 0 Synch. 8BUSCLK÷4/÷12

0 1 1 Asynch. 10 variable

1 0 2 Asynch. 11BUSCLK÷64/÷32

1 1 3 Asynch. 11 variable

REN is the Receiver enable bit. Setting this bit to 1enables serial reception, else reception is disabled.

TB8 is the 9th bit to be transmitted in Modes 2 and3. This bit is set and cleared by software as de-sired.

RB8 is the received 9th data bit in Modes 2 and 3.In mode 1, if SM2 = 0, RB8 is the received stop bitvalue. In Mode 0, it has no function.

TI is the Transmit interrupt flag. This flag is set byhardware at the end of the 8th bit time in mode 0,or at the beginning of the stop bit in all other modesduring serial transmission. This bit must becleared by software.

RI is the Receive interrupt flag. This flag is set byhardware at the end of the 8th bit time in mode 0,or halfway through the stop bits time in the othermodes during serial reception. However, the re-striction on SM2 applies on this bit. This bit can becleared only by software

The SCON SFR is set to 00h by a reset.


SSeerriiaall DDaattaa BBuuffffeerr

Mnemonic: SBUF Address: 99h

SBUF.7-0 is the serial data, read from or written tothis location. It actually consists of two separate 8-bit registers. One is the receive register and theother is the transmit buffer.

Any read access gathers data from the receivedata buffer, while write transfers are to the transmitdata buffer.

The SBUF SFR is set to 00h by a reset.


IInntteerrrruupptt EEnnaabbllee

EA - ET2 ES ET1 EX1 ET0 EX0

7 6 5 4 3 2 1 0

Mnemonic: IE Address: A8h

EA, when set, is the global enable bit and enablesall interrupts. When cleared, this bit disables allinterrupts, except for HPINT.

IE.6 is an un-implemented bit. It returns a Highwhen read.

ET2, when set, enables the Timer 2 interrupt.

ES, when set, enables the Serial interrupt.


EX1, when set, enables External interrupt 1.


EX0, when set, enables External interrupt 0.

The IE SFR is set to 01000000b by a reset.


SSllaavvee AAddddrreessss

Mnemonic: SADDR Address: A9h

SADDR is used only during multiple MCU opera-tions involving the serial port.

SADDR is loaded with the given or broadcast ad-dress for the serial port if the E5 is used as a slaveprocessor during multiprocessor communications.

The SADDR SFR is set to 00h by a reset.


IInntteerrrruupptt PPrriioorriittyy

- - PT2 PS PT1 PX1 PT0 PX0

7 6 5 4 3 2 1 0

Mnemonic: IP Address: B8h

The IP.7-6 bits are un-implemented and return aHigh when read.


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PT2, when set, defines the Timer 2 interrupt as ahigher priority interrupt.

PS, when set, defines the Serial port interrupt as ahigher priority interrupt.

PT1, when set, defines the Timer 1 interrupt as ahigher-priority interrupt.

PX1, when set, defines the External Interrupt 1 asa higher-priority interrupt.

PT0, when set, defines the Timer 0 interrupt as ahigher-priority interrupt.

PX0, when set, defines External Interrupt 0 as ahigher-priority interrupt.

The IP SFR is set to 11000000b by a reset.


SSllaavvee AAddddrreessss MMaasskk EEnnaabbllee

Mnemonic: SADEN Address: B9h

The SADEN register enables the Automatic Ad-dress Recognition feature of the Serial port. Whena bit in the SADEN is set to 1, the same bit locationin SADDR is compared with the incoming serialport data. When SADEN is 0, then the bit becomesa don’t-care in the comparison. When all the bitsof SADEN are 0, an interrupt occurs for any in-coming address.

The SADEN SFR is set to 00h by a reset.


TTiimmeedd AAcccceessss

Mnemonic: TA Address: C7h

The Timed Access (TA) register controls the ac-cess to protected Watchdog controller bits in the8032 microcontroller. A separate timed accessregister (PROTECT) supports the secure initializa-tion mode. To access protected bits, applicationsoftware must first write AAh to the TA SFR. Thismust be immediately followed by a write of 55h toTA. This opens a window for three machine cy-cles, during which time software can write to theseprotected bits.

The TA returns FFh when read.

There is unrestricted write access to this SFR, aread is not required.

Example:

MOV TA, 0AAH ; Write ‘AA’ followed by ‘55’ to open; window

MOV TA, 055H ; Window now open for three machine; cycles

SETB RWT ; Reset watchdog timer

TTiimmeerr 22 CCoonnttrrooll

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2

7 6 5 4 3 2 1 0

Mnemonic: T2CON Address: C8h

TF2 is the Timer 2 overflow flag. This bit is setwhen Timer 2 overflows. It is also set when thecount equals the capture register value while indown count mode. It can be set only if RCLK andTCLK are both 0. It is only cleared by software.Software can also set or clear this bit.

EXF2 is the Timer 2 External Flag. A falling-edgetransition on the T2EX sideband signal or a Timer2 underflow/overflow condition sets this flag basedon the CP/RL2, EXEN2 and DCEN bits. If set by afalling-edge transition, this flag must be cleared bysoftware. Setting this bit in software or a detectedfalling-edge transition on T2EX pin forces a timerinterrupt, if enabled.

RCLK is the Receive clock flag. This bit deter-mines the serial port timebase when receiving datain serial modes 1 or 3. If this bit is 0, then Timer 1overflow is used for baud rate generation, elseTimer 2 overflow is used. Setting this bit forcesTimer 2 into baud-rate generator mode.

TCLK is the Transmit clock flag. This bit deter-mines the serial port timebase when transmittingdata in serial modes 1 and 3. If it is set to 0, theTimer 1 overflow is used to generate the baud rateclock, else Timer 2 overflow is used. Setting thisbit forces Timer 2 into baud-rate generator mode.

EXEN2 is the Timer 2 External Enable bit. This bitenables the capture/reload function on the T2EXsideband signal if Timer 2 is not generating baudclocks for the serial port. If this bit is 0, then theT2EX sideband signal is ignored, else a falling-edge transition detected on the T2EX sidebandsignal results in capture or reload.

TR2 is the Timer 2 Run Control bit. This bit en-ables/disables the operation of Timer 2. HaltingTimer 2 by clearing this bit preserves the currentcount value in TH2, TL2.

C/T2 is the Counter/Timer select bit. This bit de-termines whether Timer 2 functions as a timer(counting clock cycles) or as a counter. Independ-ent of this bit, the timer runs at 2 clocks per tickwhen used in baud rate generator mode. If it is setto 0, then Timer 2 operates as a timer at a speeddepending on T2M bit (CKCON.5). Otherwise, itcounts falling edges on the T2 sideband signal.

CP/RL2 is the Capture/Reload Select bit. This bitdetermines whether the capture or reload functionis used for Timer 2. If either RCLK or TCLK is set,this bit will not function and the timer will function inan auto-reload mode following each overflow. Ifthe bit is 0, then auto-reload occurs whenever

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Timer 2 overflows or a falling edge is detected onT2EX if EXEN2 = 1. If this bit is 1, Then Timer 2captures happen whenever a falling edge is de-tected on T2EX if EXEN2 = 1.

The T2CON is reset to 00h by a reset.


TTiimmeerr 22 MMooddee CCoonnttrrooll

- - - - - - - DCEN

7 6 5 4 3 2 1 0

Mnemonic: T2MOD Address: C9h

DCEN is the Down Count Enable bit. This bit, inconjunction with the T2EX sideband signal controlsthe direction that Timer 2 counts in 16-bit auto-reload mode.

When DCEN is set, Timer 2 counts up or down,controlled by the T2EX sideband signal. WhenHigh, T2EX causes Timer 2 to increment. WhenLow, Timer 2 decrements. When DCEN=0, Timer2 only counts up.

The T2MOD is reset to FEh by a reset.


TTiimmeerr 22 CCaappttuurree LLSSBB

Mnemonic: RCAP2L Address: CAh

RCAP2L is the least-significant byte of the Timer 2capture register. This register is used to capturethe TL2 value when a Timer 2 is configured incapture mode. RCAP2L is also used as the least-significant byte of a 16-bit reload value when Timer2 is configured in auto-reload mode.

The RCAP2L SFR is set to 00h on any reset.


TTiimmeerr 22 CCaappttuurree MMSSBB

Mnemonic: RCAP2H Address: CBh

RCAP2H is the least-significant byte of the Timer 2capture register. This register is used to capturethe TH2 value when a Timer 2 is configured incapture mode. RCAP2H is also used as the most-significant byte of a 16-bit reload value when Timer2 is configured in auto-reload mode.

The RCAP2H SFR is set to 00h on any reset.



Mnemonic: TL2 Address: CCh

TL2 is the least-significant byte of Timer 2.




Mnemonic: TH2 Address: CDh

TH2 is the most-significant byte of Timer 2.



PPrrooggrraamm SSttaattuuss WWoorrdd

CY AC F0 RS1 RS0 OV F1 P

7 6 5 4 3 2 1 0

Mnemonic: PSW Address: D0h

CY is the Carry flag. This bit is set by arithmeticoperations that generate a carry in the ALU. It isalso used as the accumulator for the bit operations.

AC is the Auxiliary carry bit. This bit is Set whenthe previous operation resulted in a carry during anaddition operation or resulted in a borrow during asubtraction from the high order nibble.

F0 is User flag 0, a general-purpose flag that canbe set or cleared by the user by software.

RS.1-0 select the active Register bank as shown inTable 34.

Table 34. Register Bank Select.

RS1 RS0Register

bank Address0 0 0 00-07h0 1 1 08-0Fh1 0 2 10-17h1 1 3 18-1Fh

OV is the Overflow flag. Set by arithmetic opera-tions. Indicates that two most significant accumu-lator bits are different. Used primarily with signedor twos-compliment data to indicate that the arith-metic operation overflowed the accuracy of the ac-cumulator.

F1 is User Flag 1, a general-purpose flag that canbe set or cleared by the user by software

P is the Parity flag. This bit is set or cleared byhardware to indicate odd/even number of 1’s in theaccumulator.

The PSW SFR is set to 00h by a reset.


WWaattcchhddoogg CCoonnttrrooll

- POR EHPI HPI WDIF WTRF EWT RWT

7 6 5 4 3 2 1 0

Write protected by Timed-Access (TA) register

Mnemonic: WDCON Address: D8h


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WDCON.7 is un-implemented and returns a Highwhen read.

POR is the Power-On Reset flag. Hardware setsthis flag on a power-up condition. This flag can beread or written by software. A write by software isthe only way to clear this bit once it is set.

EHPI is the Enable High-Priority Interrupt bit.When set to 1, this bit enables the High-PriorityInterrupt. If cleared, then the high-priority side-band signal (HPINT) is ignored.

HPI is the High-Priority Interrupt flag. This flag isset by hardware whenever the high-priority side-band signal (HPINT) is asserted. Software mustclear this bit. Writing a 1 to this bit forces an inter-rupt if the EHPI bit is also set.

NOTE: Some of the bits in the Watchdog Controlregister (WDCON) are protected. Theycannot be accidentally overwritten by anerrant program. Before attempting tochange the RWT, EWT, WDIF, or PORbits, you must write the proper sequenceto the Timed Access (TA) register.

WDIF is the Watchdog Timer Interrupt Flag. If thewatchdog interrupt is enabled, hardware sets thisbit to indicate that a watchdog interrupt occurred. Ifthe interrupt is not enabled, then this bit indicatesthat the time-out period has elapsed.

WTRF is the Watchdog Timer Reset Flag. Hard-ware sets this bit whenever the watchdog timercauses a reset. Software must clear this bit. APower-On or System Reset event also clears thebit. This bit helps software to determine the causeof a reset. If EWT = 0, the watchdog timer has noaffect on this bit.

EWT is the Enable Watchdog Timer reset. Settingthis bit enables the Watchdog Timer Reset func-tion.

RWT is the Reset Watchdog Timer bit. This bitforces the watchdog timer into a known state. Set-ting this bit via software resets the watchdog timer,usually before a watchdog time-out occurs. If theRWT bit is not set before a watchdog time-outhappens, then two possible subsequent eventsoccur. If a watchdog time-out occurs while theEWDI (EIE.4) interrupt enable bit is set, then awatchdog interrupt results. If a watchdog time-outoccurs, then 512 clock cycles later, the WatchdogTimer resets the MCU if EWT is set. Setting RWTduring this 512 clock period resets the WatchdogTimer, avoiding the MCU reset. This bit is self-clearing.

The WDCON SFR is set to a 1x0x0xx0b on anexternal reset, an 'x' indicating a bit unaffected byreset. WTRF is set to a 1 on a Watchdog timerreset, but to a 0 on power on/down resets. WTRF

is not altered by an external reset. POR is set to 1by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.

All the bits in this SFR have unrestricted read ac-cess. POR, EWT, WDIF and RWT require timedaccess write. The remaining bits have unrestrictedwrite accesses.

AAccccuummuullaattoorr

Mnemonic: ACC Address: E0h

ACC.7-0, the A or ACC register, is the standard8032 accumulator

The ACC is reset to 00h on any reset

This SFR has unrestricted read/write access.

EExxtteennddeedd IInntteerrrruupptt EEnnaabbllee

- - - EWDI - - - -

7 6 5 4 3 2 1 0

Mnemonic: EIE Address: E8h

EIE.7-5 are reserved bits and return a High whenread.

EWDI enables the Watchdog timer interrupt.

EIE.3-0 are reserved bits and return a High whenread.

The EIE SFR is set to 11101111b on any reset.


EExxtteennddeedd IInntteerrrruupptt PPrriioorriittyy

- - - PWDI - - - -

7 6 5 4 3 2 1 0

Mnemonic: EIP Address: F8h

EIP.7-5 are reserved bits and return a High whenread.

PWDI, when set, defines the Watchdog timer as ahigher-priority interrupt.

EIP.3-0 are reserved bits and return a High whenread.

The EIP SFR is set to 11101111b on any reset.


Instruction Set

The Triscend configurable system-on-chip exe-cutes all the instructions of the standard 8032 fam-ily. The operation of these instructions, their effecton the flag bits and the status bits is exactly thesame. However, timing of these instructions isdifferent. The are two reasons for the timing differ-ences.

First, each 8032 “Turbo” microcontroller machinecycle takes 4 clock periods, while in the original8032 requires 12 clock periods. Second, the

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“Turbo” microcontroller only performs one fetch permachine cycle, i.e. 4 clocks per fetch. The stan-dard 8032 can require two fetches per machinecycle, or 6 clocks per fetch.

The 8032 "Turbo" microcontroller's advantage isthat there is only one fetch per machine cycle. Inmost cases, the number of machine cycles is equalto the number of operands required by the instruc-tion. Jumps and calls require an additional cycle tocalculate the new address. Overall, the 8032"Turbo" microcontroller reduces the number ofdummy fetches and wasted cycles, thereby im-proving efficiency compared to the original 8032.

AAddddrreessssiinngg MMooddeess

The 8032 microcontroller uses eight different ad-dressing modes. These modes are as follows, withdetailed descriptions below.

1. Register addressing

2. Direct addressing

3. Register Indirect addressing

4. Immediate addressing

5. Base register plus Index register Indirect ad-dressing

6. Relative addressing

7. Absolute addressing

8. Long addressing

RReeggiisstteerr AAddddrreessssiinngg

Register addressing uses the eight working regis-ters (R0-R7) of the current register bank located inthe scratchpad RAM. The last three bits in the in-struction op-code indicate the selected register.The current register bank is one of four registerbanks residing in the scratchpad RAM. The twobits RS1-RS0 in the Program Status Word (PSW)select the working bank. Consequently, the sameinstruction can access different registers simply byswitching between banks. ACC, B, the currentDPTR determined by DPS.0, and CY can also beaddressed as registers.

Example:

ADDC A, R2 ; Add Accumulator to register R2 with carry.

DEC R7 ; Decrement contents of register R7

CLR A ; Clear the Accumulator

SETB C ; Set the Carry flag (Boolean Processor; Accumulator)

DDiirreecctt AAddddrreessssiinngg

Direct addressing is the only method to refer to theSpecial Function Registers (SFRs). This modeaccesses the entire lower 128 bytes of theScratchpad RAM.

Direct addressing also applies to bit operations.The Scratchpad RAM area from 20h to 2Fh is bit-addressable. The bits in this area have their ownunique bit addresses from 00h to 7Fh. These bitsmay be addressed by directly specifying the bit ad-dress. Several SFRs are also bit addressable.The bits in these SFRs are addressed by addingthe bit position to the SFR address.

Example:

MOV 20h, 21h ; Move contents of RAM location 20h to; RAM location 21h

MOV P1, P3 ; Move data at Port 1 Pins to Port 3 latch

SETB 7Fh ; Set bit 7Fh in Scratchpad RAM. This is; actually MSB of the RAM location 2Fh.

MOV TR1, C ; Move carry flag contents to TR1 flag in; TCON SFR

RReeggiisstteerr IInnddiirreecctt AAddddrreessssiinngg

Register Indirect addressing mode uses the R0and R1 registers to store the address of the se-lected Scratchpad RAM location. By changing thecontents of R0 or R1, the same instruction will ad-dress different RAM locations. However, this ad-dressing mode is limited to the 128 bytes ofScratchpad RAM only (the upper 128 bytes). Spe-cial Function Registers (SFRs) cannot be ad-dressed by this method.

Example:

MOV R0, #20h ; Load register R0 with 20h

MOV A, @R0 ; Move contents of RAM location 20h to ; the Accumulator

Stack operations are also examples of RegisterIndirect addressing. In this case, the SFR StackPointer (SP) stores the address rather than theworking registers R0 and R1. Instructions likePUSH and POP use this mode of addressing.

Example:

PUSH TCON ; Save the contents of SFR TCON onto the; stack

POP DPL ; Loads the SFR DPL with the data at the; top of the stack

Data Memory may also be accessed using Regis-ter Indirect Addressing mode. The MOVX instruc-tions are used for this purpose. The registers R0,R1, DPTR or DPTR1 can be used as pointers forthis purpose. When using R0 and R1 as pointers,the lower 8-bits of the address are the contents ofR0 or R1, while the upper 8-bits of the address aresupplied by the P2 SFR. The P2 SFR must there-fore be set to the correct value before using thisinstruction. When using DPTR or DPTR1 as thepointer, then the entire 16-bit address is taken fromthe selected Data Pointer.


www.triscend.com 62

Example:

MOVX @R0, A ; Moves the Accumulator contents to the; external Data Memory locations pointed to; by R0 in the page pointed to by the P2; SFR.

MOVX A, @DPTR ; Move data from the Data Memory pointed: to by the selected Data Pointer, into the: Accumulator.

IImmmmeeddiiaattee AAddddrreessssiinngg

Immediate addressing is used when part of the op-code instruction is a constant. This method is mostcommonly used to initialize registers and SFRs orto perform mask operations.

Example:

MOV A, #40h ; Mov 40h to Accumulator

XRL SCON, #FFh ; Xor SCON SFR with FFh, thereby; complementing its contents

BBaassee RReeggiisstteerr pplluuss IInnddeexx RReeggiisstteerr IInnddiirreecctt AAdd--ddrreessssiinngg

This addressing mode provides access to a bytefrom the 8032's program memory—separate fromdata memory—via an indirect move. The addressof the move location is the sum of the base register(PC or DPTR/DPTR1) and an index register (ACC).The result is always written to the ACC, overwritingthe index value that previously resided there.

Example:

MOV DPTR, #1234h ; Data Pointer is loaded with constant; 1234h

MOV A, #23h ; Accumulator is loaded with index; value 23h

MOVC A, @A+DPTR ; Accumulator is loaded with byte from; the Program Memory at location; 1234h + 23h = 1257h

RReellaattiivvee AAddddrreessssiinngg

Relative Addressing is used to specify the destina-tion address for jumps within 128 bytes of the cur-rent program counter, common is short loopingfunctions.

The destination address is given in the form of atwo’s complement address offset that is added tothe PC. The relative address is one byte long, andso the offset will vary from -128 to +127.

Example:

SJMP 20h ; Jump to a location 20h bytes after the current; instruction. If the SJMP instruction is at; 1010h, then the jump will be to location; 1010h + 2h + 20h = 1032h

JZ FEh ; If the Accumulator is zero, then jump to the; same instruction ; If the JZ instruction is at; 2359h, then the jump will be to location; 2359h + 2h + FEh = 2359h + 2h - 2h = 2359h

AAbbssoolluuttee AAddddrreessssiinngg

Absolute addressing is used to specify the destina-tion address in ACALL and AJMP instructions. Theoperand is an 11-bit address within the current 2Kblock of program memory.

In this mode of addressing, the 16-bit address isgenerated by taking the five highest order bits ofthe next instruction (PC + 2) and concatenating thelowest order 11 bit field contained in the currentinstruction. The resulting addressed location lieswithin the 2K page of the Program Memory, relativeto the first byte of the instruction following the cur-rent instruction.

Example:

ACALL 0200h ; If the current instruction is at location; 7FFFh, then a call will be made to the; location 8200h

LLoonngg AAddddrreessssiinngg

Long addressing specifies the full 16-bit addressanywhere within the 64K program memory for theLJMP and LCALL instructions.

Example:

LJMP 8000h ; Jump to location 8000h in program memory.

Interrupts

The Triscend E5 has a three priority level interruptstructure with 12 interrupt sources. Each of theinterrupt sources has an individual flag, interruptvector and enable bit. The standard 8032 micro-controller interrupts have individual priority bits.Furthermore, the interrupts—with the exception ofthe High-Priority Interrupt—can be globally enabledor disabled.

IInntteerrrruupptt SSoouurrcceess

The external interrupt sideband signals, INT0 andINT1, are either edge triggered or level triggered,depending on bits IT0 and IT1 in the TCON regis-ter. The flag bits IE0 and IE1 in the TCON registergenerate the interrupt and indicate which interrupthas occurred. When an external interrupt inputgenerates an interrupt, the appropriated flag bit iscleared upon entering the Interrupt Service routine,but only if the interrupt type is edge triggered. Inlevel activated mode, the external requestingsource controls the interrupt flag bit rather than theon-chip hardware. For level-triggered interrupts,the IE0 and IE1 flags are not cleared by hardwareand must be cleared by the software.

The TF0 and TF1 flags generate the Timer 0 and 1Interrupts. These flags are set when Timer 0 andTimer 1 overflow, respectively. Hardware auto-matically clears the TF0 and TF1 flags when thetimer interrupt is serviced.

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The Timer 2 interrupt is generated by a logical ORof the TF2 and the EXF2 flags. These flags are setby overflow/underflow or capture/reload events inthe Timer 2 operation. The hardware does notclear these flags when a Timer 2 interrupt is exe-cuted. Software has to resolve the cause of theinterrupt between TF2 and EXF2 and clear the ap-propriate flag.

The Watchdog timer can be used as a systemmonitor or a simple timer. In either case, theWatchdog timer interrupt flag WDIF (WDCON.3) isset when the time-out count is reached. If the in-terrupt is enabled by the enable bit EIE.4, then aninterrupt occurs.

The serial port also generates interrupts on datareception or transmission. However, there is onlyone interrupt source from the Serial block, the logicOR of the RI and TI bits in the SCON SFR. Thesebits are not automatically cleared by the hardwareand the software must clear these bits.

The High-Priority Interrupt flag, HPI, (WDCON.4) isset when the HPINT sideband signal is asserted. Ifthis interrupt is enabled then an interrupt occurs.The high-priority interrupt has the highest priorityover all the interrupts. The user cannot alter itspriority but it can be enabled or disabled via soft-ware. The EHPI bit enables the high-priority inter-rupt. This bit is not controlled by the global inter-rupt enable EA.

The standard 8032 interrupt flags that generateinterrupts can be set or reset by writing to the ap-propriate registers. Consequently, software cangenerate interrupts. The addition E5 interrupts(DMA, JTAG, software and hardware breakpoint)can only by reset by software. Individual interruptscan be enabled or disabled by setting or clearing abit in the IE or the EIE SFR. IE also has a globalenable/disable bit, EA, which is cleared to disableall the interrupts at once, except for the high-priorityinterrupt (HPI), which is unaffected by EA.

PPrriioorriittyy LLeevveell SSttrruuccttuurree

There are three priority levels for the interrupts,highest, high and low. The high-priority interruptHPI has the highest priority. No other interrupt canhave this priority. Naturally, a higher priority inter-rupt cannot be interrupted by a lower priority inter-rupt. However there is a predefined hierarchyamong the interrupts themselves. This hierarchyhelps the interrupt controller to resolve simultane-ous requests having the same priority level.

There are three priority levels for the interrupts,highest, high and low. The high-priority interruptHPI has the highest priority. No other interrupt canhave this priority. Naturally, a higher priority inter-rupt cannot be interrupted by a lower priority inter-rupt. However there is a predefined hierarchy

among the interrupts themselves. This hierarchyhelps the interrupt controller to resolve simultane-ous requests having the same priority level.

Table 35. Priority structure of interrupts.

Source FlagPriorityLevel

PriorityBit

High-Priority HPI1

(high-est)

External Inter-rupt 0

IE0 2 &

Timer 0 Over-flow

TF0 3 &

External Inter-rupt 1

IE1 4 &

Timer 1 Over-flow

TF1 5 &

Serial PortRITI

6 &

Timer 2 Over-flow

TF2EXF2

7 &

DMA

OVR0INIT0TC0

OVR1INIT1TC1

8

HardwareBreakpoint

BP0IBP1I

9

JTAG JTAGI 10Software Break-point (A5 in-struction)

EA5 11

Watchdog Timer WDIF 12(lowest)

&

The default hierarchy is defined as shown Table35. The interrupts are numbered starting from thehighest priority to the lowest. Some of the inter-rupts have an individual priority bit that, when set,places those interrupts in a higher-priority category.

The default priority remains for interrupts placed inthe higher-priority category.

The interrupt flags are sampled in C2 of every ma-chine cycle. In the same machine cycle, the sam-pled interrupts are polled and their priority is re-solved. If certain conditions are met, then thehardware executes an internally generated LCALLinstruction that vectors the process to the appropri-ate interrupt vector address. The conditions forgenerating the LCALL are

1. An interrupt of equal or higher priority is notcurrently being serviced.

2. The current polling cycle is the last machinecycle of the instruction currently being exe-cuted.


www.triscend.com 64

3. The current instruction does not involve a writeto IP, IE, EIP or EIE registers and is not aRETI.

An LCALL is only generated if all of the conditionsare met. The polling cycle is repeated every ma-chine cycle, with the interrupts sampled in C2 ofthe same machine cycle. If an interrupt flag is ac-tive in one cycle but not responded to, and is notactive when the above conditions are met, the de-nied interrupt will not be serviced. This means thatactive interrupts are not remembered. Every poll-ing cycle is new.

Table 36. Interrupt Sources and Reset Method.InterruptSource Flag

Cleared byHardware

Cleared bySoftware

HPINT HPI &

INT0 IE0Edge-

triggeredLevel-

triggeredTimer 0 TF0 &

INT1 IE1Edge-

triggeredLevel-

triggeredTimer 1 TF1 &

SI &SerialPort TI &

Timer 2TF2EXF2

&

OVR0 &INIT0 &TC0 &OVR1 &INIT1 &

DMAController

TC1 &Watchdog WDIF &

The processor responds to a valid interrupt by exe-cuting an LCALL instruction to the appropriateservice routine. Hardware may or may not clearthe flag that caused the interrupt, as shown inTable 36. For Timer interrupts, the TF0 or TF1flags are cleared by hardware whenever the proc-essor vectors to the appropriate timer service rou-tine. With External interrupts, INT0 and INT1, theflags are cleared only if they are edge triggered.For Serial interrupts, the flags are not cleared byhardware. The ISR must poll to determine if thetransmitter or receiver generated the interrupt andclear the appropriate flags. With the Timer 2 inter-rupt, the flag is not cleared by hardware. ThePower-Fail Interrupt flag (PFI) and Watchdog timerinterrupt flag (WDIF) must be cleared by software.The hardware LCALL behaves exactly like thesoftware LCALL instruction. This instruction savesthe Program Counter (PC) contents onto the Stack,but does not save the Program Status Word(PSW).

The Program Counter (PC) is reloaded with thevector address of the interrupt that caused the

LCALL. The vector addresses for the differentsources are as shown in Table 37 Note that thevector addresses are not evenly spaced in mem-ory.

Table 37. Vector locations forinterrupt sources.

SourceVector

AddressKeil

Intr. #High-PriorityInterrupt

0x0033 6

External Interrupt 0 0x0003 0Timer 0 Overflow 0x000B 1External Interrupt 1 0x0013 2Timer 1 Overflow 0x001B 3Serial Port 0x0023 4Timer 2 Interrupt 0x002B 5DMA 0x003B 7HardwareBreakpoint

0x0043 8

JTAG 0x004B 9Software Breakpoint 0x0053 10Watchdog Timer 0x0063 12

Execution continues from the vectored addressuntil an RETI instruction is executed. On executingthe RETI instruction, the processor pops the Stackand loads the PC with the contents at the top of thestack. The user’s software must restore the stackto its values prior to the hardware LCALL whenexecution returns to the interrupted program. Allinterrupt service routines end with the Return FromInterrupt (RETI) instruction. Note that a RET in-struction performs like a RETI instruction, but itdoes not inform the Interrupt Controller when theinterrupt service routine is complete, leaving thecontroller to think that the service routine is in prog-ress.

EExxtteerrnnaall IInntteerrrruuppttss

There are three external interrupt sources in thisprocessor. The High-Priority Interrupt is suppliedvia the HPINT sideband signal. This interrupt haspriority over all other interrupts and typically con-nects to an external power-fail signal. The otherexternal interrupts are INT0 and INT1, also avail-able as sideband signals. These interrupts can beprogrammed to be edge triggered or level acti-vated, by setting bits IT0 and IT1 in TCON SFR.

NOTE: The polarity of the external interrupt sig-nals, INT0 and INT1, are opposite that ofthe original 8032. In the original 8032,these signals are falling-edge triggeredor active-Low level. In the E5 family,these signals are rising-edge triggered oractive-High level.

65 www.triscend.com

In the edge-triggered mode, the INT0 and INT1sideband signals are sampled at C4 in every ma-chine cycle. If the sample is Low in one cycle andHigh in the next, then a low-to-high transition isdetected and the interrupts request flag IE0 or IE1is set in the timer control register, TCON. The flagbit then requests the interrupt. Because externalinterrupts are sampled every machine cycle, theymust be held High or Low for at least one completemachine cycle. The interrupt service routine auto-matically clears the appropriate IE0 or IE1 flag.

In level activated mode, the requesting sourcemust hold the pin High until the interrupt is serv-iced. The IE0 or IE1 flag is not cleared by thehardware on entering the service routine.

If the interrupt continues to be held High—evenafter the service routine is completed—then theprocessor may acknowledge another interrupt re-quest from the same source.

RReessppoonnssee TTiimmee

The response time for each interrupt source de-pends on several factors like nature of the inter-rupt, the instruction currently executing, and wait-states on the CSI bus.

External interrupts INT0 and INT1 are sampled atC3 of every machine cycle and then their corre-sponding interrupt flags IE0 and IE1 are set or re-set. Similarly, the Serial port flags RI and TI areset in C3. The Timer 0 and 1 overflow flags are setat C3 of the machine cycle in which overflow hasoccurred. These flag values are polled only in thenext machine cycle. If a request is active and allthree conditions are met, then the hardware-generated LCALL is executed. This call itself takesfour machine cycles to complete.

Consequently, there is a minimum latency of fivemachine cycles between the time the interrupt flagis set and the interrupt service routine begins exe-cuting. A longer response time should be antici-pated if any of the following three conditions is met.

1. An interrupt of equal or higher priority is cur-rently being serviced.

2. The current polling cycle is not the last ma-chine cycle of the instruction currently beingexecuted.

3. The current instruction involves a write to IP,IE, EIP or EIE registers and is not a RETI.

If a higher or equal priority interrupt is being serv-iced, then the interrupt latency time depends on theservice routine currently executing. If the pollingcycle is not the last machine cycle of the instructionbeing executed, then an additional delay is intro-duced. The maximum response time—if no otherinterrupt is currently being serviced—occurs if the8032 is performing a write to IE, IP, EIE or EIP and

then executes a MUL or DIV instruction. From thetime an interrupt source is activated, the longestresponse time is 12 machine cycles. This includes

! 1 machine cycle to detect the interrupt,

! 2 machine cycles to complete the IE, IP, EIE orEIP access,

! 5 machine cycles to complete the MUL or DIVinstruction and

! 4 machine cycles to complete the hardwareLCALL to the interrupt vector location.

Thus in a single-interrupt system, the interrupt re-sponse time is always more than 5 machine cyclesbut not more than 12 machine cycles. The maxi-mum latency of 12 machine cycles is 48 clock cy-cles. In the original 8051, the maximum latency is8 machine cycles or 96 clock cycles. Conse-quently, the E5’s interrupt response time is twotimes faster than an average 8051.

Table 38. Interrupt Response Latency(Single-Interrupt System).

Minimum MaximumMachine Cycles 5 12Clock Cycles 20 48

Reset Conditions

Table 39. Reset Types and Affected Resources.RESET CONDITION

Po

we

r-O

n R

ese

t

RS

T-

Pin

JTA

G C

om

ma

nd

(FO

RC

E_

BR

ST

)A

pp

lica

tion

Re

set

(RS

TC

)W

atc

hd

og

Tim

er

Re

set

JTA

G C

om

ma

nd

(J_

RE

SE

T)

Device Resources Affected8032 “Turbo” MCU & & & & & &DMA Controller & & &MemoryInterface Unit (MIU)

& & &

ConfigurationRegisters (CRU)

& & &

Clock controlregisters

&

JTAG Unit &Post-Reset Behavior

(Re-) InitializeDevice

& & &

Begin ExecutingCode from 0000h

& & & & & &

Several possible conditions reset the Triscend E5configurable system-on-chip. Different resetsources affect the device differently.


www.triscend.com 66

For example, a Power-On Reset (POR) conditionresets all of the device functions including the 8032“Turbo” microcontroller, peripherals connected tothe internal CSI bus, many of the internal systemregisters (CRU), the clock logic, and the JTAG unit.

By contrast, asserting the RST- pin resets most ofthe device, but leaves the clock control registersand JTAG unit unaffected.

Finally, a watchdog reset or asserting the applica-tion reset sideband signal, RSTC, only affects theembedded 8032 microcontroller. All other systemlogic is unaffected.

Table 39 summarizes the various reset conditionsand the system resources that each affects. Thetable indicates how the device behaves after thereset. Some reset conditions cause the device tore-initialize and restart code execution from 0000h.Others merely restart code execution.

PPoowweerr--OOnn RReesseett ((PPOORR))

The on-chip analog circuitry continuously monitorsthe VCC levels and detects a power on or powerfail condition. As long as VCC is below the thresh-old VRST, the device remains in the reset condi-tion. Once VCC goes above the VRST level, theanalog circuit releases the reset.

On-chip logic generates a power-on reset (POR)when power is applied to the device, resetting alldevice resources that can be reset. POR is re-leased after a clock source is available (after thefirst two rising clock edges).

The software should clear the POR flag afterreading it, otherwise it will not be possible to cor-rectly determine future reset sources. If the powerfails, i.e. falls below VRST, then the device againgoes into the reset state. When the power returnsto the proper operating levels, the device againperforms a power on reset and sets the POR flag.

RRSSTT-- DDeevviiccee PPiinn

The RST- pin, when asserted Low, resets all inter-nal resources except for the clock control registersand the JTAG unit. The assertion of the reset isasynchronous but its de-assertion is automaticallysynchronized with bus clock signal, BCLK. A glitchfilter prevents glitches on the RST- pin lasting lessthan 2ns. RST- should always be asserted with asignal lasting more than 8 ns in duration.

The RST- pin can be disabled by two conditions.First, the RST- pin is ignored if the CSoC is placedin Secure mode by setting the MIU bit (SECU-RITY.0) in the Security register. This condition iscleared once power is removed from the device.Second, a FORCE_NOBRST command can beissued via the JTAG unit during debugging. This

JTAG-initiated condition is cleared once the com-mand is no longer asserted.

JJTTAAGG RReesseett

For debugging purposes, the JTAG unit can force aSystem Reset or an MCU Reset event. There arethree reset-related commands that can be issuedvia the JTAG unit.

1. J_RESET resets the MCU.

2. FORCE_BRST resets everything except theclock control registers and the JTAG unit.

3. FORCE_NOBRST disables the RST- pin, pre-venting the pin from causing a reset event.This function overrides FORCE_BRST.

AApppplliiccaattiioonn RReesseett vviiaa RRSSTTCC SSiiddeebbaanndd SSiiggnnaall

The reset input to the 8032 “Turbo” microcontrolleris supplied via an active-High sideband signalcalled RSTC. When asserted, RSTC resets theMCU but no other peripherals or system-relatedresources. The RSTC sideband signal is usuallysupplied by functions in the CSL matrix or from aPIO pin.

WWaattcchhddoogg TTiimmeerr RReesseett

The 8032 “Turbo” microcontroller contains awatchdog timer, typically used to insure propersystem operation. The Watchdog timer is a freerunning timer with programmable time-out inter-vals. The user’s software can clear the watchdogtimer at any time causing it to restart the count.When the timer reaches its time-out interval, aninterrupt flag is set. If the Watchdog reset is en-abled then the watchdog timer generates a resetunder the following condition.

1. If the watchdog timer reset is enabled by set-ting EWT (WDCON.1).

2. When the watchdog timer reaches its time-outcount.

3. If the application software does not reset theWatchdog timer by setting the RWT bit(WDCON.0) within 512 clock cycles after time-out.

A watchdog timer reset only resets the MCU. Thereset condition is maintained by hardware for twomachine cycles.

SSyysstteemm BBeehhaavviioorr aafftteerr aa RReesseett EEvveenntt

After a reset event, the system either re-initializesand re-starts code execution or just re-starts codeexecution, depending on the type of reset event.

RRee--IInniittiiaalliizzaattiioonn

Following some types of resets, as shown in Table39, the CSoC starts or re-starts the device initiali-zation process. The initialization process, de-

67 www.triscend.com

scribed separately in the "System Initialization"section, typically lasts tens to hundreds of millisec-onds, depending on the CSoC clock source andthe operating mode. After the E5 is fully initialized,the user application program begins executing frommicrocontroller address 0000h.

AAfftteerr MMCCUU RReesseett

After resetting the MCU, the MCU starts or re-starts executing the user application program from8032 code location 0000h. There are no other im-plications of an MCU Reset. An MCU Reset eventdoes not cause the device to re-initialize.

MMiiccrrooccoonnttrroolllleerr RReesseett SSttaattee

Most of the SFRs and registers on the device arecleared by reset. The Program Counter is forcedto 0000h and is held there as long as the resetcondition is applied. The reset state however doesnot affect the on-chip RAM. The data in the RAMis preserved during the reset. However, the stackpointer is reset to 07h, and therefore the stackcontents are lost. However, the RAM contents willbe lost if the Vcc falls below approximately 2V, asthis is the minimum voltage level required for theRAM to operate normally. Therefore, after a first-time power on reset, the RAM contents are inde-terminate. During a power fail condition, if thepower falls below 2V, the RAM contents are lost.After a power on/fail reset, POR = 1, the RAMcontents should be assumed lost.

Table 40. SFR Reset Conditions.

SFR Name Reset ValueACC 00000000b

B 00000000bCKCON 00000001b

DPH 00000000bDPH1 00000000bDPL 00000000bDPL1 00000000bDPS 00000000bEIE 11101111bEIP 11101111bIE 01000000bIP 11000000bP0 11111111bP1 11111111bP2 11111111bP3 11111111bPC 0000h

PCON 00110000bPSW 00000000b

RCAP2H 00000000bRCAP2L 00000000bSADDR 00000000bSADEN 00000000b

SFR Name Reset ValueSBUF 11111111bSCON 00000000b

SP 00000111bT2CON 00000000bT2MOD 11111110b

TA 11111111bTCON 00000000bTH0 00000000bTH1 00000000bTH2 00000000bTL0 00000000bTL1 00000000bTL2 00000000b

TMOD 00000000b

When reset, most SFRs are cleared, as shown inTable 40. Interrupts and Timers are disabled.

The Watchdog timer is disabled by a Power-OnReset (POR). The WDCON SFR bits are set orcleared in reset condition depending on the sourceof the reset, as shown in Table 41.

Table 41. Watchdog Timer Reset Values.

ExternalReset

WatchdogReset

Power-onReset

WDCON 1x0x0xx0b 1x0x01x0b 11000000b

An 'x' indicates that the reset does not change thebit. The POR bit WDCON.6 is set only by thepower on reset. The PFI bit WDCON.4 is set whenthe power fail condition occurs. However a power-on reset clears this bit if Vcc> Vpfw following thecrystal start-up time. The WTRF bit WDCON.2 isset when the Watchdog timer causes a reset. Apower-on reset also clears this bit. The EWT bitWDCON.1 is cleared by power-on resets. This dis-ables the Watchdog timer resets. A watchdog orexternal reset does not affect the EWT bit.

Power Management

The Triscend E5 configurable system-on-chip hasseveral features that reduce power consumption,including two power saving modes, Power-Downand Idle. A power-on/power-fail reset guaranteesproper start-up or restart operation.

PPoowweerr MMaannaaggeemmeenntt

The Triscend E5 configurable system-on-chip hasa built-in power-on reset system. This ensures thatif the power levels are below the VRST level, thedevice is forced into the reset state. When poweris turned on—such as during a cold reset—the de-vice is reset automatically and remains so as longas VCC is less that VRST. Similarly, when powerfalls below VRST, the device is automatically reset.


www.triscend.com 68

This eliminates the need for any external reset cir-cuitry.

PPoowweerr SSaavviinngg

The Triscend E5 has two power saving modes ofoperation, the Power Down mode and the Idlemode. These two modes are possible because theE5 is implemented in fully static CMOS logic. Thispermits the device to reduce the clock speed toDC. In the most aggressive power down state,where subsystems are properly shut down orblocked, the overall current can be reduced to atypical value of less than 50 µA.

IIddllee MMooddee

The Idle mode is primarily provided for compatibilitywith the original 8032 microcontroller. The deviceis placed in Idle mode by setting the IDL bit(PCON.0). The instruction that sets the idle bit isthe last instruction executed before the device goesinto Idle mode.

In the Idle mode, the MCU clock is disabled. How-ever, the interrupt controllers, timers, watchdogtimer, and serial port continue to operate. Idlemode freezes the MCU state including the ProgramCounter, the Stack Pointer, the Program StatusWord, and the Accumulator. The other registersretain their contents.

There are two ways to exit Idle mode. Because theinterrupt controller remains active, asserting anyenabled interrupt wakes up the processor. Thisautomatically clears the Idle bit, terminates the Idlemode, and executes the appropriate interruptservice routine (ISR). After the ISR, the programcontinues to execute from the instruction followingthe instruction that placed device into Idle mode.

An alternate method to exit the Idle mode is byforcing a reset condition. The device is reset byeither applying a Low on the external RST- pin, aPower on/fail reset condition, a Watchdog timerreset, or asserting an application reset using theRSTC sideband signal. Some reset conditionscause the Triscend E5 device to re-initialize beforere-starting code execution from 0000h. See the"System Initialization" section for more informa-tion.

After a reset condition, the program counter is re-set to 0000h and all the SFRs are set to the resetcondition. Because the clock is already running,there is no delay and execution starts immediately.In the Idle mode, the Watchdog timer continues torun, and if enabled, a time-out will cause a watch-dog timer interrupt, which will wake up the device.The software must reset the Watchdog timer inorder to preempt the reset, which will occur 512clock periods after the time-out. When the MCUexits from the Idle mode with a reset, the instruc-

tion following the one which put the device into Idlemode is not executed..

PPoowweerr--DDoowwnn MMooddee

The device is placed into power-down mode bysetting the PCON.1 bit. The instruction that setsthis bit is the last instruction executed before thedevice goes into power-down mode. In power-down mode, all clocks are optionally stopped andinternal functions optionally disabled. All activity iscompletely stopped and the power consumption isreduced to the lowest possible value.

The power down control logic optionally preventsthe global clock signals from toggling when theMCU powers down. The PWDSEL defines thesystem behavior when the system enters the powerdown mode.

The MCU is powered down following the executionof an instruction that set the PD flag inside itsPCON register. The MCU exits power down by areset pulse or by responding to an external inter-rupt, as described later.

Prior to entering a power down state, the applica-tion program configures PWDSEL with settings thatbest fits the particular application.

PPoowweerr DDoowwnn SSeelleecctt

- - PIO XTAL OSC GBUFCSL

BCLKBCLK

7 6 5 4 3 2 1 0

Mnemonic: PWDSEL Address: FF62h

PIO, when set, signals all of the PIO pins when apower-down event occurs. Within each PIO, user-defined values configure the PIO to optionally blockinputs by driving a High value. In addition, the out-put driver is optionally three-stated, turning on theweak-follower feature. The individual PIO controlsare loaded during device initialization.

XTAL, when set, blocks the external oscillator dur-ing power down mode. BCLK is frozen in its Highstate. Note that the memory interface unit (MIU)must be set up correctly to properly exit powerdown mode, as described later.

OSC, when set, shuts off the internal oscillatorduring power down mode.

GBUF, when set, signals the six global bufferswhen a power-down event occurs. Each globalbuffer has individual control bits that define its be-havior during a power down or breakpoint event.

CSL_BCLK, when set, blocks the bus clock into theconfigurable system logic (CSL) matrix duringpower-down mode.

BCLK, when set, blocks the bus clock duringpower-down mode.

69 www.triscend.com

Power down mode is initiated by writing a “1” to thepower down bit in the microcontroller’s PCON SFR.Depending on what portions of the device are se-lected for shut down or blocking, the effect is im-mediate. However, special attention is requiredwhen exiting power down mode after shutting offthe crystal oscillator.

PPoowweerr--OOnn RReesseett CCoonnttrrooll

- - - - - - - PORCT

7 6 5 4 3 2 1 0

Mnemonic: PORCTRL Address: FF63h

PORCT, when set, disables the Power-On Reset(POR) circuitry during power-down mode. Clearingthis bit keeps the POR circuitry active.

Power down mode is initiated by writing a “1” to thepower down bit in the microcontroller’s PCON SFR.

SShhuuttttiinngg DDoowwnn tthhee CCrryyssttaall OOsscciillllaattoorr

If the external crystal is selected to drive the inter-nal system clock (BCLK), it can be shut down dur-ing power-down by setting the XTAL bit. However,if the crystal oscillator is shut down, the deviceautomatically selects the internal ring oscillator asthe default clock source upon exiting power downmode. Consequently, if the user program fetchesinstructions via the MIU when leaving powerdown—the usual case—potential timing problemscould occur if the frequency of the internal ring os-cillator is greater than the frequency of the externalcrystal. Before entering power down mode, theuser application code must properly configure theMIU’s external memory timing with values that aremore conservative. See Table 42 for more details.

RReessttaarrttiinngg tthhee CCrryyssttaall OOsscciillllaattoorr aafftteerr EExxiittiinnggPPoowweerr--DDoowwnn MMooddee

If the crystal oscillator is disabled during powerdown, then the internal ring oscillator becomes theclock source for the bus clock, BCLK.

Before switching back to the crystal oscillator, theuser program must wait for the crystal oscillator tostabilize. This can be accomplished either by asoftware timing loop or by using one of the MCUtimers. Once the necessary time has elapsed, theuser program must switch back to the externalcrystal and set the MIU read timing parameters tothe pre-power-down values.

Table 42 summarizes the sequence for enteringand exiting power down mode, when turning off thecrystal oscillator during power-down mode. Themethod used depends on the crystal frequency.With the crystal shut off, the device wakes frompower-down mode using the internal ring oscillator.The sequences in Table 42 represent the cases

where the crystal is faster and slower than the in-ternal ring oscillator.

The registers accessed in Table 42 are MIUCTRLand MISC. MIUCTRL controls the MIU timing andMISC contains the clock select bit. These registersare configuration register (CRU) bits. The CRUblock size must be set to 4K bytes in order to en-able access to these registers by clearing theDMAP3_CTL.0 bit.

Table 42. MIU Timing Considerations forPowering Down the Crystal Oscillator.

XTALFreq.

Power DownSequence

Exit power downsequence

< 20MHz

Add more cy-cles to MIU readtiming in orderto work with a20MHz clock

Set power downmode.

Wait desired timefor crystal to sta-bilize

Switch clocksource to externalcrystal

Optimize MIUread timing backto XTAL Fre-quency value.

> 20MHz

Set power downmode

Wait desired timefor crystal to sta-bilize

Optimize MIUread timing backto XTAL Fre-quency value.

Switch clocksource to externalcrystal

The MIUCTRL register (external data default loca-tion FE33h) is described in the MIU section.

The MISC register is located at the external defaultaddress location FEB1h. The clock select bit is inbit location 0. When cleared, the default value, theinternal ring oscillator becomes the bus clocksource. If set, then the external clock oscillatordrives the bus clock.

EExxiittiinngg PPoowweerr--DDoowwnn MMooddee

The Triscend E5 configurable system-on-chip exitspower down mode either from a reset or by as-serting either INT0 or INT1 sideband signal config-ured as a level-sensitive interrupt. An external re-set causes the device to exit the Power down state.The Low on RST- pin terminates the Power Downmode, and restarts the clock. In the Power downmode, all clocks are stopped, so the Watchdogtimer cannot be used to provide the reset to exitPower down mode. The Power on/fail reset, how-


www.triscend.com 70

ever, provides reset if power falls below the thresh-old level of VRST.

Three different events cause the device to exitpower down mode.

1. Apply a reset pulse on the RST- pin.

2. Assert the application-reset signal, RSTC.

3. Interrupt the MCU using one of the externalinterrupt sideband signals, INT0 or INT1 andhold the signal for at least two machine cycles.

RReesseett PPuullssee oonn RRSSTT--

Applying a reset pulse on the external RST- pincauses the Triscend E5 to exit power-down mode.When asserted, the RST- pulse resets the entiresystem, including MCU and its PCON SFR. Theinternal ring oscillator becomes the default systemclock source and the device begins the initializationprocess. The clock source selection for bus clockhappens during initialization. At the end of initiali-zation, the CPU begins executing the user’s appli-cation program. This method of exiting powerdown mode might be too slow for some applica-tions.

AAsssseerrttiinngg AApppplliiccaattiioonn RReesseett ((RRSSTTCC))

Another method to exit power down mode is to as-sert the application reset sideband signal, RSTC,from within the CSL matrix. The MCU re-startsexecuting the application program from 0000h. Ifthe crystal oscillator was blocked during powerdown, then default clock source is the internal os-cillator. Before switching back to the crystal oscil-lator, the user program must wait for the crystaloscillator to stabilize.

EExxtteerrnnaall IInntteerrrruupptt vviiaa SSiiddeebbaanndd SSiiggnnaall

The E5 wakes from the Power Down mode by as-serting the INT0 or INT1 interrupt sideband signals.The corresponding interrupt must be enabled, theglobal interrupt enable bit must be set and the INT0and INT1 sideband signals configured in level-sensitive mode. If these conditions are met, thenasserting the external pin re-enables the on-chiposcillator. The INT0 or INT1 sideband signalshould be asserted long enough for the internaloscillator to start and stabilize. The power downmode is finally exited when the external interrupt isreleased. The device then executes an interruptservice routine (ISR) for the corresponding externalinterrupt. After the interrupt service routine is com-pleted, the program execution returns to the in-struction after the one that put the device intoPower Down mode and continues from there.

Upon receiving an interrupt, the PCON SFR powerdown bit (PDBIT) is asynchronously reset to “0”. Inturn, it re-enables all the circuits that were selectedfor power down blocking. Again, if the crystal os-

cillator was blocked during power down, the inter-rupt routine must switch back from the internal ringoscillator to the crystal oscillator.

Glossary

CSoC - Configurable System-on-Chip. A configur-able device containing a dedicated processor, con-figurable logic, on-chip RAM, and a dedicated in-ternal bus.

CRU - Configuration Register Unit. Registers thatdefine special functions on the Triscend E5 device.

CSL - Configurable System Logic. The peripheralconfigurable logic matrix providing user-programmable functions to the microcontroller andits peripherals.

CSI - Configurable System Interconnect. The on-chip bus that bridges the Configurable SystemLogic (CSL) matrix, the 8032 "Turbo" microcon-troller, the dedicated peripherals, and the MemoryInterface Unit (MIU).

DMA - Direct Memory Access. A controller thatoffloads memory and I/O transfers from the micro-controller.

JTAG - Joint Test Action Group. A general namegiven to the four-wire serial interface described inIEEE 1149.1.

MCU - Microcontroller Unit. The 8032 "Turbo" mi-crocontroller embedded within the Triscend E5configurable system-on-chip.

MIU - Memory Interface Unit. Connects the micro-controller, its peripherals, and the internal systembus to external memory resources.

PIO - Programmable Input/Output.

SFR - Special Function Register. An 8032-basedterm for registers that control the microcontrollersperipheral functions.

Life Support Policy

Triscend's products are not authorized for use as criticalcomponents in life support devices or systems unless aspecific written agreement pertaining to such intendeduse is executed between the manufacturer and thePresident of Triscend.

1. Life support devices or systems are devices which(a) are intended for surgical implant into the body or(b) support or sustain life and whose failure to per-form, when properly used in accordance with in-structions for use provided in the labeling, can bereasonably expected to result in significant injury tothe user.

2. Critical component in any component of a life sup-port device or system whose failure to perform canbe reasonably expected to cause the failure of thelife support device system, or affect its safety or ef-fectiveness.

71 www.triscend.com

Pin Description

Table 43 describes the pins available on an E5 configurable system-on-chip device. The directionality ofeach pin is described for parallel, serial, and slave mode initialization.

Table 43. Pins available on an E5 configurable system-on-chip and their function.Pin Name Pin Description Parallel Serial Slave

A0/SCLK

Address bus bit 0 from the MIU in parallel mode.

Serial clock output to serial PROM in serial mode.

In slave mode, this pin has an internal high-impedancepull-up resistor that is active until initialization is com-plete.

O O I (pull-up)

A17/PIOA16/PIOA15/PIOA14/PIOA13/PIOA12/PIOA11/PIOA10/PIOA9/PIOA8/PIOA7/PIOA6/PIOA5/PIOA4/PIOA3/PIOA2/PIOA1/PIO

Address bus bit in parallel mode.

In other modes, this pin may be used as a PIO. Untilinitialization is complete, this pin has an internal high-impedance pull-up resistor.

O I (pull-up) I (pull-up)

BCLK/XTAL

Bus clock input from an external clock source or the out-put from the internal crystal oscillator amplifier. Connectto one side of the external crystal or ceramic resonator orto an external clock source.

O O O

CE-

Active-Low chip-enable signal. An output when the con-figurable system-on-chip accesses external memoryduring initialization in either parallel or serial modes.

An input while in slave mode.

O O I

D0/SDIN

Data bus bit 0 in parallel mode.

Serial data input (SDIN) in serial mode.

In slave mode, this pin has an internal high-impedancepull-up resistor that is active until initialization is com-plete.

I I I (pull-up)

D7/PIOD6/PIOD5/PIOD4/PIOD3/PIOD2/PIOD1/PIO

Data bus bit in parallel mode.

In other modes, this pin may be used as a PIO. Untilinitialization is complete, this pin has an internal high-impedance pull-up resistor.

I I (pull-up) I (pull-up)


www.triscend.com 72

Pin Name Pin Description Parallel Serial Slave

GNDGround connection for internal logic; connect to groundfor I/O functions. All must be connected.

I I I

GNDIOGround connection for I/O functions; connect to groundfor internal logic. All must be connected.

I I I

N.C. No connect. There is no function on this pin. N.C. N.C. N.C.

OE-/SRST

Active-Low output-enable signal. An output when theconfigurable system-on-chip accesses external memoryduring initialization in parallel or serial modes. An inputwhile in slave mode.

O O I

PIO

General-purpose input, output, or bi-directional signal pinafter initialization is complete. Before initialization iscomplete, these pins have internal high-impedance pull-up resistors that pull the signal pin to a High logic level.

I (pull-up) I (pull-up) I (pull-up)

PIO/A18PIO/A19PIO/A20PIO/A21PIO/A22PIO/A23PIO/A24PIO/A25PIO/A26PIO/A27PIO/A28PIO/A29PIO/A30

Typically, a general-purpose input, output, or bi-directional signal pin after initialization is complete. Be-fore initialization is complete, this pin has an internalhigh-impedance pull-up resistor that pulls the signal pinto a High logic level. Also used in multi-chip mode toexpand the upper address bits for external accesses.


PIO/GBUF5PIO/GBUF4PIO/GBUF3PIO/GBUF2PIO/GBUF1PIO/GBUF0

Global buffer input. Typically, a general-purpose input,output, or bi-directional signal pin after initialization iscomplete. Before initialization is complete, this pin hasan internal high-impedance pull-up resistor that pull thesignal pin to a High


PIO/XDONE

External data transfer done signal. Typically, a general-purpose input, output, or bi-directional signal pin afterinitialization is complete. Before initialization is complete,this pin has an internal high-impedance pull-up resistorthat pulls the signal pin to a High logic level. Also used inmulti-chip mode to for inter-device transfer handshaking.


PMOD/PIO/A31

Tied Low during initialization to indicate serial mode. Leftundriven or pulled High during initialization for parallelmode. Also a potential general-purpose input, output, orbi-directional signal pin after initialization is complete butwith the restrictions described above. Before initializationis complete, this pin has an internal high-impedance pull-up resistor that pulls the signal pin to a High logic level.Also used in multi-chip mode to expand the upper ad-dress bits for external accesses.


RST- Device reset input. Active Low. I I ISLAVE- Slave mode input. Active Low. I I I

TCK JTAG Test Clock input. Tie High if unused. I I ITDI JTAG Test Data Input. Tie High if unused. I I ITDO JTAG Test Data Output. O O OTMS JTAG Test Mode Select input. Tie High if unused. I I I

73 www.triscend.com

Pin Name Pin Description Parallel Serial Slave

VCC

Supply voltage for internal logic functions, separate fromI/O. Connect to a +3.3 volt supply. All must be con-nected and each must be decoupled with a 0.01 to 0.1µF capacitor to ground.

I I I

VCCIO

Supply voltage for I/O functions, separate from internallogic. Connect to a +3.3 volt supply. All must be con-nected and each must be decoupled with a 0.01 to 0.1µF capacitor to ground.

I I I

VSYSExternal system voltage-good indicator input. Indicateswhen external devices have sufficient operating voltage.

I I I

WE-/SEN-

Active-Low write-enable signal typically used to programexternal FLASH-based devices. An output when the E5accesses external memory during initialization in parallelor serial modes. An input while in slave mode.

O O I

XTALIN

The input from the external crystal into the internal crystaloscillator amplifier. Connect to one side of the externalcrystal or ceramic resonator. Leave unconnected if notusing an external crystal or resonator.

I I I

Pinout Diagrams and Tables

AAvvaaiillaabbllee PPaacckkaaggeess aanndd PPaacckkaaggee CCooddeess

Each Triscend E5 family member is available indifferent packages. Each ordering code contains aletter defining the package style, as shown in Table44.

Table 44. Package Codes.

PackageCode

PackageType

L 128-pin PQFPQ 208-pin PQFPB 436-pin BGA

FFoooottpprriinntt--CCoommppaattiibbiilliittyy

Each Triscend E5 configurable system-on-chip isdesigned to be footprint compatibly with other E5family members available in the same package,providing additional design and manufacturingflexibility. A designer can easily select a larger ormore cost-effective E5 device that fits a pre-existing printed circuit board (PCB) design.

AAvvaaiillaabbllee PPIIOOss bbyy PPaacckkaaggee

The number of user-configurable PIO pins dependson the base device type and the package in whichit is packaged. Table 45 shows the available PIOsby package style. Two values are indicated foreach device type, one for parallel mode and one forserial mode configuration. Both cases assume thatthe upper address bits, A[31:18] are used as PIOs,which is the default case.

Table 45. Available PIOs by PackageDevice Mode LQ128 PQ208 BG436

Parallel 52 68E502

Serial 76 92Parallel 60 100

E505Serial 84 124Parallel 60 126



E532Serial 150 316


www.triscend.com 74

112288--ppiinn TThhiinn PPllaassttiicc QQuuaadd FFllaatt PPaacckk,, ttoopp vviieeww ((PPaacckkaaggee CCooddee==LL))

VC

CIO

GN

DIO

A17

/PIO

A16

/PIO

A15

/PIO

A14

/PIO

A13

/PIO

A12

/PIO

VC

CIO

A11

/PIO

A10

/PIO

A9/

PIO

A8/

PIO

GN

D

12

8

VC

C

12

7

GN

DIO

12

6

12

5

12

4

12

3

12

2

PIO

12

1

PIO

12

0

A7/

PIO

11

9

GN

DIO

11

8

11

7

11

6

11

5

11

4

11

3

11

2

A6/

PIO

11

1

11

0

10

9

10

8

10

7

10

6

10

5

10

4

GN

DIO

A5/

PIO

A4/

PIO

A3/

PIO

A2/

PIO

10

3

10

2

10

1

10

0

99

98

A1/

PIO

97

A0/

SC

LK

PIO

PIO

PIO

PIO

VCCIO

89

88

87

D3/PIO

RST-

79

78

D7/PIO

77

GNDIO

76

D5/PIO

75

D4/PIO

74

GND

73

VCC

72

71

D2/PIO

70

69

68

PIO

67

PIO

66

D1/PIO

65

D0/SDIN

D6/PIO

GNDIO

86

85

CE-

84

OE-/SRST

83

82 GNDIO81

80

PIO/XDONE

PIO (N.C.)

WE-/SEN-SLAVE-

96

94

93

92

91

90

PIOPIO

PIO (N.C.)PIO (N.C.)

VCCIO

PIO (N.C.)PIO

GNDIO

VSYS953

3

PIO

34

PIO

35

PIO

36

PIO

/GB

UF

53

7

PIO

38

PIO

39

PIO

40

PIO

/GB

UF

4

41

GN

DIO

42

VC

C

43

GN

D

44

45

46

47

48

PIO

49

PIO

/GB

UF

3

50

51

GN

DIO

52

PIO

/GB

UF

2

53

PIO

54

PIO

55

PIO

56

PIO

57

VC

CIO

PIO

PIO

/GB

UF

1

PIO

/GB

UF

0

GN

DIO

58

59

60

61

GN

DIO

62

63

PIO

64

PIO

VC

CIO

PIO

PIO

PIO

PIO

1

XTALIN 2

BCLK/XTAL 3

4

GNDIO

5

PIO/A26

6

PIO/A27

7

TDI

8

TDO

9

GNDIO 10

(N.C.) PIO

11

PIO 12

TCK

13

TMS

14

15

(N.C.) PIO 16

PIO/A23

17VCCIO18

PIO/A22 19

PIO

20

PIO/A24 21

PIO/A25 22

PIO/A18

23

PIO/A19

24

25

PIO/A20PIO/A21

GNDIO

PIO/A29PIO/A30

(N.C.) PIO 26

(N.C.) PIO 27

PIO/A28 28

29

30

31

GNDIO

VCCIO 32

PMOD/PIO/A31

TE502S08L

TE505S16L

TE512S16L

(N.C.) indicates a pin that is not connected on the TE502S08L device in this package.

75 www.triscend.com

112288--ppiinn tthhiinn PPQQFFPP ((PPaacckkaaggee CCooddee==LL)) PPaacckkaaggee PPiinnoouutt TTaabblleess

Shaded cells represent a pin that is not connected on the TE502 device but is a PIO pin for all other de-vices.

Pin TE502TE505TE512

1 GNDIO GNDIO2 XTALIN XTALIN3 BCLK/XTAL BCLK/XTAL4 TDI TDI5 TDO TDO6 TCK TCK7 TMS TMS8 PIO/A18 PIO/A189 PIO/A19 PIO/A19

10 GNDIO GNDIO11 PIO PIO12 PIO PIO13 PIO/A20 PIO/A2014 PIO/A21 PIO/A2115 N.C. PIO16 N.C. PIO17 VCCIO VCCIO18 GNDIO GNDIO19 PIO/A22 PIO/A2220 PIO/A23 PIO/A2321 PIO/A24 PIO/A2422 PIO/A25 PIO/A2523 PIO/A26 PIO/A2624 PIO/A27 PIO/A2725 GNDIO GNDIO26 N.C. PIO27 N.C. PIO28 PIO/A28 PIO/A2829 PIO/A29 PIO/A2930 PIO/A30 PIO/A30

31PMOD/PIO/A31

PMOD/PIO/A31

32 VCCIO VCCIO33 GNDIO GNDIO34 PIO PIO35 PIO PIO36 PIO PIO37 PIO/GBUF5 PIO/GBUF538 GNDIO GNDIO39 PIO PIO40 PIO PIO41 PIO PIO42 PIO/GBUF4 PIO/GBUF443 PIO PIO44 PIO PIO45 VCC VCC46 GND GND47 PIO PIO48 PIO/GBUF3 PIO/GBUF3

Pin TE502TE505TE512

49 GNDIO GNDIO50 PIO/GBUF2 PIO/GBUF251 PIO PIO52 VCCIO VCCIO53 PIO PIO54 PIO PIO55 PIO PIO56 PIO/GBUF1 PIO/GBUF157 GNDIO GNDIO58 PIO PIO59 PIO PIO60 PIO PIO61 PIO/GBUF0 PIO/GBUF062 PIO PIO63 PIO PIO64 VCCIO VCCIO65 GNDIO GNDIO66 D0/SDIN D0/SDIN67 D1/PIO D1/PIO68 PIO PIO69 PIO PIO70 PIO PIO71 PIO PIO72 GNDIO GNDIO73 N.C. PIO74 N.C. PIO75 D2/PIO D2/PIO76 D3/PIO D3/PIO77 VCC VCC78 GND GND79 D4/PIO D4/PIO80 D5/PIO D5/PIO81 VCCIO VCCIO82 GNDIO GNDIO83 D6/PIO D6/PIO84 D7/PIO D7/PIO85 N.C. PIO86 N.C. PIO87 PIO PIO88 PIO/XDONE PIO/XDONE89 GNDIO GNDIO90 WE-/SEN- WE-/SEN-91 SLAVE- SLAVE-92 OE-/SRST OE-/SRST93 CE- CE-94 RST- RST-95 VSYS VSYS96 VCCIO VCCIO97 GNDIO GNDIO

Pin TE502TE505TE512

98 A0/SCLK A0/SCLK99 A1/PIO A1/PIO

100 A2/PIO A2/PIO101 A3/PIO A3/PIO102 GNDIO GNDIO103 A4/PIO A4/PIO104 A5/PIO A5/PIO105 A6/PIO A6/PIO106 A7/PIO A7/PIO107 PIO PIO108 PIO PIO109 GNDIO GNDIO110 VCC VCC111 GND GND112 A8/PIO A8/PIO113 A9/PIO A9/PIO114 A10/PIO A10/PIO115 A11/PIO A11/PIO116 VCCIO VCCIO117 PIO PIO118 PIO PIO119 A12/PIO A12/PIO120 A13/PIO A13/PIO121 GNDIO GNDIO122 PIO PIO123 PIO PIO124 A14/PIO A14/PIO125 A15/PIO A15/PIO126 A16/PIO A16/PIO127 A17/PIO A17/PIO128 VCCIO VCCIO


www.triscend.com 76

112288--PPiinn LLQQFFPP PPiinnss bbyy TTyyppee


Type TE502TE505TE512

PIO* 52 60VCC 3 3VCCIO 8 8GND 3 3GNDIO 16 16D[7:0] 8 8A[17:0] 18 18JTAG 4 4N.C. 8 0Others 8 8

SSeerriiaall MMooddee

Type TE502TE505TE512

PIO* 76 84VCC 3 3VCCIO 8 8GND 3 3GNDIO 16 16SDIN 1 1SCLK 1 1JTAG 4 4N.C. 8 0Others 8 8

PIO* includes pure PIO pins andthose with alternate functions

77 www.triscend.com

112288--ppiinn tthhiinn PPQQFFPP ((PPaacckkaaggee CCooddee==LL)) PPaacckkaaggee MMeecchhaanniiccaall DDrraawwiinngg

1

32

33 64

65

96

97128

Pin 1Identifier

D1

D

EE1Top View

e b

A A2

A1

See Detail 'A'

θ2

θ1

θ3

L1

L

θ

c

Detail 'A'

S

MillimetersSymbol Min. Nom. Max.

A — — 1.60A1 0.05 — —A2 1.35 1.40 1.45b 0.13 0.18 0.23c 0.09 — 0.20D 15.85 16.00 16.15D1 13.90 14.00 14.10E 15.85 16.00 16.15E1 13.90 14.00 14.10e 0.40 BSCL 0.45 0.60 0.75L1 1.00 REFS 0.20 — —θ 0º 3.5º 7ºθ1 0º — —θ2 12º TYPθ3 12º TYP

1. All dimensions and tolerances conform to ASME Y14.5M-1994.

2. All dimensions are in millimeters.

3. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion shall not exceed 0.25 mm per side.

4. Package top dimensions may be smaller than bottom dimensions.

JEDEC Reference Drawing: MS-026CJEDEC File Location: http://www.jedec.org/DOWNLOAD/pub95/MS-026c.pdf

Assembly Vendor Drawing: SPIL, D128-SW1-A

http://www.jedec.org/DOWNLOAD/pub95/MS-026c.pdf


www.triscend.com 78

220088--ppiinn PPllaassttiicc QQuuaadd FFllaatt PPaacckk,, ttoopp vviieeww ((PPaacckkaaggee CCooddee==QQ))

208

207

VC

CIO

206

PIO

205

PIO

204

PIO

203

PIO

202

A17

/PIO

201

A16

/PIO

200

GN

DIO

199

PIO

198

PIO

197

A15

/PIO

196

A14

/PIO

195

PIO

(N

.C.)

194

193

PIO

192

PIO

191

GN

DIO

190

VC

CIO

189

PIO

188

PIO

187

A13

/PIO

186

A12

/PIO

185

PIO

184

PIO

183

A11

/PIO

182

GN

DIO

181

A10

/PIO

180

179

178

A9/

PIO

177

A8/

PIO

176

GN

D

175

VC

C

174

173

VC

CIO

172

GN

DIO

171

170

169

PIO

(N

.C.)

168

PIO

167

PIO

166

A7/

PIO

165

A6/

PIO

164

A5/

PIO

163

A4/

PIO

162

GN

DIO

161

PIO

(N

.C.)

160

A3/

PIO

159

A2/

PIO

158

A1/

PIO

157

A0/

SC

LK

PIO

(N

.C.)

PIO

(N

.C.)

PIO

(N

.C.)

PIO

(N

.C.)

PIO

(N

.C.)

PIO

(N

.C.)

GN

DIO

53

PIO

54

PIO

55

PIO

56

PIO

/GB

UF

557

(N.C

.) P

IO58

GN

DIO

59

PIO

60

PIO

61

PIO

62

PIO

/GB

UF

463

PIO

64

(N.C

.) P

IO

65

(N.C

.) P

IO66

PIO

67

VC

CIO

68

GN

DIO

69

70

71

VC

C72

GN

D73

PIO

74

PIO

/GB

UF

375

(N.C

.) P

IO76

77

GN

DIO

78

PIO

/GB

UF

279

PIO

80

PIO

81

PIO

82

PIO

83

PIO

/GB

UF

184

PIO

85

PIO

86

VC

CIO

87

GN

DIO

88

PIO

89

PIO

90

91

92

PIO

93

PIO

/GB

UF

094

PIO

95

PIO

96

PIO

97

PIO

98

GN

DIO

99

PIO

100

PIO

101

PIO

102

PIO

103

VC

CIO

104

(N.C

.) P

IO(N

.C.)

PIO

(N.C

.) P

IO

(N.C

.) P

IO(N

.C.)

PIO

GN

DIO

1

XTALIN 2

BCLK/XTAL 3

TDI 4

TDO 5

TCK 6

TMS 7

PIO/A18 8

PIO/A19 9

GNDIO 10

PIO 11

PIO 12

13

14

(N.C.) PIO 15

PIO/A20

16

PIO/A21

17

VCCIO 18

GNDIO 19

PIO/A22 20

PIO/A23 21

(N.C.) PIO 22

(N.C.) PIO 23

VCC 24

GND 25

PIO/A24 26

PIO/A25 27

GNDIO 28

PIO/A26 29

PIO/A27 30

31

32

PIO/A28

33

PIO/A29

34

PIO/A30

35

PMOD/PIO/A31

36

VCCIO 37

GNDIO 38

39

40

41

42

43

44

GNDIO 45

46

47

48

49

50

51

VCCIO 52

GNDIO

(N.C.) PIO(N.C.) PIO

(N.C.) PIO(N.C.) PIO(N.C.) PIO(N.C.) PIO(N.C.) PIO(N.C.) PIO

(N.C.) PIO(N.C.) PIO(N.C.) PIO(N.C.) PIO

(N.C.) PIO(N.C.) PIO(N.C.) PIO(N.C.) PIO

156

155

VCCIO

154

VSYS

153

RST-

152

CE-

151

OE-/SRST

150

SLAVE-

149

WE-/SEN-

148

GNDIO

147

PIO/XDONE

146

PIO

145

144

PIO (N.C.)143

PIO (N.C.)

142

141

D7/PIO

140

D6/PIO

139

GNDIO

138

VCCIO

137

D5/PIO

136

D4/PIO

135

134

PIO (N.C.)

133

GND

132

VCC

131

D3/PIO

130

D2/PIO

129

GNDIO

128

127

126

125

124

D1/PIO

123

D0/SDIN

122

PIO

121

PIO

120

GNDIO

119

VCCIO

118

PIO (N.C.)117

PIO

116

PIO

115

114

113

GNDIO112

111

110

109

108

107

106

105

PIO (N.C.)

GNDIOPIO (N.C.)PIO (N.C.)PIO (N.C.)PIO (N.C.)

PIO (N.C.)PIO (N.C.)PIO (N.C.)PIO (N.C.)

PIO (N.C.)PIO (N.C.)PIO (N.C.)PIO (N.C.)PIO (N.C.)PIO (N.C.)

PIO (N.C.)PIO (N.C.)TE502S08Q

TE505S16Q

TE512S16Q

TE520S40Q

TE532S64Q

(N.C.) indicates a pin that is not connected on the TE520S08Q or TE505S16Q device in this package.

79 www.triscend.com

220088--ppiinn PPQQFFPP ((PPaacckkaaggee CCooddee==QQ)) PPaacckkaaggee PPiinnoouutt TTaabblleess

Shaded cells represent a pin that is not connected on the TE502 or TE505 device but is connected on allother devices.

Pin TE502 TE505

TE512TE520TE532

1 GNDIO GNDIO GNDIO2 XTALIN XTALIN XTALIN

3BCLK/XTAL

BCLK/XTAL

BCLK/XTAL

4 TDI TDI TDI5 TDO TDO TDO6 TCK TCK TCK7 TMS TMS TMS8 PIO/A18 PIO/A18 PIO/A189 PIO/A19 PIO/A19 PIO/A19

10 GNDIO GNDIO GNDIO11 PIO PIO PIO12 PIO PIO PIO13 PIO/A20 PIO/A20 PIO/A2014 PIO/A21 PIO/A21 PIO/A2115 N.C. N.C. PIO16 N.C. PIO PIO17 N.C. PIO PIO18 VCCIO VCCIO VCCIO19 GNDIO GNDIO GNDIO20 PIO/A22 PIO/A22 PIO/A2221 PIO/A23 PIO/A23 PIO/A2322 N.C. N.C. PIO23 N.C. N.C. PIO24 VCC VCC VCC25 GND GND GND26 PIO/A24 PIO/A24 PIO/A2427 PIO/A25 PIO/A25 PIO/A2528 GNDIO GNDIO GNDIO29 PIO/A26 PIO/A26 PIO/A2630 PIO/A27 PIO/A27 PIO/A2731 N.C. PIO PIO32 N.C. PIO PIO33 N.C. PIO PIO34 N.C. PIO PIO35 N.C. PIO PIO36 N.C. PIO PIO37 VCCIO VCCIO VCCIO38 GNDIO GNDIO GNDIO39 PIO/A28 PIO/A28 PIO/A2840 PIO/A29 PIO/A29 PIO/A2941 N.C. PIO PIO42 N.C. PIO PIO43 N.C. PIO PIO44 N.C. PIO PIO45 N.C. GNDIO GNDIO46 PIO/A30 PIO/A30 PIO/A30

47PMOD/PIO/A31

PMOD/PIO/A31

PMOD/PIO/A31

48 N.C. PIO PIO49 N.C. PIO PIO50 N.C. PIO PIO51 N.C. PIO PIO

Pin TE502 TE505

TE512TE520TE532

52 VCCIO VCCIO VCCIO53 GNDIO GNDIO GNDIO54 PIO PIO PIO55 PIO PIO PIO56 PIO PIO PIO

57PIO/GBUF5

PIO/GBUF5

PIO/GBUF5

58 N.C. N.C. PIO59 GNDIO GNDIO GNDIO60 PIO PIO PIO61 PIO PIO PIO62 PIO PIO PIO

63PIO/GBUF4

PIO/GBUF4

PIO/GBUF4

64 PIO PIO PIO65 PIO PIO PIO66 N.C. N.C. PIO67 N.C. N.C. PIO68 VCCIO VCCIO VCCIO69 GNDIO GNDIO GNDIO70 N.C. N.C. PIO71 N.C. N.C. PIO72 VCC VCC VCC73 GND GND GND74 PIO PIO PIO

75PIO/GBUF3

PIO/GBUF3

PIO/GBUF3

76 N.C. N.C. PIO77 N.C. N.C. PIO78 GNDIO GNDIO GNDIO

79PIO/GBUF2

PIO/GBUF2

PIO/GBUF2

80 PIO PIO PIO81 PIO PIO PIO82 PIO PIO PIO83 PIO PIO PIO

84PIO/GBUF1

PIO/GBUF1

PIO/GBUF1

85 PIO PIO PIO86 PIO PIO PIO87 VCCIO VCCIO VCCIO88 GNDIO GNDIO GNDIO89 PIO PIO PIO90 PIO PIO PIO91 N.C. N.C. PIO92 N.C. N.C. PIO93 PIO PIO PIO

94PIO/GBUF0

PIO/GBUF0

PIO/GBUF0

95 PIO PIO PIO96 PIO PIO PIO97 GNDIO GNDIO GNDIO98 PIO PIO PIO99 PIO PIO PIO


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Pin TE502 TE505

TE512TE520TE532

100 PIO PIO PIO101 PIO PIO PIO102 PIO PIO PIO103 PIO PIO PIO104 VCCIO VCCIO VCCIO105 GNDIO GNDIO GNDIO106 N.C. PIO PIO107 N.C. PIO PIO108 N.C. PIO PIO109 N.C. PIO PIO110 D0/SDIN D0/SDIN D0/SDIN111 D1/PIO D1/PIO D1/PIO112 N.C. GNDIO GNDIO113 N.C. PIO PIO114 N.C. PIO PIO115 N.C. PIO PIO116 N.C. PIO PIO117 N.C. N.C. PIO118 PIO PIO PIO119 PIO PIO PIO120 VCCIO VCCIO VCCIO121 GNDIO GNDIO GNDIO122 PIO PIO PIO123 PIO PIO PIO124 N.C. PIO PIO125 N.C. PIO PIO126 N.C. PIO PIO127 N.C. PIO PIO128 N.C. PIO PIO129 N.C. PIO PIO130 GNDIO GNDIO GNDIO131 D2/PIO D2/PIO D2/PIO132 D3/PIO D3/PIO D3/PIO133 VCC VCC VCC134 GND GND GND135 N.C. N.C. PIO136 N.C. N.C. PIO137 D4/PIO D4/PIO D4/PIO138 D5/PIO D5/PIO D5/PIO139 VCCIO VCCIO VCCIO140 GNDIO GNDIO GNDIO141 D6/PIO D6/PIO D6/PIO142 D7/PIO D7/PIO D7/PIO143 N.C. N.C. PIO144 N.C. N.C. PIO145 N.C. PIO PIO146 N.C. PIO PIO147 PIO PIO PIO

148PIO/XDONE

PIO/XDONE

PIO/XDONE

149 GNDIO GNDIO GNDIO150 WE-/SEN- WE-/SEN- WE-/SEN-151 SLAVE- SLAVE- SLAVE-152 OE-/SRST OE-/SRST OE-/SRST153 CE- CE- CE-154 RST- RST- RST-

Pin TE502 TE505

TE512TE520TE532

155 VSYS VSYS VSYS156 VCCIO VCCIO VCCIO157 GNDIO GNDIO GNDIO158 A0/SCLK A0/SCLK A0/SCLK159 A1/PIO A1/PIO A1/PIO160 A2/PIO A2/PIO A2/PIO161 A3/PIO A3/PIO A3/PIO162 N.C. N.C. PIO163 GNDIO GNDIO GNDIO164 A4/PIO A4/PIO A4/PIO165 A5/PIO A5/PIO A5/PIO166 A6/PIO A6/PIO A6/PIO167 A7/PIO A7/PIO A7/PIO168 PIO PIO PIO169 PIO PIO PIO170 N.C. N.C. PIO171 N.C. N.C. PIO172 VCCIO VCCIO VCCIO173 GNDIO GNDIO GNDIO174 N.C. N.C. PIO175 N.C. N.C. PIO176 VCC VCC VCC177 GND GND GND178 A8/PIO A8/PIO A8/PIO179 A9/PIO A9/PIO A9/PIO180 N.C. N.C. PIO181 N.C. N.C. PIO182 GNDIO GNDIO GNDIO183 A10/PIO A10/PIO A10/PIO184 A11/PIO A11/PIO A11/PIO185 PIO PIO PIO186 PIO PIO PIO187 A12/PIO A12/PIO A12/PIO188 A13/PIO A13/PIO A13/PIO189 PIO PIO PIO190 PIO PIO PIO191 VCCIO VCCIO VCCIO192 GNDIO GNDIO GNDIO193 PIO PIO PIO194 PIO PIO PIO195 N.C. N.C. PIO196 N.C. N.C. PIO197 A14/PIO A14/PIO A14/PIO198 A15/PIO A15/PIO A15/PIO199 PIO PIO PIO200 PIO PIO PIO201 GNDIO GNDIO GNDIO202 A16/PIO A16/PIO A16/PIO203 A17/PIO A17/PIO A17/PIO204 PIO PIO PIO205 PIO PIO PIO206 PIO PIO PIO207 PIO PIO PIO208 VCCIO VCCIO VCCIO

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220088--ppiinn PPQQFFPP PPiinnss bbyy TTyyppee


Type TE502 TE505

TE512TE520TE532

PIO* 68 100 126VCC 4 4 4VCCIO 10 12 12GND 4 4 4GNDIO 20 24 24D[7:0] 8 8 8A[17:0] 18 18 18JTAG 4 4 4N.C. 64 26 0Others 8 8 8

SSeerriiaall MMooddee

Type TE502 TE505

TE512TE520TE532

PIO* 92 124 150VCC 4 4 4VCCIO 10 12 12GND 4 4 4GNDIO 20 24 24SDIN 1 1 1SCLK 1 1 1JTAG 4 4 4N.C. 64 26 0Others 8 8 8

PIO* includes pure PIO pins and those with alter-nate functions.


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220088--ppiinn PPQQFFPP ((PPaacckkaaggee CCooddee==QQ)) PPaacckkaaggee MMeecchhaanniiccaall DDrraawwiinngg

1

52

53 104

105

156

157208

A A2

A1

e b

Pin 1Identifier

See Detail 'A'

D1

D

EE1Top View θ2

θ1

θ3

L1

L

θ

c

Detail 'A'

S

MillimetersSymbol Min. Nom. Max.

A 3.92 — 4.07A1 0.25 — —A2 3.15 3.23 3.30b 0.18 — 0.28c 0.13 — 0.23D 30.35 30.60 30.85D1 27.90 28.00 28.10E 30.35 30.60 30.85E1 27.90 28.00 28.10e 0.50 BSCL 0.35 0.50 0.65L1 1.30 REFS 0.20 — —θ 0º — 7ºθ1 0º — —θ2 12º TYPθ3 12º TYP

1. All dimensions and tolerances conform to ASME Y14.5M-1994.

2. All dimensions are in millimeters.

3. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion shall not exceed 0.25 mm per side.

4. Package top dimensions may be smaller than bottom dimensions.

JEDEC Reference Drawing: MS-029A-FA-1JEDEC File Location: http://www.jedec.org/DOWNLOAD/pub95/ms-029a.pdf

Assembly Vendor Drawing: SPIL, Q208-SW2-C

http://www.jedec.org/DOWNLOAD/pub95/ms-029a.pdf

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443366--bbaallll BBaallll--GGrriidd AArrrraayy PPaacckkaaggee,, ttoopp vviieeww ((PPaacckkaaggee CCooddee==BB))

AB

TDI PIO PIOA17/PIO

A15/PIO

PIO PIO

PIO

PIO PIOA11/PIO

PIO

PIO

PIO

PIO

TMSBCLK/XTAL

1 2 3 4

A

B

C

D

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

PIO PIOA16/PIO

A14/PIO

PIO

PIO TCKXTAL

IN PIO PIO PIO PIO

PIOPIO/A19

TDO GNDIO GNDIO GNDIO PIO PIO

PIO

PIO

A12/PIO

A13/PIO

PIO PIO

PIO

PIO

PIO

A10/PIO

PIO

PIO

A9/PIO

A8/PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

A7/PIO

PIO

PIO

A6/PIO

A5/PIO

PIO

PIO

A4/PIO

GNDIO

PIO

PIO

PIO

GNDIO

PIO

PIO

A1/PIO

GNDIO

A3/PIO

A2/PIO

VSYS

OE-/SRST

A0/SCLK

RST-

N.C.

PIO/XDONE

CE-

N.C.

SLAVE-

PIO

E

F

PIO PIOPIO/A18

GNDIO GNDIO GNDIO GNDIO GNDIO GNDIOVCCIO VCCIO VCCIO GND VCC VCCIO GNDIO VCCIO VCCIO GNDIO GNDIO GNDIO GNDIO PIOPIOWE-/SEN-

GNDIO

G

PIO PIO PIO GNDIO GNDIO PIOPIOPIOGNDIO GNDIO

PIOPIO/A20

PIO GNDIOPIO

PIO PIOPIO/A21

GNDIOPIOH

PIO PIO PIO PIOJ VCCIO

PIO/A23

PIO PIO PIOK VCCIO

PIO GNDIOPIO/A22

L

PIO/A24

PIOM VCCIO

PIO/A25

N VCC

PIO PIO GNDPIOP

PIOPIO/A26

PIO/A27

PIOR VCCIO

PIO PIO PIO GNDIOPIOT

PIO PIOU VCCIO

PIO PIOV VCCIOPIO

PIO

PIO GNDIOW

YPIO/A28

PIO GNDIO

AA

PIO/A29

PIO GNDIO GNDIO

PIO PIOPMOD/PIO/A31

GNDIO GNDIO GNDIO GNDIO GNDIO VCCIO VCCIO GNDIO VCCIO VCC GND

AC

PIOPIO/A30

GNDIO GNDIO GNDIOPIO PIO PIO/GBUF4

PIO PIO PIO PIOPIO

VCCIO GNDIO

AD

PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO/GBUF3

PIO/GBUF2

PIO

AE

PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO

AF

PIO PIO PIO/GBUF5

PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO

VCCIO VCCIO GNDIO GNDIO GNDIO

PIO PIO PIO GNDIO

PIO

PIO/GBUF1

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

GNDIO

GNDIO

GNDIO

GNDIO

PIO

PIO

PIO/GBUF0

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIO

PIOD1/PIO

PIO

D0/SDIN

PIO PIO

GNDIO GNDIO PIO PIO

GNDIO PIO PIO PIO

PIOGNDIO

PIO PIO PIOVCCIO

PIO PIOVCCIO PIO[N.C.]

GNDIO PIO PIO PIO PIO

PIO PIO PIO PIOVCCIO

PIO PIO PIOVCC

GNDD2/PIO

PIOD3/PIO

VCCIO

GNDIOD4/PIO

PIO

PIO PIO PIOD5/PIO

VCCIO

PIO PIOD6/PIO

PIOVCCIO

GNDIO PIO PIO PIOD7/PIO

GNDIO PIO PIO PIO PIO

GNDIO GNDIO GNDIO GNDIO




PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

PIO[N.C.]

TE520S40B(this device has N.C. pins)

TE532S64B

PIO[N.C.]

indicates that this is connected on the TE532S64B device but is a 'no connect' on the TE520S40B device.


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443366--bbaallll BBaallll--GGrriidd AArrrraayy ((PPaacckkaaggee CCooddee==BB)) PPaacckkaaggee PPiinnoouutt TTaabblleess

Shaded cells represent a pin that is a no connect for the TE520 but is a PIO pin for all other devices.

Ball TE520 TE532A1 TDI TDIA2 PIO PIOA3 PIO PIOA4 A17/PIO A17/PIOA5 A15/PIO A15/PIOA6 PIO PIOA7 N.C. PIOA8 PIO PIOA9 N.C. PIO

A10 A12/PIO A12/PIOA11 PIO PIOA12 PIO PIOA13 A11/PIO A11/PIOA14 PIO PIOA15 N.C. PIOA16 N.C. PIOA17 N.C. PIOA18 PIO PIOA19 PIO PIOA20 PIO PIOA21 PIO PIOA22 PIO PIOA23 PIO PIOA24 A3/PIO A3/PIOA25 A0/SCLK A0/SCLKA26 CE- CE-B1 TMS TMSB2 BCLK/XTAL BCLK/XTALB3 PIO PIOB4 PIO PIOB5 A16/PIO A16/PIOB6 A14/PIO A14/PIOB7 PIO PIOB8 N.C. PIOB9 PIO PIO

B10 A13/PIO A13/PIOB11 PIO PIOB12 PIO PIOB13 PIO PIOB14 PIO PIOB15 N.C. PIOB16 N.C. PIOB17 N.C. PIOB18 PIO PIOB19 PIO PIOB20 PIO PIOB21 PIO PIOB22 PIO PIOB23 PIO PIOB24 A2/PIO A2/PIOB25 RST- RST-B26 N.C. N.C.C1 PIO PIOC2 TCK TCKC3 XTALIN XTALINC4 PIO PIO

Ball TE520 TE532C5 PIO PIOC6 PIO PIOC7 PIO PIOC8 N.C. PIOC9 PIO PIO

C10 N.C. PIOC11 N.C. PIOC12 PIO PIOC13 A10/PIO A10/PIOC14 N.C. PIOC15 A9/PIO A9/PIOC16 PIO PIOC17 PIO PIOC18 PIO PIOC19 PIO PIOC20 A6/PIO A6/PIOC21 A4/PIO A4/PIOC22 PIO PIOC23 A1/PIO A1/PIOC24 VSYS VSYSC25 N.C. N.C.C26 SLAVE- SLAVE-D1 PIO PIOD2 PIO/A19 PIO/A19D3 TDO TDOD4 GNDIO GNDIOD5 GNDIO GNDIOD6 GNDIO GNDIOD7 PIO PIOD8 PIO PIOD9 N.C. PIO

D10 PIO PIOD11 N.C. PIOD12 PIO PIOD13 PIO PIOD14 N.C. PIOD15 A8/PIO A8/PIOD16 PIO PIOD17 PIO PIOD18 PIO PIOD19 A7/PIO A7/PIOD20 A5/PIO A5/PIOD21 GNDIO GNDIOD22 GNDIO GNDIOD23 GNDIO GNDIOD24 OE-/SRST OE-/SRSTD25 PIO/XDONE PIO/XDONED26 PIO PIOE1 PIO PIOE2 PIO PIOE3 PIO/A18 PIO/A18E4 GNDIO GNDIOE5 GNDIO GNDIOE6 GNDIO GNDIOE7 GNDIO GNDIOE8 GNDIO GNDIO

Ball TE520 TE532E9 VCCIO VCCIO

E10 VCCIO VCCIOE11 GNDIO GNDIOE12 VCCIO VCCIOE13 GND GNDE14 VCC VCCE15 VCCIO VCCIOE16 GNDIO GNDIOE17 VCCIO VCCIOE18 VCCIO VCCIOE19 GNDIO GNDIOE20 GNDIO GNDIOE21 GNDIO GNDIOE22 GNDIO GNDIOE23 GNDIO GNDIOE24 WE-/SEN- WE-/SEN-E25 PIO PIOE26 PIO PIOF1 PIO PIOF2 PIO PIOF3 PIO PIOF4 GNDIO GNDIOF5 GNDIO GNDIO

F22 GNDIO GNDIOF23 GNDIO GNDIOF24 PIO PIOF25 PIO PIOF26 PIO PIOG1 PIO PIOG2 PIO/A20 PIO/A20G3 PIO PIOG4 PIO PIOG5 GNDIO GNDIO

G22 GNDIO GNDIOG23 PIO PIOG24 PIO PIOG25 PIO PIOG26 PIO PIOH1 PIO PIOH2 PIO PIOH3 PIO/A21 PIO/A21H4 PIO PIOH5 GNDIO GNDIO

H22 GNDIO GNDIOH23 PIO PIOH24 PIO PIOH25 PIO PIOH26 D7/PIO D7/PIOJ1 PIO PIOJ2 PIO PIOJ3 PIO PIOJ4 PIO PIOJ5 VCCIO VCCIO

J22 VCCIO VCCIOJ23 PIO PIOJ24 PIO PIO

85 www.triscend.com

Ball TE520 TE532J25 D6/PIO D6/PIOJ26 PIO PIOK1 PIO/A23 PIO/A23K2 PIO PIOK3 PIO PIOK4 PIO PIOK5 VCCIO VCCIO

K22 VCCIO VCCIOK23 PIO PIOK24 PIO PIOK25 PIO PIOK26 D5/PIO D5/PIOL1 PIO PIOL2 N.C. PIOL3 N.C. PIOL4 PIO/A22 PIO/A22L5 GNDIO GNDIO

L22 GNDIO GNDIOL23 D4/PIO D4/PIOL24 N.C. PIOL25 N.C. PIOL26 PIO PIOM1 PIO/A24 PIO/A24M2 N.C. PIOM3 N.C. PIOM4 PIO PIOM5 VCCIO VCCIO

M12 GNDIO GNDIOM13 GNDIO GNDIOM14 GNDIO GNDIOM15 GNDIO GNDIOM22 VCCIO VCCIOM23 PIO PIOM24 N.C. PIOM25 N.C. PIOM26 D3/PIO D3/PION1 N.C. PION2 N.C. PION3 N.C. PION4 PIO/A25 PIO/A25N5 VCC VCC

N12 GNDIO GNDION13 GNDIO GNDION14 GNDIO GNDION15 GNDIO GNDION22 GND GNDN23 D2/PIO D2/PION24 N.C. PION25 N.C. PION26 N.C. PIOP1 N.C. PIOP2 PIO PIOP3 PIO PIOP4 PIO PIOP5 GND GND

P12 GNDIO GNDIOP13 GNDIO GNDIOP14 GNDIO GNDIOP15 GNDIO GNDIOP22 VCC VCC

Ball TE520 TE532P23 PIO PIOP24 PIO PIOP25 PIO PIOP26 N.C. PIOR1 PIO PIOR2 PIO/A26 PIO/A26R3 PIO/A27 PIO/A27R4 PIO PIOR5 VCCIO VCCIO

R12 GNDIO GNDIOR13 GNDIO GNDIOR14 GNDIO GNDIOR15 GNDIO GNDIOR22 VCCIO VCCIOR23 PIO PIOR24 PIO PIOR25 PIO PIOR26 PIO PIOT1 PIO PIOT2 PIO PIOT3 PIO PIOT4 PIO PIOT5 GNDIO GNDIO

T22 GNDIO GNDIOT23 PIO PIOT24 PIO PIOT25 PIO PIOT26 PIO PIOU1 PIO PIOU2 N.C. PIOU3 PIO PIOU4 N.C. PIOU5 VCCIO VCCIO

U22 VCCIO VCCIOU23 N.C. PIOU24 PIO PIOU25 N.C. PIOU26 PIO PIOV1 N.C. PIOV2 PIO PIOV3 PIO PIOV4 PIO PIOV5 VCCIO VCCIO

V22 VCCIO VCCIOV23 PIO PIOV24 PIO PIOV25 PIO PIOV26 N.C. PIOW1 N.C. PIOW2 PIO PIOW3 N.C. PIOW4 N.C. PIOW5 GNDIO GNDIO

W22 GNDIO GNDIOW23 N.C. PIOW24 N.C. PIOW25 PIO PIOW26 N.C. PIOY1 PIO PIOY2 N.C. PIO

Ball TE520 TE532Y3 PIO/A28 PIO/A28Y4 PIO PIOY5 GNDIO GNDIO

Y22 GNDIO GNDIOY23 PIO PIOY24 PIO PIOY25 N.C. PIOY26 PIO PIOAA1 N.C. PIOAA2 PIO/A29 PIO/A29AA3 PIO PIOAA4 GNDIO GNDIOAA5 GNDIO GNDIO

AA22 GNDIO GNDIOAA23 GNDIO GNDIOAA24 PIO PIOAA25 PIO PIOAA26 N.C. PIOAB1 PIO PIOAB2 PIO PIOAB3 PMOD/PIO/

A31PMOD/PIO/A31

AB4 GNDIO GNDIOAB5 GNDIO GNDIOAB6 GNDIO GNDIOAB7 GNDIO GNDIOAB8 GNDIO GNDIOAB9 VCCIO VCCIO

AB10 VCCIO VCCIOAB11 GNDIO GNDIOAB12 VCCIO VCCIOAB13 VCC VCCAB14 GND GNDAB15 VCCIO VCCIOAB16 GNDIO GNDIOAB17 VCCIO VCCIOAB18 VCCIO VCCIOAB19 GNDIO GNDIOAB20 GNDIO GNDIOAB21 GNDIO GNDIOAB22 GNDIO GNDIOAB23 GNDIO GNDIOAB24 D0/SDIN D0/SDINAB25 PIO PIOAB26 PIO PIOAC1 PIO PIOAC2 PIO/A30 PIO/A30AC3 PIO PIOAC4 GNDIO GNDIOAC5 GNDIO GNDIOAC6 GNDIO GNDIOAC7 PIO PIOAC8 PIO/GBUF4 PIO/GBUF4AC9 PIO PIO

AC10 PIO PIOAC11 N.C. PIOAC12 PIO PIOAC13 N.C. PIOAC14 PIO PIOAC15 PIO PIO


www.triscend.com 86

Ball TE520 TE532AC16 N.C. PIOAC17 PIO PIOAC18 N.C. PIOAC19 PIO PIOAC20 PIO PIOAC21 GNDIO GNDIOAC22 GNDIO GNDIOAC23 GNDIO GNDIOAC24 PIO PIOAC25 D1/PIO D1/PIOAC26 PIO PIOAD1 PIO PIOAD2 PIO PIOAD3 PIO PIOAD4 PIO PIOAD5 PIO PIOAD6 PIO PIOAD7 PIO PIOAD8 PIO PIOAD9 PIO PIO

AD10 PIO PIOAD11 PIO PIOAD12 PIO/GBUF3 PIO/GBUF3AD13 N.C. PIOAD14 PIO/GBUF2 PIO/GBUF2AD15 PIO PIOAD16 N.C. PIOAD17 N.C. PIOAD18 PIO PIOAD19 N.C. PIOAD20 PIO PIOAD21 PIO PIOAD22 PIO PIOAD23 PIO PIOAD24 PIO PIOAD25 PIO PIOAD26 PIO PIOAE1 PIO PIOAE2 PIO PIOAE3 PIO PIOAE4 PIO PIOAE5 PIO PIOAE6 PIO PIOAE7 PIO PIOAE8 PIO PIOAE9 PIO PIO

AE10 N.C. PIOAE11 N.C. PIOAE12 N.C. PIOAE13 PIO PIOAE14 PIO PIOAE15 PIO PIOAE16 PIO PIOAE17 PIO/GBUF1 PIO/GBUF1AE18 PIO PIOAE19 N.C. PIOAE20 PIO PIOAE21 PIO PIOAE22 PIO PIOAE23 PIO PIO

Ball TE520 TE532AE24 PIO PIOAE25 PIO PIOAE26 PIO PIOAF1 PIO PIOAF2 PIO PIOAF3 PIO/GBUF5 PIO/GBUF5AF4 PIO PIOAF5 PIO PIOAF6 PIO PIOAF7 PIO PIOAF8 PIO PIOAF9 PIO PIO

AF10 PIO PIOAF11 N.C. PIOAF12 N.C. PIOAF13 PIO PIOAF14 PIO PIOAF15 PIO PIOAF16 PIO PIOAF17 PIO PIOAF18 N.C. PIOAF19 PIO PIOAF20 N.C. PIOAF21 PIO PIOAF22 PIO/GBUF0 PIO/GBUF0AF23 PIO PIOAF24 PIO PIOAF25 PIO PIOAF26 PIO PIO

443366--ppiinn BBGGAA BBaallllss bbyy TTyyppee

PPaarraalllleell MMooddeeType TE520 TE532

PIO* 228 292VCC 4 3VCCIO 24 24GND 4 3GNDIO 72 72D[7:0] 8 8A[17:0] 18 18JTAG 4 4N.C. 64 2Others 8 8

SSeerriiaall MMooddeeType TE520 TE532

PIO* 252 316VCC 4 4VCCIO 24 24GND 4 3GNDIO 72 72SDIN 1 1SCLK 1 1JTAG 4 4N.C. 64 2Others 8 8

PIO* includes pure PIO pins andthose with alternate functions.

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Electrical and Timing Characteristics

AAbbssoolluuttee MMaaxxiimmuumm RRaattiinnggss

Symbol Parameter Min Max UnitsVCC Supply voltage relative to GND -0.5 4.0 VVIN Input voltage relative to GND (Note 1) -0.5 5.5 VVTS Voltage applied to three-state output (Note 1) -0.5 5.5 VTSTG Storage temperature (ambient) -60 +150 °C

TSOLMaximum soldering temperature (10 s at 1/16in. = 1.5 mm)

+260 °C

TJ Junction temperature, plastic packages +125 °C

Note 1: Maximum DC overshoot above VCC or undershoot below GND must be limited to either 0.5 V or 10 mA,whichever is easier to achieve. During transitions, device pins may undershoot to -2.0 V or overshoot to+7.0 V, provided that this condition lasts less than 10 ns and with less than 200 mA forcing current.

RReeccoommmmeennddeedd OOppeerraattiinngg CCoonnddiittiioonnss//DDCC CChhaarraacctteerriissttiiccss

Symbol Parameter Min Max UnitsTest

Conditions

VCCSupply voltage relative toGND

3.0 3.6 V

VIL Input Low voltage -0.5 30% VCC VVIH Input High voltage 50% VCC 5.5 V

VSSchmitt Hysteresis, hystere-sis mode

5% VCC 20% VCC V

TIN Input signal transition time 250 nsVOL Output Low voltage 0 10% VCC VVOH Output High voltage 90% VCC VCC V

VDR

Data retention supply volt-age (below which, initializa-tion data may be lost)

2.5 V

Commercial:TA=0° to +70° CTJ=0° to +85° C

IndustrialTA=-40° to +85° CTJ=-40° to +100° C

IOL Output Low current 1.5 mA @VOL maxIOH Output High current -0.5 mA @VOH minIIL Input leakage current -10 +10 uA @0<Vin<VCC

CIO Pin capacitance 10 pFLIO Pin inductance 20 nH

Note 1: Continuous static loads must fall within the IOH, IOL limits in this section.


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Triscend E5 Switching Characteristic Guidelines

For the most-recent timing parameters, visit the Triscend web site at:

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http://www.triscend.com/products

89 www.triscend.com

Output Buffer Switching Characteristics

0

10

20

30

40

50

60

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Output Voltage (V)

Ou

tpu

t C

urr

ent

(mA

)

IOL

IOH

Figure 43. 12 mA output buffer characteristics (TJ= 25ºC, VCCIO=3.3 Volts), HSpice simulation.

0

10

20

30

40

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Output Voltage (V)

Ou

tpu

t C

urr

ent

(mA

)

IOL

IOH

Figure 44. 12 mA output buffer characteristics (TJ= 85ºC, VCCIO=3.0 Volts), HSpice simulation.


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Ordering Information

TE5 20 S 40 - 40 Q CTriscend E5

ConfigurableSystem-on-Chip

Family


(CSL) Cells x 100(approximate)

Memory Size(K bytes)

Temperature RangeC = Commercial I = Industrial

Package StyleL = 128-pin Plastic Quad Flat PackQ = 208-pin Plastic Quad Flat PackB = 436-pin Ball-Grid Array

Maximum processorand CSI bus frequency(MHz)

Device Type

TE502S08TE505S16TE512S16TE520S40TE532S64

Sales OfficesHHeeaaddqquuaarrtteerrss

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Tel: 1-650-968-8668Fax: 1-650-934-9393Web: www.triscend.comE-mail:

[email protected]

Triscend Europe5 Bridlington SpurWindsor MeadowsSlough, England SL19JZUNITED KINGDOM

Tel: +44 1-753-674023Fax: +44 1-753-674016

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Triscend, the Triscend logo, and FastChip are trademarks of Triscend Corporation. All other trademarks are theproperty of their respective owners.

Triscend Corporation does not assume liability resulting from the application or use of any product describedherein. No circuit patent licenses are implied. Triscend Corporation reserves the right to make changes withoutnotice to any product herein to improve reliability, function, or design. Patents pending.

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C O N T E N T S

OVERVIEW .............................................................. 3

8032 "TURBO" MICROCONTROLLER ........................ 5

Programmable I/O Ports .................................... 5UART ................................................................. 5Timers ................................................................ 5Interrupts ............................................................ 6Data Pointers ..................................................... 6Power Management ........................................... 6Power-On reset .................................................. 6

DMA CONTROLLER................................................. 6

Functional Description........................................ 7DMA Initialization and Termination .................... 7Transfer Modes.................................................. 7Bus Address Generation.................................... 8Data FIFO .......................................................... 8CRC Feature...................................................... 8Interrupts Generation ......................................... 8Configuration Registers ..................................... 9Interfacing CSL Peripherals to the DMAController.......................................................... 12

CONFIGURABLE SYSTEM INTERCONNECT (CSI) BUS15

Data Read Bus................................................. 15Data Write Bus................................................. 15Address Bus..................................................... 15Address Selectors............................................ 15Address Selector Operation............................. 16Address Specification ...................................... 16Address Selector Modes.................................. 17Wait-State Monitor and Control Signals........... 17Breakpoint Event Monitor and Control Signals 18CSI Bus Transactions ...................................... 18Side-band Signals ............................................ 20

CONFIGURABLE SYSTEM LOGIC (CSL)................... 21

Bank Resources............................................... 22CSL Cell Capabilities ....................................... 25Logic Functions................................................ 25Arithmetic Functions ........................................ 25Memory Functions............................................ 27Sequential Functions........................................ 28

PROGRAMMABLE INPUT/OUTPUT (PIO) PINS...........29

Creating a PIO Port for the Microcontroller ......295-Volt Tolerant I/Os ..........................................29Storage Elements .............................................29PIO Input Side ..................................................30PIO Output Side................................................30Other PIO Options ............................................30Low-Power Mode..............................................31JTAG Support...................................................31Default, Unconfigured State .............................31Default, Configured State .................................31Electro-static Discharge (ESD) Protection........31

MEMORY INTERFACE UNIT ......................................32

Functional Description ......................................32Initialization of the MIU .....................................34MIU Register Description..................................34

ADDRESS MAPPERS ...............................................36

Code mappers ..................................................38C1, C2 – Fully programmable code mappers...39Data mappers ...................................................40SFR export mapper ..........................................42Default Values for Higher-Order AddressMappers............................................................42

SYSTEM DEBUGGER...............................................43

CONFIGURATION REGISTER UNIT (CRU) .................45

SYSTEM INITIALIZATION ..........................................45

Parallel Mode....................................................46Serial Initialization .............................................46JTAG Initialization.............................................47Slave Mode.......................................................48'Stealth' Mode ...................................................48Size of Initialization Data...................................49Time to Initialize an E5 CSoC Device...............49VSYS Control....................................................50

CLOCKING AND GLOBAL SIGNAL DISTRIBUTION.......50

System clock select (BCLK) .............................50Six Global Buffers.............................................51Clock and Global Signal Stopping ....................51


ii

8032 “TURBO” MICROCONTROLLER ARCHITECTURE

............................................................................. 51

ALU .................................................................. 51Accumulator ..................................................... 51B Register ........................................................ 52Program Status Word ...................................... 52Data Pointers ................................................... 52Scratch-pad RAM............................................. 52Stack Pointer.................................................... 52Timers/Counters .............................................. 52Memory Organization....................................... 52Special Function Registers .............................. 54

INSTRUCTION SET.................................................. 60

Addressing Modes ........................................... 61Immediate Addressing ..................................... 62

INTERRUPTS .......................................................... 62

Interrupt Sources ............................................. 62Priority Level Structure..................................... 63External Interrupts............................................ 64Response Time................................................ 65

RESET CONDITIONS ............................................... 65

Power-On Reset (POR) ................................... 66RST- Device Pin............................................... 66JTAG Reset ..................................................... 66Application Reset via RSTC Sideband Signal.. 66Watchdog Timer Reset .................................... 66System Behavior after a Reset Event .............. 66Microcontroller Reset State.............................. 67

POWER MANAGEMENT........................................... 67

Power Management ......................................... 67Power Saving ................................................... 68Shutting Down the Crystal Oscillator................ 69Restarting the Crystal Oscillator after ExitingPower-Down Mode........................................... 69Exiting Power-Down Mode............................... 69

GLOSSARY ............................................................ 70

LIFE SUPPORT POLICY........................................... 70

PIN DESCRIPTION .................................................. 71

PINOUT DIAGRAMS AND TABLES .............................73

Available Packages and Package Codes.........73Footprint-Compatibility......................................73Available PIOs by Package ..............................73128-pin Thin Plastic Quad Flat Pack, top view(Package Code=L)............................................74128-pin thin PQFP (Package Code=L) PackagePinout Tables....................................................75128-Pin LQFP Pins by Type .............................76128-pin thin PQFP (Package Code=L) PackageMechanical Drawing .........................................77208-pin Plastic Quad Flat Pack, top view(Package Code=Q)...........................................78208-pin PQFP (Package Code=Q) PackagePinout Tables....................................................79208-pin PQFP Pins by Type .............................81208-pin PQFP (Package Code=Q) PackageMechanical Drawing .........................................82436-ball Ball-Grid Array Package, top view(Package Code=B) ...........................................83436-ball Ball-Grid Array (Package Code=B)Package Pinout Tables.....................................84436-pin BGA Balls by Type...............................86

ELECTRICAL AND TIMING CHARACTERISTICS ...........87

Absolute Maximum Ratings..............................87Recommended Operating Conditions/DCCharacteristics..................................................87

TRISCEND E5 SWITCHING CHARACTERISTIC

GUIDELINES ...........................................................88

OUTPUT BUFFER SWITCHING CHARACTERISTICS .....89

ORDERING INFORMATION........................................90

SALES OFFICES .....................................................90

Headquarters ....................................................90Sales Representatives......................................90U.S. Distribution................................................90Japan................................................................90Europe/Middle-East ..........................................90Israel .................................................................90Asia-Pacific .......................................................90

Documents

DIAKOM · ® Triscend E5 Configurable System-on-Chip Family January, 2000 (Version 1.00) Product Description © 1998-2000 by Triscend Corporation. All rights reserved. Patents