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林永隆 (Youn-Long Lin)Department of Computer Scienc
eNational Tsing Hua University
High-Level Synthesisof VLSIs
THEDA Tsing Hua Electronic Design Automation
2
VLSI Design Tools
• Design Capturing/Entry• Analysis and Characterization• Synthesis/Optimization
– Physical (Floor planning, Placement, Routing)
– Logic (FSM, Retiming, Sizing, DFT)– High Level(RTL, Behavioral)
• Management
3
Design Methodology Progress
Capture and Simulate
Describe and Synthesis
Specify and ???
4
Productivity
Re-Targetability
Correctness
Why Synthesis?
Unsynthesizability
Performance Loss
Inertial
Why not Synthesis?
5
Structural Behavioral
Physical
X’tor
Gate
RTL
Block
Boolean
FSM
Algorithm
GDSII
Placement
Floorplan
Y-ChartDan D Gajski
6
Structural Behavioral
Physical
X’tor
Gate
RTL
Block
Boolean
FSM
Algorithm
GDSII
Placement
Floorplan
LayoutSynthesis
7
Structural Behavioral
Physical
X’tor
Gate
RTL
Block
Boolean
FSM
Algorithm
GDSII
Placement
Floorplan
LogicSynthesis
8
Structural Behavioral
Physical
X’tor
Gate
RTL
Block
Boolean
FSM
Algorithm
GDSII
Placement
Floorplan
High-LevelSynthesis
9
High Level Synthesis
CDFG
Parsing
Transformation
Synthesis
StructuralRTL
BehavioralDescription
10
What Went Wrong?
• Too much emphasis on incremental work on algorithms and point tools
• Unrealistic assumption on component capability, architectures, timing, etc
• Lack of quality-measurement from the low level
• Too much promising on fully automation (silicon compiler??)
11
Essential Issues
• Behavioral Specification Languages
• Target Architectures
• Intermediate Representation
• Operation Scheduling
• Allocation/Binding
• Control Generation
12
Behavioral Specification Languages
• Add hardware-specific constructs to existing languages– HardwareC
• Popular HDL– Verilog, VHDL
• Synthesis-oriented HDL– UDL/I
13
Target Architectures
• Bus-based
• Multiplexer-based
• Register file
• Pipelined
• RISC, VLIW
• Interface Protocol
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Design Space Exploration
Arch I
Arch II
Arch III
Dela
y
Area
15
FSM with Data Path (FSMD)
FSMDataPath
FSMDataPath
FSMDataPath
Interactive FSMDs
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Intermediate Representation
* *+
Control Flow Graph
Data Flow Graph
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Scheduling (Temporal Binding)
• Time & Resource Tradeoff• Time-Constrained
– Integer Linear Programming (ILP)– Force-Directed
• Resource-Constrained– List Scheduling
• Other Heuristics– Simulated Annealing, Tabu Search, ...
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Allocation/Binding
Functional UnitsOperations
StorageVariablesSignals
Bus/Wire/MuxData Transfers
19
RF
FUFU
RF
Variables/Signals
Data Transfer
Operations
20
Controller Specification Generation
ScheduledCDFG
AllocatedDatapath
Micro-Operationsfor
Every Control Step
21
HLS Quality Measures
• Performance
• Area Cost
• Power Consumption
• Testability
• Reusability
22
Hardware Variations
• Functional Units– Pipelined, Multi-Cycle, Chained, Multi-
Function
• Storage– Register, RF, Multi-Ported, RAM, ROM,
FIFO, Distributed
• Interconnect– Bus, Segmented Bus, Mux, Protocol-Based
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Functional Unit Variations
+**
**
-+
Step 1
Step 2
Step 3
Step 4
+
++
24
Storage/Interconnect Variations
RF
FUFU
RFSegmentedBuses
DistributedFIFO
Mux
Chaining
Multi-Port
25
Architectural Pipelining
FSMDataPath
26
THEDA’s Work on HLS
• ILP-based Scheduling• Bipartite Weighted Matching for Datapath
Allocation• Performance-Driven Interconnect Synthesis• Loop Folding & Retiming• Integrating Synthesis and Layout• DSP Core Generation• Book on HLS
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Integer Linear Programming for Scheduling
• Given # Control Steps• ASAP + ALAP ==> Possible Steps for
each Operations• Tight Constraints on
– Dependency– One Scheduled Step per Op– Resource Usage per Step
• Many Extensions
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Advanced Scheduling for Loop Folding
1
2
33
2
1
1 iteration per 3 cycles 1 iteration per 2 cycles
29
Loop Folding(cont.)
1
2
3
Prologue
Epilogue
Folded Body
30
Retiming and Loop Folding
1
2
3
BA C D E F BA C D E F
1
2
3
BACD
E
F B
AC
D
E
F
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Integrating Layout and Synthesis
HDL Description
HDL Synthesis RC Extraction &Delay Calculation
Chip Layout
Post-LayoutTiming Analysis
Module Resynthesis
Timing Ok & no morearea improvement
P&R
Soft-MacroPlacement
Block Placement
Soft-MacroFormation
No
Module ResynthesisSoft-MacroPlacement
Soft-MacroFormation
32
HLS Techniques for DSP Code Generation
Memory Allocation
SchedulingAddress Generation
33
Applications of HLS Technology
• Code generation for embedded processors
• Retargetable compilers for application-specific instruction-set processors (ASIP)
• Reconfigurable computing
• Advanced features in logic synthesizer
34
System-on-a-Chip
Processor Memory
ExternalMemoryInterface
IPBus Master UART
WirelessB
ridg
e US
B
35
SOC with PLDs
Processor Memory
ExternalMemoryInterface
FPGABus Master FPGA
WirelessB
ridg
e US
B
36
WaferFoundry
SystemHouses/
IC Vendors(Fabless)
Integrators
Library/IP
Vendors(Chipless)
EDAVendors
Paradigm Shift
37
IP and Synthesis
• Authoring IP for Synthesis
• Synthesis utilizing IP
• Synthesizing IPs
Executable Data Sheets
38
Executable Data Sheets
IP
IP WrapperMore thanjust thePort Interface
39
Future Directions
• Realistic Methodology– Evolutional Transition from Current
Practice– Domain Specific
• IP-Centric– As both Authoring Aid and Integrator
• Software– Co-design and Code Generation
40
Valu
e
Time
EDA
IP
IC