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CMOS INVERTER

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The CMOS Inver t er St a t ic Mode l

Outline First Glance Digital Gate Characterization Static Behavior (Robustness)

VTC Switching Threshold Noise Margins

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The CMOS Inver t er :

A Fi rs t Glanc e

VDD

Vinout

CL


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CMOS Invert ers (1)

VDD

PMOS

InOut

1.2m= 2

Polysilicon

Metal1

GND

NMOS


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CMOS Inver t er Opera t ion Pr inc ip le

1 0

VOH = VDD VOL = 0 5.2


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Dig i t a l Gat e Fundam ent a l

Parameters Functionality

Reliabilit Robustness

Area Performance

Power Consumption

Energy


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The Ideal Invert er

V

Ri =

R =

g =-


in

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St at ic CMOS Propert ies

Basic inverter belongs to class of staticcircuits: output always connected to either

DD SS.

Rail to rail voltage swing

Ratio less design

Low output impedanceV

Extremely high input impedance

No static power dissipation

Good noise properties/margins

V

g =-


{TPS}: prioritize the list above

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Voltage Transfer Characteristic (VTC)

5.2


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Load L ine (Ck t Theory)

2.5ID

[10-4 A]

2.5V

B2.0=

VGS = 2.5V

VGS

A1.0

1.5

VGS = 1.5V

.

0.5 VGS = 1.0VVinVout

0V

Exercise:

0 0.5 1.0 1.5 2.0 2.5DS

The blue load line A corresponds to R =The orange load line B corresponds to R =

With load line A and V = 1V V =

12.5k25k

a rox 1.6 V


Draw a graph Vout(Vin) for load line A and B

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PMOS Load Lines VDD-

Goal: Combine IDn and IDp in one graph ++

-VDSp

IDp

rc o :

Vin = VDD + VGSp

Vin out

IDnDn DpVout = VDD + VDSp

Dp DnV =0

in

in

V =3

DnVin=0

Vin=3

VDSp

VGSp=-5

VGSp=-2VoutVDSp


Vout = VDD + VDSpin DD GSp

IDn = - IDp

Example: VDD=5V

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CMOS Inver t er Load Charac t er is t ic s

I ,Vin

= 5Vin= 0

NMOSPMOS

Vin= 4V = 1

Vin= 3Vin= 2 V = 2V = 3

Vin= 1

Vin= 4

Vin= 4

Vin= 5

Vin= 2Vin= 3

Vin= 0Vin= 1

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CMOS Invert er VTC

Vout

4

In,p

Vin = 5Vin = 0

NMOSPMOS

2

3Vin = 4

Vin = 3

Vin = 1

Vin = 2 V = 2V = 3

Vin = 4

1Vin = 0

Vin = 1

Vin = 4

Vin = 5

Vin = 2Vin = 3

Vin1 2 3 4 5


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Operat ing

Condi t ions

Need to know for proper dimensioning,analysis of noise margin, etc.

Vout = Vin - VTp

Vout

Vdd

NMOS

1 Vin = VGS < VTn off

Vout = Vin - VTn2 Vout > Vin - VTn

VDS > VGS - VTnVdd - |VTp|

V VV

- VTp

V

VGD < VTn saturation

3 Vout < Vin - VTn resistive

1 2 3PMOS

4 in DD Tp55 Vout < Vin - VTp saturation

6

Exercise: check


6 Vout > Vin - VTp resistiveresults for PMOS

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Operat ing Condi t ions

Vout = Vin - VTp

Vout

Vdd

2 saturation3 resistive

Vout = Vin - VTn

5 saturation6 resistive

Vdd - |VTp|

V VV

- VTp

V

Vout

5

NMOS off

PMOS lin

1 2 33

4

NMOS sat

saPMOS lin

456

1

2

NMOS lin

sat

NMOS linPMOS sat


Vin1 2 3 4 5

o

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Inverter Static Behavior egenera onNoise margins e ay me r cs

5.3


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The Rea l is t i c Inver t er

Vout 2.5Vout [V]

Ri =

Ro= 0 1.5

2.0

g =-

0.5

1.0

V0 0.5 1.0 1.5 2.0 2.5

VIN [V]

Ideal InverterRealistic Inverter


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The Regenerat ive Proper t y

A chain of inverters

RegenerativeProperty: ability to

a weak signal in achain of gates


The regenerative property. .

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The Regenerat ive Proper t y (2)

v0 v1 v2 v3 v4 v5 v6...

.

v1, v3, ... v1, v3, ...

f(v) finv(v)

finv(v) f(v)

v0, v2, ... v0, v2, ...

b Re enerative ate c Non-re enerative ate


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The regenerat ive Proper t y (3)

Exercise: what is the output voltage of a chain of 4nver ers w a p ece-w se near pass ng roug ,

10), (3,7), (7,1) and (10,0) [Volt], as the result of an input

voltage of 6 [Volt].

Exercise: discuss the behavior for an input of 5 [Volt]


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Inver t er Sw i t c h ing Thresho ldAnaly t ic a l Der ivat ion

VM is Vin such that Vin = Vout

VDS = VGS VGD = 0 saturation

Assume VDSAT < VM - VT

(velocity saturation)

Ignore channel length modulation

VM follows from

= -n p

5.3.1


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Inver t er Sw i t c h ing Threshold

A nal t i c al Der i vat i on c d

2/VVVkVI DSATTGSDSATD IDSATn(VM) = - IDSATp(VM)

2/VVVV DSATnTnMDSATn n2/VVVVVk

2/VVVVk DSATnTnMDSATp n

kL

W

k'

P

2/VVVVk)L/W('

DSATnTnMDSAT'np n

ppnP

See Example 5.1:


p . n DD Usually: Ln = Lp

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Gat e Sw i t c h ing Thresho ld

w /o Veloc i t y Sat ura t ion

Long channel approximation

Also applicable with low VDD

4.0

Exercise (Problem 5.1):-

3.0

VM

channel approximation

as shown below

1.0

2.0

. . . . .

kp/kn

pTnTpDD krwith

r

)VVV(rVM 1


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Noise in Dig i t a l In t egrat ed Ci rc u i t s

VDDv(t)

i t

(a) Inductive coupling (b) Capacitive coupling c ower an groun

noise

Study behavior of static CMOS Gates with noisysignals


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Noise Margins

VOH

DD

VOL

VIL VIHVDD0

1.3.2 5.3.2

VOL = Output Low Voltage

V = In ut Low Volta e


VOH, VIH =

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Noise Margins

VOL = Output Low Voltage

VIL = Input Low Voltage


VOH, VIH =

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Noise Margins

NMH = VOH - VIH = High Noise Margin


L = IL - OL = ow o se arg n

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Noise Marg in for Real is t ic Gat es

VOL not well defined

Conveniently relate to slope s = -1


{TPS}: explain significance of slope = -1 for noise margin

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Noise Marg in Calc u la t ion

Piece-wise linearapproximation of g = gain factor

e now owto compute VM

w

VVVVV DDOLOHILIH

compute g

g

VVV MMIH

g

VVVV MDDMIL


IHDDH VVN ILL VN

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Noise Margin Calc u lat ion (2)

outnDSATnTninDSATn V/VVVVk n 12

out . in in

012 DDpoutpDSATpTpDDinDSATp VV/VVVVVkP

out rdV 1 DSATVkpnDSATpTMVVin

/VVVdVMin

2

Mostly determined by technologyDSATnnVk

See example 5.2

Exercise: verify calculation

Exercise: explain why we add channel lengthmodulation to the IDexpressions (we did not do


this to determine VM)

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Gain as a func t ion of VDD

pnDSATpTMVVin

out

/VVV

r

dV

dVg

in2

1consider

2

2.5

0.15

0.2

1.5

Vout(

V)

0.1

V

out

(V)

Gain=-1

0.5

0.05

0 0.5 1 1.5 2 2.50

Vin

(V)

0 0.05 0.1 0.15 0.20

Vin

(V)


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Dynam ic Noise Marg in

Previous definition was Static Noise Margin

Dynamic Noise Margin: how does noise energyeterm ne e av or

A short pulse may have higher amplitude than a

Short spikes may safely exceed Static Noise

Margin

mplitude

isePulse


No

Noise Pulse Duration

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CMOS INVERTERdynam ic behav ior (per fo rm anc e)

Capacitances (Dis)charge timesDelay

5.4


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Delay as a func t ion o f VDD

5.5

4.5

ed)

52.0'

DDLHL

VCt

3

3.5

r

maliz DSATnTnDDSATnnn

2

2.5

tp

(N Spice

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

Fg.5.17


VDD (V)

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Sizing

Propagation Delay tp can be reduced by

Increasing VDD (until VDD >> VT + VDSAT/2)

Increasing W

Reducing CL

WVVVVkLW

VCt L

DSATnTnDDDSATnnn

DDLpHL

)2/()/(

52.0

'

CL can be reduced by good layout design

u par o L epen s on


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t p as a func t ion of Wp/Wn

5x 10-11

Ipd tpHL

4.5

(sec) t

pHL

pLH WnCD tpLH

3.5

tp

(tpHL + tpLH)/2

31 1.5 2 2.5 3 3.5 4 4.5 5

p

Wp/Wn

Min t in general not when t LH = t HL


Save area, time at expense of robustness

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TUD/EE ET4293 - DigIC - 11/12 - NvdM - 03 Inverter 07 inductance 42

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In t r ins ic vs Ex t r ins ic vs Paras it i c Load Cap

CGS4

VDDVDD

M

CDB2VoutV

CGS3

CDB1

+

ou

M3

CW1

Cint = CDB1 + CDB2 + 2(CGD1 + CGD2) Cext = CGS3 + CGS4 + CGD3 + CGD4

Intrinsic loadExtrinsic / fan-out load


par = w

I l t d I t Si i

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Iso lat ed Inver t er Sizing

int

extinteqextinteqp

C

CCRCCRt 169.0)(69.0

par ignored or its effect canbe absorbed in other C

R0: resistance of minimum size inverter(assume proper = Wp/ Wnratio)

C0: intrinsic load (output, drain) cap of min. size inverter

t =0.6 R C:intrinsic or unloaded delay

basic time constant for technology

DDS: sizing factor for Wn, Wpof driving inverter

Wn= S Wmin, Wp= S Wmin

Req= R0/S Cint= SC0


00 1

SCtt pp

I l t d I t Si i

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Iso lat ed Inver t er Sizing

00 1

SC

Ctt extpp

Increasing S reduces delay until SC0>> Cext

tp

S

p0


Cext

I t Ch i

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Inver t er Chain

Assume size of inverter 1 is fixed.

Increasing S of inverter 2 reduces tpof inverter 2

InOut

p

Expect an optimum!

CL

{TPS} If CL is given and knowing properties of input source:

- How many stages are needed to minimize the delay?- How to size the inverters?


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Example

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Example

In Out

L 1

C1 = Cgin,1

1 f f

CL/C1 has to be evenly distributed across N= 3 stages:

283f 19813 03

0 forttt ppp


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O i Ef f i F f

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Opt im um Ef fec t ive Fanout f

Optimum ffor given process defined by

fN

ln

ln

ff 1exp

,up or down to integer value)

=0 =1

fopt e=2.72 3.6

Nopt lnF 0.78lnF


Normal ized t vs f

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Normal ized tp vs. f

With Self-Loadin =1,

Slight increase of tp forf > fopt

fopt = 3.6 Choosing too few

stages (f > fopt) isrelatively harmless for

Too many stages isexpensive in terms of


http://en.wikipedia.org/wiki/FO4

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Pow er Dens it y

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y

Estimate Furnace: 2000 Watt r=10cm P 6Watt/cm2

Processor chip: 100 Watt, 3cm2 P 33Watt/cm2

Power-aware desi n desi n for low ower is


blossoming subfield of VLSI Design

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Where Does Pow er Go in CMOS

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Dynamic Power Consumption

Short Circuit Currentsw

switching (NMOS and PMOS on together)

Leakage

Leaking diodes and transistors

May be important for battery-operated equipment


Dynam ic Pow er

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Dynamic Power Ei= energy of switching event i

depends on process, layout =

i

iE

T

P1

Ei= Power-Delay-Product P-D

important quality measure

Energy-Delay-Product E-D

combines ower s eed erformance


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Low -t o-High Trans i t ion Energy

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vDD

i(t)

C

v0(t)

E Ener delivered b su l

dtVtiE DDVDD

DDV

DD dtdt

dvCV 0

2DD

CV

2221 DDcDDV CVECVE DD


Where is the rest? Dissipated in transistor

Low -t o-High Trans i t ion Energyv

DD

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vDD

i(t)

C

v0(t)

dtvViE DDdiss 0

0 00dtivdtiVDD


cV EE D

High-t o-Low Trans i t ion Energy

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qu va en c rcuC

i

Exercise: Show that the energy that is dissipatedin the transistor upon discharging C from VDD to

= 2 ss


Com pare Charg ing St rat egies

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Ci CdT

I TConstant voltage Constant current

+

-

V

CI

C

R

2T

RE I RI dt I RI dt RI T C

R R CdV

E V idt V V C dt

dt

2

0

1

2

V

c CV V CdV CV 2RCCV

T

Reduced dissipation if T > 2RC = t76% Difficult to reap benefits in practice


See Adiabatic Logic

CMOS Dynam ic Pow er Diss ipat ion

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stransition#EnergyEnergyPower

merans onme

fCVD2

Independent of transistor on-resistances

Can only reduce C, VDDor fto reduce power


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|VDSp| Short Ci rc u i t Current

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Input and output waveforms ofinverter loaded with a largecapacitance (top) and with a smallinput

|VTp|

.

Short-circuit current increases with|VDSp|. This is clearly much larger

waveform

VTn

output for

large CL

on average for small CL comparedto large CL.

Similarl short-circuit current canexist for low-to-high transition atoutput.

Tp|VDSp|

VTn output forsmall CL


NMOSturns on

PMOSturns off

Short Ci rc u i t Current

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Pull-up turns offbefore VDSp becomess gn can


Best to maintain approximately equal input/output slopes

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Sub-ThresholdCurrent

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Rapidly becomesbottleneck with lowering

threshold voltages Modern technologies offer

low-Vt and hi-Vt devicesBalance speed and power

Y. Taur, CMOS design near the limit


, , ,Numbers 2/3, 2002

Sub-Threshold Cur ren t

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Rapidly becomes bottleneck with lowering thresholdvoltages

Modern technologies offer low-Vt and hi-Vt devicesBalance speed and power

-

10-2

Linear-

10-2

Linear

10-8

10-6 Quadratic

ID(A)

10-8

10-6 Quadratic

ID(A)

10-120 0.5 1 1.5 2 2.5

10-10

VT

Exponential

10-120 0.5 1 1.5 2 2.50 0.5 1 1.5 2 2.5

10-10

VT

Exponential


VGS (V)VGS (V)

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Transis t or Sizing for Min im um Energy

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In Out

CL= FCG1C

G1

1 f

Goal: Minimize Energy of whole circuit

Desi n arame ers: fan V52.0DDLVC

t tp tpref of circuit with f= 1 and VDD= Vref

)2/()/( DSATnTnDDDSATnnn VVVVkLW

DD

pp

Vf

tt0

11

See E . 5.21

Ex.5.13


TEDD VV

VTE= VT VDSAT :Effective VT

Trans ist or Sizing (2)

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TEDD

DDppp

VV

Vt

f

Fftt 00 11

22F

fF

f

Performance Constraint (with = 1, tpref f=1):

1330

0

F

f

VVVF

f

tt TEDD

TEref

ref

DD

refp

p

pref

p

TE: ec no ogy . , ref: s an ar supp y .

F: fanout

VDD, f: design parameters

VDD is a function of f, given a fixed performance

Ff 515


fFFff 108814

Trans ist or Sizing (3)

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DD=

4

F=1

2

2.53

.

)

Supply voltage neededas a function of ftomaintain reference

5

1.5

2vdd( per ormance

Lowest supply voltageneeded for f= F0.5

200.5

1

fFFff

fVDD

108814

5152

1 2 3 4 5 6 7

f


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Trans ist or Sizing (5)ref

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1.5

1den

ergy

F

Ff

V

V

E

E

ref

DD

ref 4

222

F

Ff

V

V

E

E

ref

DD

ref 4

222

0.5ormalize

0

f Device sizing is effective


Optimal sizing for energy slightly different from sizing for performance

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Also see: IBM JRD, Vol 46, no 2/3, 2002

Scaling CMOS to the limit

http://www.research.ibm.com/journal/rd46-23.html

5.6


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Why Sc al ing

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Reduce price per function:

chip for the same money better products

Build same roducts chea er, sell the samepart for less money larger market

Price of a transistor has to be reduced

ut a so want to e aster, sma er, ower power


Sc al ing Models

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Fixed Voltage Scaling

most common model until 1990s

only dimensions scale, voltages remain constant

ideal model dimensions and voltage scale together bythe same factor S

General Scaling

most realistic for todays situation

voltages and dimensions scale with different factors


Sc al ing for Ve loc i t y Sat ura ted Dev ic es=

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Parameter Relation General Scaling

W, L, tox 1/S

VDD, VT 1/U

NSUB V / Wdepl2

S2

/U2

Cox 1/tox S

Cgate CoxW L 1/S

n, p ox

Isat CoxW V 1/U

Current Density I sat / Area S 2/U

Ron V / Isat 1

Intrinsic Delay RonCgate 1/S

2


sa

Power Density P / Area S 2/U2

IC Tec hnology Sc al ing

S li i d it d f

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Scaling improves density and performance

First order scaling theory

dimensions, 1/S

voltages 1/S

2008 / 1971

0.007

0.007

intrinsic delay 1/S

power per transistor 1/S20.007

0.00004

Scaling trend

2008 201019821971


first proc (65nm)

Tec hnology Prac t i c e & ITRS

Scaling Technology Generations

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Scaling Technology Generations S 1.4 20.5 per generation

ITRS: International Technology Roadmap for Semiconductors-

developments and (planning) requirements

htt ://www.itrs.net/home.html


(and a self-fulfilling prophecy at the same time)

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Summary

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Digital Gate Characterization ( 1.3).

VTC

Switching Thresholdo se arg ns

Dynamic Behavior (Performance) ( 5.4)CapacitancesDelay

Power ( 5.5)

Scaling ( 5.6)


Documents

03 Inverter