03 System Architecture

8/8/2019 03 System Architecture

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ELE 3230 - Part 3 1

Par t 3

8088 Sys tem Arc h it ec t u re

(Hal l : c h2; Brey : c h2; Tr iebel : c h2)

ELE 3230Mic roproc essors and Com put er Sys tems


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ELE 3230 - Part 3 2

His t o r i c a l Bac k ground

1969/70 Intel 4004, first Microprocessor (M.E.Hoff) 4 bit microprocessor, originallydeveloped for Busicom, a small Japanese calculator company. Limited to 4096 memorylocation (of 4 bit data), 45 instructions; integrated 2300 PMOS transistors.

1971 Intel 8008, first 8 bit microprocessor (16K x 8bit)

1973 Intel 8080, 10 x faster than 8008, more memory (64k)

1974 Other 8 bit processors: Motorola 6800, Fairchild F8,

1975 Signetic 2650, MOS Technology 6502 (used in Apple II), Rockwell PPS-8

1976 National IMP-PACE, first 16 bit microprocessor, followed by Texas Instrument,TMS9900, Zilog Z80 (8 bit) (used in Radio Shack TRS-80)

1977 Intel 8085 (8080 with built-in clock & system controller) 1978 Motorola 6809 (8 bit), Intel 8086 (16 bit processor, 1M)

1978/79 Intel 8088 - variant of 8086 with 8 external data pins

1981 IBM adopts Intel 8088 for IBM PC/XT

(see http://bwrc.eecs.berkeley.edu/CIC/archive/cpu_history.html )

2 most popular microprocessor series:

INTEL 8086, 80186, 80286, 80386, 80486, Pentium

Motorola 68000, 68010, 68020, 68030, 68040


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ELE 3230 - Part 3 3

Mic roproc essor Com put er Sys t em

CentralProcessing

Unit (CPU)

InputOutput

Unit

(I/O Unit)

Memory

Data Bus

Address Bus

Control Bus

Control Bus

Processor Bus

Co-Processor(e.g. Floating point unit)

Control Unit (CU)

Registers

Arithmetic & LogicUnit (ALU)

Data Bus

Address Bus


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ELE 3230 - Part 3 4

Mic roproc essor Com put er Sys t em

Control Unit (CU) generates all the control signals within theCPU. It initializes the registers on power-up, generates thesignal to fetch instructions for the ALU.

The Control unit may be implemented (i) completely byhardware (hard-wired controller e.g. using a state counterand a Programmable Logic Array) or (ii) by a mixture of

software instructions (microcode stored in CPU) andhardware (microprogrammed control). Both the Intel 8086family and Motorola 68000 family use microprogrammedcontrollers.

Registers - small, fast memory which usually store data andaddresses associated with the instruction being carried out.

ALU performs arithmetic and logic operations

CentralProcessing

Unit (CPU)

Control Unit (CU)Control Unit (CU)

RegistersRegisters




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ELE 3230 - Part 3 5

Ins t ruc t ion Ex ec ut ion Cyc le

Two main steps in the cycle:

1. Fetch the next instruction from main memory

2. Decode and Execute the instructionThe Fetch cycle consists of

i) use the instruction pointer (IP) to set the address bus with the

address of the next instruction and increment the instruction pointer;

ii) wait (few hundred nanoseconds) for data to be transferred to the

data bus from memory; and

iii) read the data from the data bus.

The Execution Cycle consists of

i) Decode the instruction and generate the correct sequence of internal

and external signals

ii) Execute the instruction and restart the Fetch Cycle


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ELE 3230 - Part 3 6

Bas ic Ins t ruc t ion Cyc le

HALT

Fetch the

NextInstruction

Executethe

Instruction

START

Fetch Cycle

Execute Cycle


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ELE 3230 - Part 3 7

Pipel ined Inst ruc t ion Fet c h and

Ex ec ut ion Cyc lesInstruction Fetch and Execution pipeline

Fetch Fetch FetchExecute Execute Execute Fetch

The Fetch and Execution are implemented by two process unitsinside CPU:

Bus Interface Unit (BIU) fetches instructions from memory, passes theinstruction to the instruction stream byte queue and starts to fetch thenext instruction immediately

Execution Unit (EU) removes instructions from the instruction queue

What are the advantages of allocating the functions to two separate units?

Both BIU and EU can be working simultaneously without waiting for thecompletion of the other task (pipelined parallel processing)

Is this efficient? How to improve it?


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ELE 3230 - Part 3 8

Tim ing Diagram for Inst ruc t ion

Pipel ine Operat ion

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Instruction 5

Instruction 6

Instruction 7

Instruction 8

Instruction 9

FI DI CO FO EI WO

FI DI CO FO EI WO

FI DI CO FO EI WO

FI DI CO FO EI WO

FI DI CO FO EI WO

FI DI CO FO EI WO

FI DI CO FO EI WO

FI DI CO FO EI WO

FI DI CO FO EI WO

1 2 3 4 65 7 8 9 10 11 12 13 14

Time

I: InstructionO: Operand

Fetch Instruction Decode Instruction Check Operand Fetch Operand (if needed) Execute Instruction Write Output

(Operand is defined in the Instruction Set part)


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ELE 3230 - Part 3 9

In t roduc t ion t o In t e l 8086/8088

Microprocessors

8086 pin diagram

GND

AD14AD13AD12

AD10AD11

AD8AD9

AD6AD7

AD4

AD5

AD3AD2AD1AD0

NM1INTRCLK

GND

(ALE)

(HLDA)

(HOLD)

(WR)

(IO/M)(DT/R)

(DEN)

(INTA)

27

7

14

11

1

23

45

6

8

910

12

13

1615

17

1918

20

34

30

40

3938

37

36

35

33

3231

29

28

2526

24

2223

21

8086CPU

MAXMODE

{ }MIN

MODE

A19/S6

A17/S4A18/S5

A16/S3AD15

Vcc

READYRESET

BHE/S7MN/MX

RDRQ/GT0

RQ/GT1LOCK

S2S1

S0

QS1

QS0

TEST

8088 pin diagram

GND

A14A13A12

A10A11

A8A9

AD6AD7

AD4

AD5

AD3AD2AD1AD0

NM1INTRCLK

GND

ALE

HLDA

HOLD

A19/S6

A17/S4A18/S5

A16/S3A15

Vcc

READYRESET

SS0MN/MX

RD

WR

IO/MDT/R

DEN

INTATEST

27

7

14

11

1

23

45

6

8

910

12

13

1615

17

1918

20

34

30

40

3938

37

36

35

33

3231

29

28

2526

24

2223

21

8088CPU

MINMODE

{ }MAX

MODE

(HIGH)

(RQ/GT0)

(RQ/GT1)(LOCK)

(S2)(S1)

(S0)

(QS0)

(QS1)

Some pins have different functionsfor two different operation modes.


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ELE 3230 - Part 3 10

In t roduc t ion t o In t e l 8086/8088

Microprocessors8088 and 8086 are almost identical except that 8088 has only 8

external data lines whereas the 8086 has 16 external data lines.

Both have

16-bit wide data bus internally in microprocessor

20 address pins, including 16 address/data (AD0-AD15) + 4address/status (A16/S3-A19/S7) for 8086, allowing a maximummemory address range of 1MByte

multiplexed address/data pins (8088 only multiplexes 8 pins, AD0-

AD7) 2 modes of operation (the maximum and minimum modes)

Same instruction set


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ELE 3230 - Part 3 11

Int e rnal Arc h it ec t u re of t he 8088

Both 8088/8086 employ parallel processing.

Contain two processing units: Execution unit (EU) and Businterface unit(BIU); operate at the same time.

The BIU sends out addresses, fetches instructions frommemory, reads data from ports and memory, and writes datato ports and memory, i.e. the BIU handles all transfers of dataand addresses on the buses for the execution unit.

The EU tells BIU where to fetch instruction or data from,

decodes instructions, and executes instructions.


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ELE 3230 - Part 3 12

8086 In t erna l B loc k Diagram


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ELE 3230 - Part 3 13

Bus Int e rfac e Uni t (BIU)

Perform bus operation such as instruction fetching, reading/writing ofdata operand for memory, inputting/outputting data for I/O peripherals.

Perform other functions such as instruction queuing and dataacquisitions.

8-bit (16-bit) bi-directional data busfor 8088 (8086).

20-bit address bus can address any one of the 220 (1,048,576) byte-

memory .

Contain segment register, instruction pointer, address generation adder,bus control logic, and an instruction queue.

Use instruction queue to implement a pipelined architecture (prefetchup to 4 (6) bytes of instruction code for 8088 (8086) and then store andaccess the codes in FIFO order).

See Part-9 for the detail discussion on instruction set and segment

registers.


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ELE 3230 - Part 3 14

Ex ec ut ion Un it (EU)

Responsible for decoding and executing instruction.

Contains: arithmetic logicunit (ALU), status and control flags, general

purpose registers, and temporary-operand register.

EU accesses the instruction from output end of the instruction queueand data from general-purpose register.

It reads one instruction at a time, decodes them, generates operandaddress if necessary, passes them to BIU and requests to perform theread/write cycle to memory or I/O, and performs the operation specifiedby the instruction on operand.

During execution, EU may test the status and control flags and updatethese flags based on the results of execution.


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ELE 3230 - Part 3 15

Flag Regist er

The flag indicates the condition of the microprocessor as well ascontrols its operations.

A flag register is a flip-flop which indicates some conditionsproduced by the execution of an instruction or controls certainoperations of the EU. A 16-bit flag register in the EU contains nineactive flags. (Each flag occupies one bit in the flag register.)

Two types of flags:conditional flags: Six flags are conditional flags. They are set or reset

by the EU on the basis of the results of some arithmetic operation.

control flags: The three remaining flags in the flags register are used

to control certain operations of processor. They are called the controlflags.


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ELE 3230 - Part 3 16

Flag Regist ers

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U=Undefined Carry Flag (CF)- set by carry out of MSB.Parity Flag (PF)- set if result has even parity.

Auxiliary carry Flag (AF)- for BCDZero Flag (ZF)- set if results = 0

Sign Flag (SF) = MSB of result

Overflow Flag (OF)- overflow flag

IF- interrupt enable flag

DF- string direction flag

TF- single step trap flag

U U U U OF DF CFPFAFZFSFTFIF UUU

MSB: Most Significant Bit

See Examples in Part-6

Conditional Flags

Control Flags


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ELE 3230 - Part 3 17

Condi t ional Flags

carry flag (CF)- indicates a carry after addition or a borrow aftersubtraction, also indicates error conditions.

parity flag (PF)- is a logic 0 for odd parity and a logic 1 for even parity.

auxiliary carry flag (AF)- important for BCD addition and subtraction;holds a carry (borrow) after addition (subtraction) between bit-3 and bit-4.Only used for DAA and DAS instructions to adjust the value of AL after aBCD addition (subtraction).

zero flag (ZF)- indicates that the result of an arithmetic or logic operation

is zero. sign flag (SF)- indicates arithmetic sign of the result after an arithmetic

operation.

overflow flag (OF)- a condition that occurs when signed numbers areadded or subtracted. An overflow indicates that the result has exceeded

the capacity of the machine.

(See Part-6 for more details)


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ELE 3230 - Part 3 18

Cont ro l Flags

The control flags are deliberately set or reset with specificinstructions YOU put in your program. The three control flags are:

trap flag (TF) - used for single stepping through a program (fordebugging);

interrupt flag (IF) - used to allow or prohibit the interruption ofa program;

direction flag (DF) - used with string instructions.

No specific instruction to set TF. See example 12-1 in Breys formore details.


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ELE 3230 - Part 3 19

General -Purpose Reg ist ers

EU has eight 8-bit general-purpose registers, labeled AH, AL, BH, BL,CH, CL, DH, and DL. These registers can be used individually fortemporary storage of 8-bit data.

Register pairs AH-AL, BH-BL, CH-CL, and DH-DL can be used togetherto form register AX, BX, CX, and DX and can be used to store 16-bit datawords.

The AL register is also called the accumulator. It has some features that

the other general-purpose registers do not have.

The advantage of using internal registers is :

It can be accessed more quickly than from external memory. No memoryreference or memory cycle is needed to get the data.

(See Part-6 for more details)

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03 System Architecture