04 UMG8900 Hardware System

www.huawei.com

Copyright © 2006 Huawei Technologies Co., Ltd. All rights reserved.

UMG8900 Hardware

System(SSM256)

Copyright © 2006 Huawei Technologies Co., Ltd. All rights reserved. Page1

Objectives

Upon completion this course, you will be able to:

Perform UMG8900 shelf、 frame and boards classifications,

functions and interfaces

Know UMG8900 logical subsystem

Perform the concatenation


References

UMG8900 System Description

UMG8900 Hardware Description Manual

UMG8900 Architecture and Principle


Contents

1. Overview

2. Board Function

3. Signaling Flow

4. Concatenation and Cables


R4 Networking


Shelf and Frame

(1)

(2)

(3)

(5)

(4)

(1) Frame lintel (2) 9U board (3) Integrated fan

(4) 8U board (5) Filter box


Shelf and Frame

(1) Frame lintel (2) Mounting angle (3) Embedded fan box

(1) Mounting angle (2) Power-in terminal of frame

(3) Interface for monitoring cable (4) Standby power-in terminal of fan box

(5) Interface for alarm cable (6) Power-out terminal of fan box

(7) Power-in terminal of fan box (8) DIP switch for setting frame ID


Frame Classification

The main control frame: Manages and controls the whole

UMG8900 equipment and provides clock signals for other frames.

The central switching frame: Implements frame subtending

function.

The service frame : Implements service processing and interfacing

functions.

The extended control frame: It is configured when the networking

with large capacity is required. It is responsible for protocol

processing and connection management, and implements

controlling and managing the service frames.


Frame Configuration

Service frame #2

Main control frame #1

Central switch frame #0

Air defence frame

Power distribution frame

Air defence frame

Dummy panel

Fiber coiler

Service frame #5

Service frame #4

Service frame #3

Air defence frame


Air defence frame

Dummy panel

Fiber coiler

Extended control frame #8

Service frame #7

Service frame #6

Air defence frame


Air defence frame

Dummy panel

Fiber coiler


DIP Switch

OFF

1 2 3 4 5 6 7 8

ON

DIP switch setting Binary

number Frame ID

SW4 SW3 SW2 SW1

ON ON ON ON 0000 0

ON ON ON OFF 0001 1

ON ON OFF ON 0010 2

ON ON OFF OFF 0011 3

ON OFF ON ON 0100 4

ON OFF ON OFF 0101 5

ON OFF OFF ON 0110 6

ON OFF OFF OFF 0111 7

OFF ON ON ON 1000 8


Slot Distribution

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

O

M

U

O

R

M

P

U

Se

rvic

e b

oa

rd

Front board s slot distribution

O

M

U

R

M

P

U

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

O

Se

rvic

e bo

ard

Se

rvic

e bo

ard


Slot Distribution

N

E

T

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

N

E

T

Se

rvic

e b

oa

rd

Back board ’ s slot distribution

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

Se

rvic

e b

oa

rd

T

N

U

T

N

U


Questions

Please describe the classification, function and location in

the shelf of the UMG8900 frames.

How to set the DIP switch?

Please describe the slot distribution of UMG8900.


Summary

Frame classification, function and distribution in shelf

Slot distribution in frame

Dip switch setting.


Contents

1. Overview

2. Board Function

3. Signaling Flow



Contents

2 Board Function

2.1 Hardware System Introduction

2. 2 Operation and Maintenance Subsystem

2.3 Gateway Control Subsystem

2.4 Packet Service Processing Subsystem

2.5 TDM Service Processing Subsystem

2.6 Service Resource Subsystem

2.7 Signaling Forwarding Subsystem

2.8 Clock Subsystem

2.9 Cascading Subsystem


Hardware System

PP

U CMU

OMU/MPU

MBus Packet

Switch

RPU E8T/ E1G

S2L/ S2E

E32/ T32

TNU BLU/FLU

CLK

IP

Packet Service Processing Subsystem

Gateway Control

Subsystem

Service Resource

Subsystem

TDM Service Processing Subsystem

Cascading Subsystem

Clock Subsystem TDM

O&M Subsystem

E8T/E1G VPU

SPF

Signaling Forwarding

Subsystem

MGC(MSOFTX3000) LMT/iManager

ASU A4L/ EAC ASU ATM A4L/EAC

HRB

NET

S2L/S2E E32/T32


Contents

2 Board Function








2.8 Clock Subsystem



OMU(MOMU)

As the management and control center of the whole

equipment, the master and slave MOMUs are inserted in

front slots 7 and 8 in the main control frame.

Providing packet switching function at the control plane to

communicate with all the boards with FE control interfaces

and to exchange information with other frames and manage

interfaces in the multi-frame cascading case.

Embedding a BAM, which provides MML and Telnet

interfaces to configure and maintain boards, and saves log

files and alarm information.

CO

M0

OFFLINE

HUAWEI

FE

0

RESET

MOMU

ACT

RUNALM


OMU(MOMU)

Monitoring and managing the states of all boards in the equipment. When

multiple frames are cascaded, the MOMU monitors and manages MMPUs in

other frames through cascaded control planes.

Implementing state monitoring and power-on/off management on the

equipment through special MBus modules; avoiding attack from instant currents

by controlling board power-on sequence.

board

board

board

Other frame

board

board

board

board

Main control frame

Board

board

board

board

Other frame

MPU

MPU (Slave)

MPU

MPU (Master)

OMU

OMU

board

(Slave)

(Master)

(Slave)

(Master)

board


MPU(MMPU)

Implementing control information interaction between the

boards and inter-frame control information interaction as

well as interface management in the case of multiple

frames subtended.

Monitoring and managing the status of all boards in the

frame.

Implementing status querying, monitoring and power-on or

power-off management to the equipment through special

maintenance module, and controlling board power-on

sequence to avoid impact from instant current. HUAWEI

RESET

CO

M0

FE

0

OFFLINE

MMPU

ACT

RUNALM


Contents

2 Board Function








2.8 Clock Subsystem



MGW Control Subsystem

CMU

PPU

OMU/MPU

FE-Switch

Gateway Control

Subsystem

H.248(FE)

MGC(MSOFTX3000)


PPU(MPPB)

Sending manipulation results to the MGC in

the form of H.248 messages.

Implementing H.248 transcoding, and

resolving transport-layer and network-layer

protocols.

Stack for Mc interface Stack for SG function

H.248

SCTP/UDP

IP

SCCP

M3UA

IP

RANAP

SCTP OFFLINE

FE

0

MPPB

CO

M0

RESET

HUAWEI

RUNALM


CMU(MCMF/MCMB)

HRB VPU

ATM IP TDM


CMU(MCMF/MCMB)

Providing internal interface to connect with the

PPU to implement interaction of H.248 messages.

Providing interfaces to connect with the HRB,

ASU, TNU to control the boards to convert media

streams.

Providing interface to connect with the MPU/OMU

to implement data configuration and output

alarms, debugging information and logs.

It includes two types: CMF (Front board) and

CMB (back board)

CO

M0

OFFLINE

HUAWEI

MCMF

RESET

ACT

RUNALM

OFFLINE

CO

M0

MCMB

HUAWEI

RESET

ACT

RUNALM


Contents

2 Board Function








2.8 Clock Subsystem



Packet Service Processing

Subsystem

ASU TAC

A4L/

EAC/

TAC

HRU HRB

E8T/

G1O/

P1H/P4L

E8T/

G1O/

P1H/P4L

OMU/MPU

TCU TCU

VPU

ASU

Packet service processing

subsystem

NET

CLK/GE/FE

IP ATM


ASU(MASU)

Processing ATM services.

Providing the standard AAL2/ AAL5

Segmentation and Reassembly (SAR)

function.

Supporting direct forwarding over PVC, OAM

cell extraction and luUP interface processing

functions.

Monitoring and managing the states of the

board and the corresponding back boards.

Supporting 1+1 backup.

CO

M0

OFFLINE

HUAWEI

MASUb

ACT

RUNALM


Back Board Corresponding to MASU

A

S

U

(m)

A

4

L

A

S

U

(s)

A

4

L

Providing four 155 M single-

mode/multi-mode ATM optical

interfaces.

Providing the 1+1 backup function

by collaborating with the service

processing board MASU.

OFFLINE

HUAWEI

8K

_O

UT

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

MA4L

ACT

RUNALM


HRB(MHRU)

Processing IP routes, and converging and distributing IP

services.

Monitoring and managing the states of the board and the

corresponding back boards.

Supporting the Internet Protocols over ATM (IPoA) function.

After the MHRU finishes the adaptation of the IP data packets

to the ATM, the ATM interface board forwards them on.


HRB(MRPU) Processing Internet Protocol (IP) routes, and converging and

distributing IP services.

Monitoring and managing the states of the board and the

corresponding back boards.

Resolving the RTP/Real-time Transport Control Protocol (RTCP)

protocols.

Jitter-buffering RTP services.

Nb UP

UDP

IP

RTP/ RTCP


Back Board Corresponding to MRPU

H

R

B

(m)

P

4

L

H

R

B

(s)

P

4

L

H

R

B

(m)

E

1

G

H

R

B

(s)

E

1

G

H

R

B

(m)

E

8

T

H

R

B

(s)

E

8

T

H

R

B

(m)

G

1

O

H

R

B

(s)

G

1

O

MRPU corresponding back boards include MG1O, MP4L and ME8T.

Example: MG1O function

Providing one GE interface in conformity with the IEEE8002.3z standard.

Providing the 1+1 backup function by collaborating with the service

processing board MRPU.


NET(MNET)

Providing packet service switching channels in its own frame to

exchange service data between all packet service boards in the frame.

Cascading two frames instead of cascading boards. The embedded

cascading module in the MNET enables interworking of 2 × GE

service data planes and interworking of 2 × FE service control planes.

Providing service control and maintenance interfaces for the

corresponding front boards such as the MOMU and MMPU to address

back cabling requirements.

Receiving clock signals from the MCLK, and sending them to TDM

service processing boards after phase lock, signal driving and

distributing.

OFFLINE

HUAWEI

OM

CM

IRF

E0

FE

1

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

CO

M0

CLK

0_IN

CLK

1_IN

MNET

ACT

RUNALM


NET(MNET)

The internal clocks synthesized and distributed by the MNET are as

follows:

32.768 MHz clock: the TDM HW synchronous clock signals for the TDM

bearer processing

38.88 MHz clock: the TDM SDH synchronous clock, including the

synchronous clock required by the ATM and POS services in the SDH

transmission mode

77.76MHz clock: the clock signal for the SDH 155 MHz line interface

2 kHz clock: the TDM SDH frame clock

The TNU, E32, T32, S2L, S1L, TCU, BLU, SPF and ECU use 32.768

MHz, 38.88 MHz and 2 kHz clock signals. Besides the three clock

signals, S1L and S2L use 77.76 MHz signal. The A4L and P1H only use

the 38.88 MHz clock signal.


Contents

2 Board Function








2.8 Clock Subsystem



TDM Service Processing

Subsystem

E32/T32/

S2L/S2E

OMU/MPU

VPU VPU

VPU

E32/T32/ S2L/S2E

TDM service processing subsystem

TNU

4*TDM

Packet processing subsystem

TDM


TNU(MTNB)

Establishing and releasing TDM timeslots in cooperation

with TDM service interface boards, and providing 8 K or 1

K switching capacity for each interface board.

Connecting with the MTNB of another frame directly or

through the UG02MBLU by multi-mode optical fibers, and

providing 32 K timeslot cascading capacity.

Managing and maintaining the boards through the

specified MBus module. Reporting the status and version

of the boards to the main control board of the local frame.

Communicating with the main control board of the local

frame through the FE interface. HUAWEI

OFFLINE

MTNB

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

CO

M0

ACT

RUNALM


S2L(MS2L)

Extracting clock signals and forming frames at

the two 155 M optical interfaces.

Processing overheads of regenerator section

and multiplex section of optical signals and

checking communication over optical channels.

Implementing SDH mapping, de-mapping and

processing overheads of high-order path and

low-order path.

Forming 2 × 63 E1

OFFLINE

HUAWEI

ACT

RUNALM

CO

M0

8K

_O

UT

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

MS2L


E32(ME32)

Providing 32 E1 interfaces.

Providing 32 E1 frames.

Providing the function of drawing the line signaling of

the R2 signaling or inserting the signaling.

Providing 8 kHz line clock reference source for the

master and slave MCLKs by distributing cables at

the board panel.

Receiving SSM information from the E1 interface

and sending it to the clock system.

Providing service link loopback at all levels and

service channel detection within the board. HUAWEI

ME32

OFFLINE

8K

_O

UT

E1

/T1

_0

-15

E1

/T1

_1

6-3

1

RUNALM


Contents

2 Board Function








2.8 Clock Subsystem



VPU(MVPB)

Supporting functions such as announcement playing, digit

collecting, audio mixing and Multiple Frequency Control (MFC).

Implementing IP packet adaptation of voice services based on

UDP, Real-time Transport Protocol (RTP), and IP. Supporting

varied voice codec types including G.711A, G.711μ, G.723, G.726,

G.729, AMR, AMR 2 and FR/HR/EFR.

Accepting resource control and management from the CMU..


VPU(MTCB)

Supporting announcement playing, digit collecting, audio mixing and MFC.

Implementing IP packet adaptation of voice services based on UDP, RTP

and IP. Supporting varied voice codec types including G.711A, G.711μ,

G.723, G.726, G.729, AMR, AMR 2 and FR/HR/EFR.

Processing IuUP and NbUP at the same time and being fully in line with

the 3GPP TS 25.415 TS 29.415 protocol.

Providing the EC function, supporting 32 ms, 64 ms and 128 ms tail delay,

being in line with the G.168-2000 standard and supporting G.164/165

tone detection.

Receiving the resource control and management of the CMU.


Contents

2 Board Function








2.8 Clock Subsystem



SPF(MSPF) Implementing signaling gateway functions. The pinch boards that attached on the

MSPF, receives signaling from TDM switching boards and then deals with it at

TDM level, and then the MSPF adapts TDM signaling to IP packets.

Implementing the core function of a signaling gateway by M3UA//M2UA/V5UA/IUA

adaptation on signaling, and forwarding adapted messages to the MGC.

SEP UMG8900 MSOFTX3000

S7UP

MTP3

S7UP

MTP3

MTP2

MTP1 MTP1

MTP2 M2UA

SCTP

IP

M2UA

SCTP

IP

MAC MAC

SS7 IP

M2UA-NIF

TDM IP


Contents

2 Board Function








2.8 Clock Subsystem



Clock Subsystem


CLK(MCLK)

CLK is the system clock board, responsible for receiving line

clock signals extracted by interface boards and external

synchronous clock signals provided by BITS.

Each MGW frame is configured with two NET boards. In the

main control frame, the clock boards provide 16-kHz clock

signals to the NET boards of the frame through the

backplane. In other MGW frames, the clock boards provide

16-kHz clock signals to the NET boards through the

distributed cables.

The CLK also outputs external synchronous clock signals.

MCLK

HUAWEI

OFFLINE

CLK

_O

UT

0C

LK

_O

UT

1C

LK

_O

UT

22M

_IN

2M

_O

UT

AN

T8K

_IN

18K

_IN

2

ACT

RUNALM


Contents

2 Board Function








2.8 Clock Subsystem



Cascading Subsystem

2# 3# 4# 5# 6# 7#

0#

1#

8#

2*GE 1*FE

T

N

U

N

E

T

N

E

T

T

N

U

B

L

U

B

L

U

B

L

U

B

L

U

T

N

U

B

L

U

N

E

T

N

E

T

B

L

U

T

N

U

B

L

U

B

L

U

B

L

U

B

L

U

B

L

U

B

L

U

N

E

T

N

E

T

4*8K TDM


BLU(MBLU)

Providing 4x8 K TDM narrowband data channels to directly

connect frames through multi-mode optical fibers that are no more

than 50 m spaced.

Providing 2x1.25 G broadband packet data channels to directly

connect frames through multi-mode optical fibers that are no more

than 50 m spaced.

Providing 1x100 M IP control data channels to directly connect

frames through category-5 twisted pair or super category-5 twisted

pair that are no more than 50 m spaced.

Providing board management and maintenance by the dedicated

MBus module of the board, communicating with and reporting

board status and version to the main control board through FE

channels.

OFFLINE

HUAWEI

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

ACT

LINK

TX0

RX0

MBLUb

ACT

RUNALM

CO

M0

FE

0

ACT

LINK

TX0

RX0

GE

TDM


FLU(MFLU)

Providing 1x8 K TDM data cascading channel for the MBLU.

Providing 1x1.25 G IP data cascading channel for the MBLU.

Providing 2x8 K TDM data cascading channels and 2x1.25 G GE

data cascading channels for the MBLU by two MFLU boards in

load-sharing mode.

Interacting with the main control board through a dedicated

maintenance module to monitor board temperature, voltage and

control power-on/off.


Questions

Please describe the UMG8900’s boards classifications and

each class’s function


Summary

UMG8900’s logical subsystem

UMG8900’s boards classification and each function


Contents

1. Overview

2. Board Function

3. Signaling Flow



Contents

3 Signaling Flow

3.1 Service Signaling Flow

3.2 Clock Signaling Flow

3.3 Loading Signaling Flow

3.4 Alarm Signaling Flow


Service Signaling Flow

Gateway Signal Control Flow (IP bearer)

C

M

U

T

C

U

S

P

F

C

M

U

R

P

U

FE

E

3

2

E

8

T

T

N

U

FE

Back

Front O

M

U

N

E

T

P

P

U

MGC

A

S

U

A

4

L



Transfer flow for the UMTS access network signaling (PPU

adaptation) MGC (MSOFTX3000)

P

P

U

S

P

F

A

S

U

FE

A

4

L

FE

Back

Front O

M

U

N

E

T

T

N

U

RNC

MSOFTX3000 RNC



Transfer flow for the UMTS access network signaling (SPF

adaptation) MGC(MSOFTX3000)

P

P

U

S

P

F

A

S

U

FE

A

4

L

FE

Back

Front O

M

U

N

E

T

T

N

U

RNC

MSOFTX3000 RNC



SS7 transfer flow

E

3

2

C

M

U

V

P

U

S

P

F

T

N

U

BSC/LE/V5AN/MSC

FE

TDM

FE

TDM

Back

FrontO

M

U

N

E

T

MGC

MSOFTX3000 BSC


T N U

V P U

H R B

E 3 2

E 8 T

GE TDM

Front

N E T

Back

TDM IP


Bearer Data Flow (TDM↔IP)


T

N

U

V

P

U

A

S

U

E

3

2

A

4

L

GE TDM

Front

N

E

T Back

TDM ATM


Bearer Data Flow (TDM↔ATM)



Bearer Data Flow (ATM↔IP)

A

S

U

N

E

T

T

N

U

H

R

B

A

4

L

E

8

T

GETDM

Front

Back

ATM IP

O

M

U

ATM IP



Bearer Data Flow (IP↔IP)

H

R

B

N

E

T

T

N

U

H

R

B

E

8

T

E

8

T

GETDM

Front

Back

IP (Domain 0) IP (Domain 1)

O

M

U

IP (Domain 0) IP (Domain 1)


Service Resource Signal Flows

Announcement Playing Signal Flow

C

M

U

E

3

2

V

P

U

S

P

F

H

R

B

T

N

U

E

8

T

FEGETDM

Front

A

S

U

A

4

L

Back


Contents

3 Signaling Flow






Clock Extraction


Clock Distribution


Contents

3 Signaling Flow






FTP Server

LMT

C

L

K

T

N

U

N

E

T

N

E

T

T

N

U

A

4

L

P

4

L

S

2

L

E

3

2

V

P

U

A

S

U

O

M

U

O

M

U

H

R

U

E

8

T

G

1

O

FE crossover network cable RS232 cable

FE crossover network cable

FE control bus

master/ slave

FTP service hyper terminal


OMU Embedded BAM

O

M

U

O

M

U

N

E

T

N

E

T

main control

frame

M

P

U

M

P

U

N

E

T

N

E

T

central exchange

frame

T

N

U

B

L

U

F

L

U

T

N

U

T

N

U

1*FE

master/slave FE bus

master/slave FE bus

se

rvic

e

bo

ard

T

N

U


OMU Embedded BAM

N E T

N E T

M P U

M P U

O M U

O M U

N E T

N E T

main control frame

M P U

M P U

N E T

N E T

central exchange frame

F L U

B L U

F L U

B L U

N E T

N E T

M P U

M P U

service frame

T N U

T N U

1*FE+2*GE+4*TDM

service

board

master/slave

FE bus

master/slave FE bus

master/ slave

FE bus

N E T

N E T

M P U

M P U

master/slave FE bus

extended control frame service frame

master/slave

FE bus

T N U

T N U

T N U

T N U

T N U

T N U

T N U

T N U


Contents

3 Signaling Flow






O

M

U

O

M

U

N

E

T

N

E

T

T

N

U

T

N

U

C

L

K

A

4

L

M

A

S

U

P

4

L

M

S

2

L

M

E

3

2

V

P

U

H

R

U

V

P

U

FE bus

Mbus se

rvic

e

bo

ard

LMT

crossover network cable

Note: when LMT is connected

with the host through LanSwitch, the straight-thru cable is used

se

rvic

e

bo

ard

master/ slave

master/ slave

Alarm Path


Alarm Path

O M U

O M U

N E T

N E T

main control frame

M P U

M P U

N E T

N E T

central exchange frame

T N U

T N U

B L U

F L U

T N U

T N U

1*FE+2*GE+4*TDM

master/ slave

FE bus

master/ slave

Mbus bus

s e r v i c

e

b o a r d

R P U


Alarm Path O M U

O M U

N E T

N E T

main control frame

M P U

M P U

N E T

N E T

central exchange

frame

T N U

T N U

F L U

B L U

F L U

B L U

N E T

N E T

M P U

M P U

T N U

T N U

N E T

N E T

M P U

M P U

T N U

T N U

service frame

T N U

T N U

1*FE+2*GE+4*TDM

se

vic

e

bo

ard

master/slave

FE bus

maste r/slave FE bus

N E T

N E T

M P U

M P U

T N U

T N U

extended control frame service frame

master/ slave Mbus

master/ slave Mbus

master/ slave Mbus


Questions

Please describe all kinds of signaling flow.


Summary

Service signaling flow

Clock signaling flow

Loading signaling flow

Alarm signaling flow


Contents

1. Overview

2. Board Function

3. Signaling Flow



Contents

4 Concatenation and Cables

4.1 Cascading Cable Distribution

4.2 Clock Cable Distribution

4.3 Monitoring Cable Distribution


Two Frames Cascading

2#

1#

2*GE 1*FE

T

N

U

N

E

T

N

E

T

T

N

U

T

N

U

N

E

T

N

E

T

T

N

U

4*8K TDM


More than Three Frames

Cascading

2# 3# 4# 5# 6# 7#

0#

1#

8#

2*GE 1*FE

T

N

U

N

E

T

N

E

T

T

N

U

B

L

U

B

L

U

B

L

U

B

L

U

T

N

U

B

L

U

N

E

T

N

E

T

B

L

U

T

N

U

B

L

U

B

L

U

B

L

U

B

L

U

B

L

U

B

L

U

N

E

T

N

E

T

4*8K TDM


Contents






Clock Extraction


Clock Cable Distribution

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

N

E

T

M

C

L

K

M

C

L

K

Master clock cable

Slave clock cable


Contents






Monitoring Cable Distribution

DB15

DB15

DB15

DB9

DB9

DB9


Service frame

Central switch frame

Main control frame

Air deflector

Fan box

Air deflector

Fan box

Fan box

DB15

DB15

DB15

DB15

DB9

DB9

DB9


Air deflector

Fan box

Air deflector

Fan box

Fan box

DB15

Service frame

Service frame

Service frame

Main control cabinet Service cabinet


Questions

If there are 4 frames, how to cascade them?


Summary

Cascading cable distribution

Clock cable distribution

Monitoring cable distribution


Summary

Board functions

Signaling flow

Concatenation and cables

Thank you www.huawei.com

Documents

04 UMG8900 Hardware System