1 2004 Morgan Kaufmann Publishers Chapter Three : Arithmetic for Computers

12004 Morgan Kaufmann Publishers

Chapter Three :Arithmetic for Computers


Outline

• 3.1 Introduction• 3.2 Signed and Unsigned Numbers• 3.3 Addition and Subtraction• 3.4 Multiplication• 3.5 Division• 3.6 Floating Point• 3.7 Real Stuff: Floating Point in the IA-32• 3.8 Fallacies and Pitfalls• 3.9 Concluding Remarks


3.1 Introduction


• Bits are just bits (no inherent meaning)— conventions define relationship between bits and

numbers

• Binary numbers (base 2)0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...decimal: 0...2n-1

• Of course it gets more complicated:numbers are finite (overflow)fractions and real numbersnegative numberse.g., no MIPS subi instruction; addi can add a negative

number

• How do we represent negative numbers?i.e., which bit patterns will represent which numbers?

Numbers


• Sign Magnitude: One's Complement Two's Complement

000 = +0 000 = +0 000 = +0001 = +1 001 = +1 001 = +1010 = +2 010 = +2 010 = +2011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4101 = -1 101 = -2 101 = -3110 = -2 110 = -1 110 = -2111 = -3 111 = -0 111 = -1

• Issues: balance, number of zeros, ease of operations

• Which one is best? Why?

Possible Representations


3.2 Signed and Unsigned Numbers


Keywords

• Least significant bit The rightmost bit in a MIPS word.

• Most significant bit The leftmost bit in a MIPS word.

• Biased notation A notation that represents the most negative value by 00 … and the most positive value by 11 … with 0 typically having the value 10 … , thereby biasing the number bias has a nonnegative representation.

two000two111

two00


Biased notation

11…111two ; the most positive value

.

.

.

10…000two ; 0, biasing the number

.

.

.

00…000two ; the most negative value


• 32 bit signed numbers:

0000 0000 0000 0000 0000 0000 0000 0000two = 0ten

0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten

0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten

...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten

0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten

1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten

1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten

1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten

...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten

1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten

1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

maxint

minint

MIPS


• Negating a two's complement number: invert all bits and add 1

– remember: “negate” and “invert” are quite different!

• Converting n bit numbers into numbers with more than n bits:

– MIPS 16 bit immediate gets converted to 32 bits for arithmetic

– copy the most significant bit (the sign bit) into the other bits

0010 -> 0000 0010

1010 -> 1111 1010

– "sign extension" (lbu vs. lb)

Two's Complement Operations


Signed versus Unsigned Comparison

1111 1111 1111 1111 1111 1111 1111 1111two two # $s0# $s0

0000 0000 0000 0000 0000 0000 0000 00000000 0000 0000 0000 0000 0000 0000 0000two two #$t1#$t1

slt $t0, $s0, $s1 #signed comparison, -1slt $t0, $s0, $s1 #signed comparison, -1tenten< 1< 1tenten, $t0=1, $t0=1

sltu $t0, $s0, $s1 #unsigned comparison, 4,294,967,295sltu $t0, $s0, $s1 #unsigned comparison, 4,294,967,295tenten< 1t< 1tenen, $t0=0, $t0=0


Negation Shortcut

Negate 2ten and then check the result by negating -2ten

1111 1111 1111 1111 1111 1111 1111 1101two

+ 1two

----------------------------------------------------------------------------

1111 1111 1111 1111 1111 1111 1111 1110two=-2ten

0000 0000 0000 0000 0000 0000 0000 0001two

+ 1two

----------------------------------------------------------------------------

0000 0000 0000 0000 0000 0000 0000 0010two=2ten


Sign Extension Shortcut

Convert 16-bit binary versions of 2ten and -2ten to 32-bit binary numbers.

0000 0000 0000 0010two= 2 ten

1111 1111 1111 1110two= -2 ten

0000 0000 0000 0000 0000 0000 0000 0010two= 2 ten

1111 1111 1111 1111 1111 1111 1111 1110two= -2 ten


FIGURE 3.1 MIPS architecture revealed thus far.

MIPS operandsName Example Comments

32 registers$s0-$s7, $t 0- $t 9,

$zero, $a0-a3, $v0-$v1, $gp, $fp, $sp, $ra, $at

Fast locations for data. In MIPS, data must be in registers to perform arithmetic.

MIPS register $zero always equals 0. Register $at is reserved for the assembler to handle large constants.

memory words

Memory[0],Memory[4], …, Memory[4294967292]

Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures, arrays, and spilled registers, such as those saved on procedure calls.

302


MIPS assembly language

Category Instruction Example Meaning Comments

Arithmetic

add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; Overflow detected

subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; Overflow detected

add immediate addi $s1, $s2, 100 $s1 = $s2+ 100 Used to add constants

Data transfer

load word lw $s1, 100($s2) $s1 = Memory [$s2 + 100] Word from memory to register

store word sw $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Word from register to memory

load half unsigned lh $s1, 100($s2) $s1 = Memory [$s2 + 100] Halfword memory to register

store half sh $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Halfword register to memory

load byte unsigned lb $s1, 100($s2) $s1 = Memory [$s2 + 100] Byte from memory to register

store byte sb $s1, 100 ($s2) Memory [$s2 + 100] = $s1 Byte from register to memory

load upper immed. lui $s1, 100 $s1 = 100 * 2^16 Loads constant in upper 16 bits

Logical

and add $s1, $s2, $s3 $s1 = $s2 & $s3 Three reg. operands; bit-by-bit AND

or or $s1, $s2, $s3 $s1 = $s2 | $s3 Three reg. operands; bit-by-bit OR

nor nor $s1, $s2, $s3 $s1 = ~($s2 | $s3) Three reg. operands; bit-by-bit NOR

and immediate andi $s1, $s2, 100 $s1 = $s2 & 100 Bit-by-bit AND reg with constant

or immediate ori $s1, $s2, 100 $s1 = $s2 | 100 Bit-by-bit OR reg with constant

shift left logical sll $s1, $s2, 10 $s1 = $s2 << 10 Shift left by constant

shift right logical srl $$s1, $s2, 10 $s1 = $s2 >> 10 Shift right by constant


Continue..

Conditional branch

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to

PC+4+100

Equal test; PC-relative branch

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to L

PC+4+100

Not equal test; PC-relative

set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1;

else $s1 = 0

Compare less than; two’s complement

set on less than immediate

slt $s1, $s2, 100 if ($s2 < 100) $s1 = 1;

else $s1 = 0

Compare < constant;

Two’s complement

set less than unsigned

sltu $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1;

else $s1 = 0

Compare less than; unsigned numbers

set less than immediate unsigned

sltuiu $s1, $s2, 100

if ($s2 < 100) $s1 = 1;

else $s1 = 0

Compare< constant;

unsigned numbers

Unconditional jump

jump j 2500 go to 10000 Jump to target address

jump register jr $ra go to $ra For procedure return

jump and link jal 2500 $ra = PC + 4; go to 10000

For procedure call


3.3 Addition and Subtraction


Keywords

• Exception Also called interrupt. An unscheduled event that disrupts program execution; used to detect overflow.

• Interrupt An exception that comes from outside of the processor. (Some architectures use the term interrupt for all exceptions.)


• Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101

• Two's complement operations easy

– subtraction using addition of negative numbers 0111+ 1010

• Overflow (result too large for finite computer word):

– e.g., adding two n-bit numbers does not yield an n-bit number 0111+ 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”

Addition & Subtraction


FIGURE 3.2 Binary addition, showing carries from right to left.


• No overflow when adding a positive and a negative number

• No overflow when signs are the same for subtraction

• Overflow occurs when the value affects the sign:

– overflow when adding two positives yields a negative

– or, adding two negatives gives a positive

– or, subtract a negative from a positive and get a negative

– or, subtract a positive from a negative and get a positive

• Consider the operations A + B, and A – B

– Can overflow occur if B is 0 ?

– Can overflow occur if A is 0 ?

Detecting Overflow


FIGURE 3.3 Overflow conditions for addition and subtraction.

Operation Operand A Operand BResult indicating

overflow

A + B

A + B

A – B

A – B

0 0

00

0 00

0

0

00

0


• An exception (interrupt) occurs

– Control jumps to predefined address for exception

– Interrupted address is saved for possible resumption

• Details based on software system / language

– example: flight control vs. homework assignment

• Don't always want to detect overflow— new MIPS instructions: addu, addiu, subu

note: addiu still sign-extends!note: sltu, sltiu for unsigned comparisons

Effects of Overflow


addu $t0, $t1, $t2

xor $t3, $t1, $t2

slt $t3, $t3, $zero

bne $t3, $zero, no_overflow

xor 4t3, $t0, $t1

slt $t3, $t3, $zero

bne $t3, $zero, overflow


addu $t0, $t1, $t2

nor $t3, $t1, $zero

sltu $t3, $t3, $t2

bne $t3, $zero, overflow


FIGURE 3.4 MIPS architecture revealed thus far

MIPS assembly languageCategory Instruction Example Meaning Comments

Arithmetic



add immediate addi $s1, $s2, 100 $s1 = $s2+ 100 + constants; overflow detected

add unsigned addu $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; overflow undetected

subtract unsigned subu $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; overflow undetected

add immediate unsigned

addiu $s1, $s2, 100 $s1 = $s2+ 100 + constants; overflow detected

move from coprocessor register

mfc0 $s1, $epc $s1 = $epc Used to copy Exception PC plus other special registers

Data transfer








Logical






Continue..




Conditional branch


PC+4+100



PC+4+100



else $s1 = 0



slt $s1, $s2, 100 if ($s2 < 100) $s1 = 1;

else $s1 = 0

Compare < constant;

Two’s complement


sltu $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1;

else $s1 = 0

Compare less than; unsigned numbers



if ($s2 < 100) $s1 = 1;

else $s1 = 0

Compare< constant;

unsigned numbers

Unconditional jump


jump register jr $ra go to $ra For procedure return


For procedure call


3.4 Multiplication


• More complicated than addition

– accomplished via shifting and addition

• More time and more area

• Let's look at 3 versions based on a gradeschool algorithm

0010 (multiplicand)

__x_1011 (multiplier)

• Negative numbers: convert and multiply

– there are better techniques, we won’t look at them

Multiplication


Multiplying 1000two by 1001two

Multiplicand 1000two

Multiplier 1001two

-------------------------------------------------------------------------

1000 (1xmultiplicand)




--------------------------------------------------------------------------

Product 1001000two


Multiplication: Implementation

Datapath

MultiplicandShift left

64 bits

64-bit ALU

ProductWrite

64 bits

Control test

MultiplierShift right

32 bits


Control

32nd repetition?

1a. Add multiplicand to product and

place the result in Product register

Multiplier0 = 01. Test

Multiplier0

Start

Multiplier0 = 1

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

No: < 32 repetitions

Yes: 32 repetitions

Done


Final Version

Multiplicand

32 bits

32-bit ALU

ProductWrite

64 bits

Controltest

Shift right

•Multiplier starts in right half of product


32nd repetition?

Product0 = 01. Test

Product0

Start

Product0 = 1

3. Shift the Product register right 1 bit


Yes: 32 repetitions

Done

1a. Add multiplicand to the left half

of the product and place the result in

the left half of the Product register


FIGURE 3.8 Multiply example using algorithm in Figure 3.6.


FIGURE 3.9 Fast multiplication hardware.


3.5 Division


Keywords

• Dividend A number being divided.

• Divisor A number that the dividend is divided by.

• Quotient The primary result of a division; a number that when multiplied by the divisor and added to the remainder produces the dividend.

• Remainder The secondary result of a division; a number that when added to the product of the quotient and the divisor produces the dividend.


A example is dividing, 1,001,010two by 1000two

1001 two Quotient----------------------------

Divisor 1000two | 1001010 two

- 1000

-----------------------------

10

101

1010

-1000

-------------------------------

10 Remainder


FIGURE 3.10 First version of the division hardware.


FIGURE 3.11 A division algorithm, using the hardware in Figure 3.10.


FIGURE 3.12 Division example using the algorithm in Figure 3.11.


FIGURE 3.13 An improved version of the division hardware.


Start

1. Shift the Remainder register left 1 bit

2. Subtract the Divisor register from the left half of the Remainder register and place the result in the left half of the Remainder register

Test Remainder

3a. Shift the Remainder register to the left, setting the new rightmost bit to 1

3b. Restore the original value by adding the Divisor register to the left half of the Remainder register and place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new rightmost bit to 0

32nd repetition

Done. Shift left half of Remainder right 1 bit

Remainder ≥ 0


Remainder < 0

Yes: 32 repetitions


Signed Division

The simplest solution is to remember the signs of the divisor and dividend and then negate the quotient if the signs disagree.

Dividend = Quotient * Divisor + Remainder

+7 / +2: Quotient = +3, Remainder = +1.

-7 / +2: Quotient = -3, Remainder = -1.

+7 / -2: Quotient = -3, Remainder = +1.

-7 / -2: Quotient = +3, Remainder = -1.


3.6 Floating Point


Keywords (1)

• Scientific notation A notation that renders numbers with a single digit to the left of the decimal point.

• Normalized A number in floating-point notation that has no leading 0.

• Floating point Computer arithmetic that represents numbers in which the binary point is not fixed.

• Fraction The value, generally between 0 and 1, placed in the fraction field.


• 3.14159265…ten • 2.71828…(℮)• 0.000000001ten or 1.0X10-9• 3,155,760,000ten or 3.15576tenX109• 1.0twoX2-1• 1.xxxxxxxxtwox2yyyy


Keywords (2)

• Exponent In the numerical representation system of floating-point arithmetic, the value that is placed in the exponent field.

• Overflow (floating-point) A situation in which a positive exponent becomes too large to fit in the exponent field.

• Underflow (floating-point) A situation in which a negative exponent becomes too large to fit in the exponent field.

• Double precision A floating-point value represented in two 32-bit word.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

s exponent fraction

1 bit 8 bits 23 bits


Keywords (3)

• Single precision A floating-point value represented in a single 32-bit word.

• Units in the last place (ulp) The number of bits in error in the least significant bits of the significant between the actual number and the number that can be prepresented.

• Sticky bit A bit used in rounding in addition to guard and round that is set whenever there are nonzero bits to the right of the round bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

s exponent fraction


Fraction (continued)

32 bits


Floating Point (a brief look)

• We need a way to represent

– numbers with fractions, e.g., 3.1416

– very small numbers, e.g., .000000001

– very large numbers, e.g., 3.15576 109

• Representation:

– sign, exponent, significand: (–1)sign significand 2exponent

– more bits for significand gives more accuracy

– more bits for exponent increases range

• IEEE 754 floating point standard:

– single precision: 8 bit exponent, 23 bit significand

– double precision: 11 bit exponent, 52 bit significand


FIGURE 3.14 MIPS architecture revealed thus farMIPS assembly language


Arithmetic



add immediate addi $s1, $s2, 100 $s1 = $s2+ 100 + constants; overflow detected

add unsigned addu $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; overflow undetected

subtract unsigned subu $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; overflow undetected

add immediate unsigned

addiu $s1, $s2, 100 $s1 = $s2+ 100 + constants; overflow detected

move from coprocessor register

mfc0 $s1, $epc $s1 = $epc Copy Exception PC + special regs

multiply mult $s2, $s3 Hi, Lo = $s2 x $s3 64-bit signed product in Hi, Lo

multiply unsigned multu $s2, $s3 Hi, Lo = $s2 x $s3 64-bit unsigned product in Hi, Lo

divide div $s2, $s3 Lo = $s2 / $s3

Hi = $s2 mod $s3

Lo = quotient, Hi = remainder

divide unsigned divu $s2, $s3 Lo = $s2 / $s3

Hi = $s2 mod $s3

Unsigned quotient and remainder

move from Hi mfhi $s1 $s1 = Hi Used to get copy of Hi

move from Lo mflo $s1 $s1 = Lo Used to get copy of Lo

Data transfer









Continue..

Logical








Conditional branch


PC+4+100



PC+4+100



else $s1 = 0



slt $s1, $s2, 100 if ($s2 < 100) $s1 = 1;

else $s1 = 0

Compare < constant;

Two’s complement


sltu $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1;

else $s1 = 0

Compare less than; natural numbers



if ($s2 < 100) $s1 = 1;

else $s1 = 0

Compare< constant;

natural numbers

Unconditional jump


jump register jr $ra go to $ra For switch, procedure return


For procedure call


IEEE 754 floating-point standard

• Leading “1” bit of significand is implicit

• Exponent is “biased” to make sorting easier

– all 0s is smallest exponent all 1s is largest

– bias of 127 for single precision and 1023 for double precision

– summary: (–1)sign significand) 2exponent – bias

• Example:

– decimal: -.75 = - ( ½ + ¼ )

– binary: -.11 = -1.1 x 2-1

– floating point: exponent = 126 = 01111110

– IEEE single precision: 10111111010000000000000000000000


FIGURE 3.15 IEEE 754 encoding of floating-point numbers.

Single precision Double precision Object representation

Exponent Fraction Exponent Fraction

0 0 0 0 0

0 nonzero 0 nonzero renormalized number

1 – 254 anything 1 – 2046 anything floating-point number

255 0 2047 0 infinity

255 nonzero 2047 nonzero NaN (Not a Number)


Floating-Point Representation

• Show the IEEE 754 binary representation of the number -0.75 in single and double precision.

• Step1: The number -0.75ten is also -3/4ten = -(1/2+1/4) = -0.11two

Step2: In scientific notation, the value is

and in normalized scientific notation, it is

Step3: (1) The general representation for a single precision number is

Then the result is

0211.0 two

121.1 two

)127(2)1()1( Exeponents Fraction

)127126(1 2)000 0000 0000 0000 0000 1000.1()1( two

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 01111110 10000000000000000000000


• (2) The general representation for a double precision number is

Then the result is

)1023(2)1()1( Exeponents Fraction

)10231022(two

12

1 2)0000 0000 1000.1()1(

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 01111111110 10000000000000000000


00000000000000000000000000000000

32 bits


Converting Binary to Decimal Floating Point

• What decimal number is represented by this single precision float?

The sign bit is 1, the exponent field contains 129, and the fraction field contains , or 0.25. Using the basic equation,

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4/121 2

0.5

425.1

225.11

2)25.01()1(2)1()1(2

)127129(1)(

BiasExponents Fraction


Floating-Point Addition

Step1: Align the decimal point of the number that has the smaller exponent.

The number on the right is the version we desire, since its exponent matches the exponent of the larger number, .

Step2: Next comes the addition of the significands:

Step3: Normalize the sum into a scientific notation.

Step4: Round the number (we assume that the significand can be only four

digits long.)

11 10610.110999.9 tenten

101 1001610.0101610.010610.1 tententen

110999.9 ten

110015.10 is sum The 015.10

016.0

999.9

tenten

ten

ten

21 100015.110015.10 tenten

22 10002.1100015.1 tenten


Decimal Floating-Point Addition – [ 0.5ten + ( - 0.4375ten) ]

• First: Convert two decimal numbers into binary numbers that are in normalized scientific notation.

Then we follow the forward algorithm:

• Step1:

• Step2:

• Step3:

Since , there is no overflow or underflow.

20

4

10

1

2110.120111.00111.0

2/716/74375.0

2000.121.01.0

2/12/15.0

twotwotwo

tententen

twotwotwo

tententen

12 2111.02110.1 twotwo111 2001.0)2111.0(2000.1 twotwotwo

4321 2000.12100.02010.02001.0 twotwotwotwo

1264127

tententen

twotwotwo

0625.016/12/1

0001.00001000.02000.14

4


Floating point addition

•

Small ALU

Exponentdifference

Control

ExponentSign Fraction

Big ALU


0 1 0 1 0 1

Shift right

0 1 0 1

Increment ordecrement

Shift left or right

Rounding hardware



Still normalized?

4. Round the significand to the appropriate

number of bits

YesOverflow or

underflow?

Start

No

Yes

Done

1. Compare the exponents of the two numbers.

Shift the smaller number to the right until its

exponent would match the larger exponent

2. Add the significands

3. Normalize the sum, either shifting right and

incrementing the exponent or shifting left

and decrementing the exponent

No Exception


Floating-Point Multiplication --

• Step1: Calculate the new exponent with the biased: 10 + ( - 5 ) = 5

• Step2: Next comes the multiplication of the significands:

The result is

• Step3: Normalize the result:

• Step4: We assume that the significand is only four digits long, so we must round the number:

• Step5: The sign of the product:

510 10200.910110.1 tenten

ten

ten

ten

10212000

9990

2220

0000

0000

200.9

110.1

510212.10 ten

65 100212.110212.10 tenten

66 10021.1100212.1 tenten

610021.1 ten


Decimal Floating-Point Multiplication --

• In binary, the task is multiplying

• Step1: - 1 + ( - 2 ) = - 3

• Step2: Multiplying the significands:

The result is

• Step3: The product is normalized and there is no overflow or underflow, since:

• Step4: Rounding the product makes no change

• Step5: Since the signs of the original operands differ, make the sign of the product negative:

)4375.0(5.0 tenten

21 2110.1by 2000.1 twotwo

two

two

two

1110000

1000

1000

1000

0000

110.1

000.1

32110.1 two

1263127

32110.1 two


FIGURE 3.18 Floating-point multiplication.


FIGURE 3.19 MIPS floating-point architecture revealed thus far.

MIPS floating-point operandsName Example Comments

32 floating-point registers

$f0, $f1, $f2, …, $f31 MIPS floating-point registers are used in pairs for double precision numbers.

memory words

Memory[0],Memory[4], …, Memory[4294967292]

Accessed only by data transfer instructions in MIPS. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures, arrays, and spilled registers, such as those saved on procedure calls.

302


MIPS assembly language


Arithmetic

FP add single add.s $f2, $f4, $f6 $f2 = $f4 + $f6 FP add (single precision)

FP subtract single sub.s $f2, $f4, $f6 $f2 = $f4 - $f6 FP sub (single precision)

FP multiply single mul.s $f2, $f4, $f6 $f2 = $f4 x $f6 FP multiply (single precision)

FP divide single div.s $f2, $f4, $f6 $f2 = $f4 / $f6 FP divide (single precision)

FP add double add.d $f2, $f4, $f6 $f2 = $f4 + $f6 FP add (double precision)

FP subtract double sub.d $f2, $f4, $f6 $f2 = $f4 - $f6 FP sub (double precision)

FP multiply double mul.d $f2, $f4, $f6 $f2 = $f4 x $f6 FP multiply (double precision)

FP divide double div.d $f2, $f4, $f6 $f2 = $f4 / $f6 FP divide (double precision)

Data transfer

load word corp. 1 lwc1 $f1, 100($s2) $f1 = Memory [$s2 + 100] 32-bit data to FP register

store word corp. 1 swc1 $f1, 100 ($s2) Memory [$s2 + 100] = $f1 32-bit data to memory

Conditional branch

branch on FP true bclt 25 if (cond == 1) go to PC+4+100 PC-relative branch if FP cond.

branch on FP false bclf 25 if (cond == 0) go to PC+4+100 PC-relative branch if not cond.

FP compare single

(eq, ne, lt, le, gt, ge)

c. lt. s $f2, $f4 if ($f2 < $f4)

cond =1; else cond = 0

FP compare less than single precision

FP compare double

(eq, ne, lt, le, gt, ge)

c. lt. d $f2, $f4 if ($f2 < $f4)

cond =1; else cond = 0

FP compare less than double precision


Name Format Example Comments

add.s R 17 16 6 4 2 0 add.s $f2, $f4, $f6

sub.s R 17 16 6 4 2 1 sub.s $f2, $f4, $f6

mul.s R 17 16 6 4 2 2 mul.s $f2, $f4, $f6

div.s R 17 16 6 4 2 3 div.s $f2, $f4, $f6

add.d R 17 17 6 4 2 0 add.d $f2, $f4, $f6

sub.d R 17 17 6 4 2 1 sub.d $f2, $f4, $f6

mul.d R 17 17 6 4 2 2 mul.d $f2, $f4, $f6

div.d R 17 17 6 4 2 3 div.d $f2, $f4, $f6

lwc1 I 49 20 2 100 lwc1 $f2, $f4, $f6

swc1 I 57 20 2 100 sec1 $f2, $f4, $f6

bc1t I 17 8 1 25 bc1t 25

bc1f I 17 8 0 25 bc1f 25

c. lt. s R 17 16 4 2 0 60 c. lt. s $f2, $f4

c. lt. d R 17 17 4 2 0 60 c. lf. d $f2, $f4

Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits ALL MIPS instructions 32 bits

MIPS floating-point machine language


FIGURE 3.20 MIPS floating-point instruction encoding.


Floating Point Complexities

• Operations are somewhat more complicated (see text)

• In addition to overflow we can have “underflow”

• Accuracy can be a big problem

– IEEE 754 keeps two extra bits, guard and round

– four rounding modes

– positive divided by zero yields “infinity”

– zero divide by zero yields “not a number”

– other complexities

• Implementing the standard can be tricky

• Not using the standard can be even worse

– see text for description of 80x86 and Pentium bug!


3.7 Real Stuff: Floating Point in the IA-32


FIGURE 3.21 The floating-point instructions of the IA-32.


FIGURE 3.22 The variations of operands for floating-point add in the IA-32.


3.8 Fallacies and Pitfalls


• Fallacy: Floating-Point addition is associative; that is, x + ( y + z) = ( x + y ) + z

• Pitfall: The MIPS instruction add immediate unsigned addiu sign-extends its 16-bit immediate field.

• Fallacy: Only theoretical mathematicians care about floating-point accuracy.


FIGURE 3.23 A sampling of newspaper and magazine articles from November 1994, including the New York Times, San Jose Mercury News, San Francisco Chronicle, and Infoworld.


3.9 Concluding Remarks


FIGURE 3.24 The MIPS instruction set covered so far.


FIGURE 3.25 Remaining MIPS-32 and “Pseudo MIPS” instruction sets.


FIGURE 3.26 The frequency of the MIPS instructions for SPEC2000 integer and floating point.


Chapter Three Summary

• Computer arithmetic is constrained by limited precision

• Bit patterns have no inherent meaning but standards do exist

– two’s complement

– IEEE 754 floating point

• Computer instructions determine “meaning” of the bit patterns

• Performance and accuracy are important so there are manycomplexities in real machines

• Algorithm choice is important and may lead to hardware optimizations for both space and time (e.g., multiplication)

• You may want to look back (Section 3.10 is great reading!)

Documents

1 2004 Morgan Kaufmann Publishers Chapter Three : Arithmetic for Computers