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3-Software Design Basics in Embedded Systems
2
Introduction
General-Purpose Processor Processor designed for a variety of computation tasks Low unit cost, in part because manufacturer spreads NRE over large
numbers of unitsMotorola sold half a billion 68HC05 microcontrollers in 1996 alone
Carefully designed since higher NRE is acceptableCan yield good performance, size and power
Low unit cost, short time-to-market/prototype, high flexibilityUser just writes software; no processor design
a.k.a. “microprocessor” – “micro” used when they were implemented on one or a few chips rather than entire rooms
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Basic Architecture
Control unit and data-path Note similarity to single-
purpose processor
Key differences Data-path is general Control unit doesn’t store
the algorithm – the algorithm is “programmed” into the memory
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
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Data-path Operations
Load Read memory location into
register
• ALU operation– Input certain registers
through ALU, store back in register
• Store– Write register to
memory location
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
10
+1
11
11
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Control Unit Control unit: configures the datapath
operations Sequence of desired operations
(“instructions”) stored in memory – “program”
Instruction cycle – broken into several sub-operations, each one clock cycle, e.g.:
Fetch: Get next instruction into IR Decode: Determine what the instruction
means Fetch operands: Move data from memory to
datapath register Execute: Move data through the ALU Store results: Write data from register to
memory
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
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Control Unit Sub-Operations
Fetch Get next instruction into
IR PC: program counter,
always points to next instruction
IR: holds the fetched instruction
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100 load R0, M[500]
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Control Unit Sub-Operations
Decode Determine what the
instruction means
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100 load R0, M[500]
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Control Unit Sub-Operations
Fetch operands Move data from
memory to data-path register
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100 load R0, M[500]
10
9
Control Unit Sub-Operations
Execute Move data through the
ALU This particular
instruction does nothing during this sub-operation
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100 load R0, M[500]
10
10
Control Unit Sub-Operations
Store results Write data from register
to memory This particular
instruction does nothing during this sub-operation
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100 load R0, M[500]
10
11
Instruction Cycles
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
PC=100
10
Fetch ops
Exec. Store results
clk
Fetch
load R0, M[500]
Decode
100
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Instruction Cycles
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
10
PC=100Fetch Decode Fetch
opsExec. Store
resultsclk
PC=101
inc R1, R0
Fetch Fetch ops
+1
11
Exec. Store results
clk
101
Decode
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Instruction Cycles
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
10...
...
load R0, M[500] 500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
1110
PC=100Fetch Decode Fetch
opsExec. Store
resultsclk
PC=101Fetch Decode Fetch
opsExec. Store
resultsclk
PC=102
store M[501], R1
Fetch Fetch ops
Exec.
11
Store results
clk
Decode
102
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Architectural Considerations
N-bit processor N-bit ALU, registers,
buses, memory data interface
Embedded: 8-bit, 16-bit, 32-bit common
Desktop/servers: 32-bit, even 64
PC size determines address space
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
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Architectural Considerations
Clock frequency Inverse of clock period Must be longer than
longest register to register delay in entire processor
Memory access is often the longest
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
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Pipelining: Increasing Instruction Throughput
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Fetch-instr.
Decode
Fetch ops.
Execute
Store res.
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Wash
Dry
Time
Non-pipelined Pipelined
Time
Time
Pipelined
pipelined instruction execution
non-pipelined dish cleaning pipelined dish cleaning
Instruction 1
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Superscalar Architectures
Performance can be improved by: Faster clock (but there’s a limit) Pipelining: slice up instruction into stages, overlap stages Multiple ALUs to support more than one instruction stream
Superscalar• Scalar: non-vector operations• Fetches instructions in batches, executes as many as possible
May require extensive hardware to detect independent instructions
(e.g. multiple ALUs)• VLIW (Very Long Instruction Word): each word in memory has multiple
independent instructions Relies on the compiler to detect and schedule instructions Currently growing in popularity CISC vs RISC?
![Building a Quantum Information Processor using ... · [M. Nielsen and I. Chuang, Quantum Computation and Quantum Information (Cambridge, 2000)] • Quantum information processing](https://img.pdfslide.net/doc/110x75/5b8106597f8b9a2a088e3dd6/building-a-quantum-information-processor-using-m-nielsen-and-i-chuang.jpg)
