1 ( 77 points) 45 min. · 2019-04-19 · 1 ( 77 points) 45 min. Topic: State Machine Design, Datapath Design, Verilog Coding You all have designed and coded the make_A_close_to_B

ee201_final_Sp2014.fm

May 11, 2014 9:23 pm EE201L Final Exam - Spring 2014 1 / 9 C Copyright 2014 Gandhi Puvvada

Spring 2014 EE201L Instructor: Gandhi Puvvada Final Exam (20%) Date: May 14, 2014, Wednesday Open-Book Open-Notes Exam Time: 10:30 AM-1:20 PM SAL101

Name: Total points: 232 Perfect score: 220 / 232

1 ( 77 points) 45 min. Topic: State Machine Design, Datapath Design, Verilog Coding

You all have designed and coded the make_A_close_to_B design.

1.1 Redesign the same with the modification that A is initially higher (or equal) to B. A approaches B from the top. You initially subtract 100 at a time and if you undershoot (go below B), then you add a 10 at a time to make A come as close to B as possible but not below B.

Examples: Find the # of clocks spent in ADJ state and also find if flag is found set in the Done state.Ain = 768; Bin = 312;

Then A = 768; 668, 568, 468, 368, 268, 278, 288, 298, 308, 318; In DONE, A is 318. Clocks in ADJ: ________ Flag is set in Done State: T / F

Ain = 712; Bin = 312; Then A = 712; 612, 512, 412, 312; In DONE, A is 312.Clocks in ADJ: ________ Flag is set in Done State: T / F

Ain = 702; Bin = 312; Then A = 702; 602, 502, 402, 302, 312; In DONE, A is 312.Clocks in ADJ: ________ Flag is set in Done State: T / F

6pts

14pts

Start

Res

et

INITIALADJUST

StartA <= Ain;B <= Bin;F <= 0;

DONE

ACK

ACK

Notes and handouts in ring binders only



1.2 Now, like in the Timing lab, where you do multiple subtractions in one clock, here you subtract a maximum of two 100’s in a clock and if you undershoot you add a maximum of three 10's in an another clock. On the next page you are provided with most of the Verilog code except for the ADJ state case branch, which you complete below. For the subtraction of the two hundreds (at most), do not use a "for" loop (code the lines explicitly) but to do the three additions of tens, use a "for" loop. Use one single variable A_temp to carry all intermediate values of A in a clock. Of course the value of A_temp should be transferred back to A at the end of the every clock and at the beginning of the next clock, you gather again the value of A into A_temp and manipulate it in A_temp using several coding steps. The purpose of the exercise is to let you demonstrate your understanding of how and where to use Blocking and Non-blocking assignments in Verilog coding.

26pts

ADJ: begin

// state transitions

if ( )

state <= DONE;

// RTL in the Data Path A_temp A; // Gather A in A_temp // subtract 1 or 2 hundreds if appropriate

if ( ) // Condition C1

begin

end

// add tens if appropriate in a "for" loop // you can set flag here (more than once!)

if ( ) // Condition C2

begin

end

A A_temp; // at the end, return the value to A end



module make_A_close_to_B (Ain, Bin, Start,

Ack, Clk, Reset, Flag, Qi, Qa, Qd, A);

input [11:0] Ain, Bin;

input Start, Ack, Clk, Reset;

output Flag; // Flag FF

output Qi, Qc, Qd;

output [11:0] A;

// Rest are wire by default

reg [11:0] A, B;

reg [2:0] state;

reg Flag;

localparam

INI

= 3'b001,

ADJ

= 3'b010,

DONE

= 3'b100;

assign {Qd, Qa, Qi} = state;

always @(posedge Clk, posedge Reset)

begin : CU_n_DU // named procedural block

integer INT; // local integer variable

reg [11:0] A_temp;

if (Reset)

begin

state <= INI;

A <= 12'bXXXXXXXXXXXX;

B <= 12'bXXXXXXXXXXXX;

Flag <= 1'bX;

end

else

begin

case (state)

INI:

begin

if (Start)

state <= ADJ;

A <= Ain;

B <= Bin;

Flag <= 0;

end

ADJ:

DONE:

begin

if (Ack)

state <= INI;

end

endcase

end

end

endmodule

CODE TO BE WRITTEN BY THE STUDENT



Notice that we either subtract 1 or 2 hundreds if needed in a clock or add 1 or 2 or 3 tens if needed in a clock. In the same clock we do *not* subtract a hundred as well as add a ten in this design. Though that is not impossible or wrong, that is a question for EE560 class in Summer 2014!

1.2.1 Are the conditions C1 and C2 on page 2 opposite of each other? Yes / No Consider the example of Ain = 312 and Bin = 312 and explain. ________________________________________________________________________________________________________________________________________________________

1.2.2 For Ain = 313 and Bin = 312, ______ (1 / 2) hundred(s) is/are subtracted in _______ (1 / 2) clocks and then ______ tens are added in _______ clocks. At the end of all the adjustments (subtracting hundreds and further adding tens if needed), do we spend an extra clock in ADJ state to realize that it is time to move to the DONE state. Yes / NoThis behavior (of spending or not spending an extra clock at the end of adjustment) is __________________________ (the same as / different from) the design on page 1.

1.2.3 Data path for the A register (just the A register). You do not have to do the datapath of the flag flip-flop or the B-reg. Note that there can be several choices for the datapath design. This is just one way. The CWB below stands for "Compare With B" Assume one-hot method of implementation and use (QI, QA, QD) as needed in controlling the datapath. Generate the needed control signals (OFL)

5pts

6+2pts

18pts

I0

SI1Y

adde

r

10

I0

SI1Y

subt

ract

er

100

I0

SI1Y

subt

ract

er

100

I0

SI1Y

adde

r

10I0

SI1Y

adde

r

10

CWBY

X

X>Y

X<YCWB

Y

X

X>Y

X<Y

CWBY

X

X>Y

X<YCWB

Y

X

X>Y

X<YCWB

Y

X

X>Y

X<Y

D[11:0]

Q[11:0]

CLK

A - regAin

CLK



2 ( 47 points) 35 min. Topic: Memory

2.1 If the 32Kx8 memory is built using the 4 chips as shown on the side starting at A8000 Hex in a 20-bit address system (1MByte address space), fill-in the 7 boxes with 3 more staring addresses and 4 ending addresses for the 4 chips.Out of the following 3 other alternatives, which is/are undesirable and why?

Explain: _____________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________

2.2 Memory map reading and interpreting: State the size and range of the shaded area in the map on the side. Assume that there is a RAM memory chip occupying that area and generate a low active chip-select signal CS when an address appears on A15-A0 which falls in the shaded area. Label the address pins and complete the address connections to the RAM chip below.

2.3 Example statement for decimal numbers: 7432 is part of the natural range of hundred numbers 7400-7499 and is also part of the natural range of thousand numbers 7000-7999.Make a similar statement for binary numbers: 1011_0111_1000_0110 is part of the natural range of 1024 (= 210) numbers ____________________________ to __________________________Let us now restate the above sentence in hexadecimal. _________ hex is part of the natural range of 1024 (= 210) numbers ________ hex to ________ hex.

2.4 Using the 8 mem. chips, build as big a byte-wide memory system as possible. Produce CSLL (Chip-Select Left Lower), CSLU (Chip-Select Left Upper) and CSR (Chip-Select Right) as function of the overall CS and label the address pins. Complete connections and labels.

8Kx8

4Kx8

4Kx8

16Kx8

A8000 H

15pts

8Kx8

4Kx8

4Kx8

16Kx8

8Kx8

4Kx8

4Kx8

16Kx8

8Kx8

4Kx8

4Kx8

16Kx8

Undesirable? Yes / No



0000

FFFF10pts

D7-D0

A -A0

OEWECSCS

MEMW

MEMR

D7-D0

Size: __________Range: _________

4pts



3 ( 16 points) 8 min. Counters

3.1 Compare synchronous counters with ripple counters below.

3.2 Special counter:

18pts

D0

D0

D[1:0]

A11-A0

OE

WECSCSLU

MEMW

MEMR

D0

A12-A0

OE

WECSCSR

MEMW

MEMR

D0

Out of the 8 chips, left 4 are of ______________ sizeand the right 4 are of _______________ size.Putting these together, you formed x8 size memory,

D[1:0]

D[1:0]

A11-A0

OE

WECSCSLU

MEMW

MEMR

D[1:0]

CSoverall CS

3+3pts

10pts

A0A1A2

B0B1B2

S0S1S2

Adder

I00I01I02

I10I11I12

Y0Y1Y2

S

Mux

100 1

11

D Q

Register

Q0

Q1

Q2

D Q

D Q

CLK

CLR

LSB

MSB

RESET

D QCLKCLK

RESETCLR

Write down the repetitive pattern of the three bit counter starting from zero.

________________________________________________________________________________________

7

Special

________________________________________________________________________________________

When Special = 0

When Special = 1



4 ( 34 points) 20 min. Topic: FIFO

4.1 A 16x8 and a 1Kx8 have the same pinout. True / FalseA 32x4 and a 16x8 have the same pinout. True / False

4.2 The consumer issues request to read (REN) ________________________ (after checking / without caring to check) to see if the FIFO is running _______ (FULL / EMPTY). If the FIFO is actually running ___________ (FULL / EMPTY), the RENQ (Read Enable Qualified) _____________ (will / will not) be activated and the read request gets refused. The consumer will come to know this (will recognize this) towards the __________ (end / beginning) of the __________(current / next) clock and will retry to consume the same item in the next clock.

4.3 Reproduced below is the question together with its answer from a previous exam.In the case of the 8-location FIFO discussed in class, the actual depth legal values are ___9___ (7/8/9/other). Another design to produce the depth, is to add a 4-bit UP/DOWN (U/D) counter (with enable (EN) control), which displays depth of the FIFO all the time. It is incremented or decremented or retained at its current value as needed. Fill-in the truth table on the side

4.3.1 Mr. Bruin further added saying that, to implement the above in a 2-clock FIFO, one should have one such up_bar/down counter in each of the two clock domains. The one on the write-side should use WENQ and RENQ_SS (RENQ double-synchronized to the WCLK). Similarly the up_bar/down counter on the read-side should use WENQ_SS and RENQ. You know Mr. Bruin is wrong but why? ___________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

4.4 For an 8-location 2-clock FIFO, to convey the WP to the _____________ (producer /consumer) and the RP to the _____________ (producer /consumer), you would use ______ (2-bit / 3-bit / 4-bit) GRAY code counters. Binary counters are not used because __________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

4.4.1 We used the words "either the new or the old value but never an absurd value" to describe ______________________________________________________________________________________________________________________________________________________________

4.4.2 Suppose we have FIFOs of only one type in our lab: single-clock FIFO or the two-clock FIFO and we need to finish our project, sometimes with inferior choices. We can use a single-clock FIFO for both kinds of applications. True / FalseWe can use a two-clock FIFO for both kinds of applications. True / False

2+2pts

6+3pts

0WENQ RENQ EN U/D

00 11 01 1

10

01

X10X

8pts

6pts

4pts

2+1pts



5 ( 30 points) 20 min. Combinational Logic

5.1 We have 9 2-to-1 muxes and 18 4-to-1 muxes in our lab. Show how would you build an 8-input 8-output barrel shifter by stating so-and-so muxes in such-and-such column/row governed by select lines ... ____________________________________________________________________________________________________________________________________________________________________________________________________________________________________

5.2 You have seen the tree of OR gates on the left below. Assume that we have only 2-input OR gates and each OR gate has 1ns delay. The second design is desirable if X6 and X7 are late at least by___________ ns. Suppose only X7 is late by 3ns. (i) What would be the delay in producing Y in the left circuit? _____ (ii) What would be the delay in producing Y in the right circuit? _____(iii) Improve the right circuit to suit and state the delay of Y in your revised circuit. _______

5.2.1 If you were to perform ORing of 256 signals using 2-input OR gates in a tree fashion, you need _______________________ OR gates arranged in _______ levels. But if you are given 4-input OR gates, you need _______________________ 4-input OR gates arranged in _______ levels.

5.2.2 Using 6 of 74LS85 magnitude comp. units, TI has shown a design to compare two _______ (20/24/25/26/30/other) -bit items. If we have only 5 of these chips, what is the biggest 2-level tree comparator we can build? _________ Exaplain:_________________________________________

5.3 You are given an incomplete design of a 2-to-1 mux with an overall enable control E. Using additional gates as needed, complete the design and on the side and label the inputs (S, I0, and I1). What is the purpose of the pull-up resistance? ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

4pts

4+2pts

X0X1

X2X3

X4X5

X6X7

Y

X0X1

X2X3

X4X5

X6X7

Y

Q#5.2.2

4+2pts

4+2pts

E

Y

8pts


May 14, 2014 11:32 am EE201L Final Exam - Spring 2014 9 / 9 C Copyright 2014 Gandhi Puvvada

6 ( 28 points) 25 min. Topic: State machine design

You know that our stock market sometimes goes up and down too much and we describe it as volatile. You are given an array of 10 past values of the stock index. Assume that the 10 values are distinct (non-repeating) values. The market is *not* volatile (a) if the stock index was monotonically ascending or descending or (b) there was at most one trend change (i.e. initially ascending and later descending or initially descending and later ascending). To find if it is ascending or descending, you compare each M[I] with the previous M[I] stored in a P register (P for previous). Obviously there is no previous for the M[0]. So we have a state called LP (Load Previous) to initialize P with M[I] when I = 0 and a state called CFT (Compare First to know the initial Trend). ASC1 and ASC2 stand for Ascending first and Ascending second (second after an initial descending trend). Similar are DEC1 and DEC2. The NOR (for normal state) is reached at the end if it is not volatile. You may reach the VOL state without going through the complete array.

All state transition arrows are in place. Complete state transition conditions and also RTL in ASC2 and DSC2. The value of I in NOR state is ____________ (always / sometimes) ____(9/10).

2+2pts

24pts

START

STA

RT

~RE

SET

INI

I <= 0;

CFT

I <= I + 1;P <= M[I];

ASC1

I <= I + 1;P <= M[I];

DEC1

I <= I + 1;P <= M[I];

DSC2

ASC2

NOR VOL

AC

K

ACK

ACK

AC

K

The TAs, Graders, and I have enjoyed teaching this course. Hope you also liked the course. Hope to see you again in EE454L and EE457. -- Gandhi

LP

I <= I + 1;P <= M[I];

1

Documents

1 ( 77 points) 45 min. · 2019-04-19 · 1 ( 77 points) 45 min. Topic: State Machine Design, Datapath Design, Verilog Coding You all have designed and coded the make_A_close_to_B