1 A Fast, Analytical Estimator for the SEU-induced Pulse Width in Combinational Designs By: Rajesh Garg Charu Nagpal Sunil P. Khatri Department of Electrical

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A Fast, Analytical A Fast, Analytical Estimator for the SEU-Estimator for the SEU-induced Pulse Width in induced Pulse Width in Combinational DesignsCombinational Designs

By:By:Rajesh GargRajesh Garg

Charu NagpalCharu NagpalSunil P. KhatriSunil P. Khatri

Department of Electrical and Computer Department of Electrical and Computer Engineering,Engineering,

Texas A&M University, College Station, TXTexas A&M University, College Station, TX

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OutlineOutline

IntroductionIntroduction Previous WorkPrevious Work ObjectiveObjective ApproachApproach

Classification of Radiation Particle StrikesClassification of Radiation Particle Strikes Our ModelOur Model

Experimental ResultsExperimental Results ConclusionsConclusions

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IntroductionIntroduction Modern VLSI DesignsModern VLSI Designs

Vulnerable to noise effects- crosstalk, SEU, etcVulnerable to noise effects- crosstalk, SEU, etc Single Event UpsetsSingle Event Upsets (SEUs) or Soft Errors (SEUs) or Soft Errors

Troublesome for both memories and Troublesome for both memories and combinational logiccombinational logic

Becoming increasingly problematic even for Becoming increasingly problematic even for terrestrial designsterrestrial designs

Applications demand reliable systemsApplications demand reliable systems Need to Need to efficientlyefficiently design design radiation tolerant radiation tolerant

circuitscircuits Analyze circuits early in design flowAnalyze circuits early in design flow Hence need SEU Hence need SEU robustness metricrobustness metric

Harden the circuits using these Harden the circuits using these metricsmetrics Approach depends on level of protection requiredApproach depends on level of protection required Need to satisfy Need to satisfy delay, area and powerdelay, area and power constraints constraints

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SEU Robustness MetricsSEU Robustness Metrics SPICESPICE based simulation of SEU events based simulation of SEU events

Most accurate metric possible Most accurate metric possible Computationally Computationally expensiveexpensive Too many scenarios required to be Too many scenarios required to be

simulatedsimulated Amount of charge dumpedAmount of charge dumped State of circuit inputsState of circuit inputs Need to simulate all nodes in a circuitNeed to simulate all nodes in a circuit

Hence we need an efficient and Hence we need an efficient and accurate SEU robustness metric accurate SEU robustness metric

This is the focus of this talkThis is the focus of this talk

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SEU Robustness MetricsSEU Robustness Metrics

Accurate and efficientAccurate and efficient models for SEU models for SEU eventsevents Can be used to harden a circuitCan be used to harden a circuit Requires solving of non-linear differential Requires solving of non-linear differential

equations.equations.

Our metric is based on theOur metric is based on the pulse width pulse width of of voltage glitch due to a radiation strike voltage glitch due to a radiation strike Good measure of SEU robustnessGood measure of SEU robustness Based on the pulse width, we can upsize Based on the pulse width, we can upsize

susceptible gates susceptible gates Easily incorporatedEasily incorporated in design flow in design flow

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Radiation Particle StrikeRadiation Particle Strike Effects of radiation particle strikeEffects of radiation particle strike

Neutron, proton and heavy cosmic ionsNeutron, proton and heavy cosmic ions Ions strike diffusion regionsIons strike diffusion regions Deposit chargeDeposit charge Results in a voltage spikeResults in a voltage spike

Radiation particle strike is modeled by a Radiation particle strike is modeled by a current pulse ascurrent pulse as

wherewhere:: Q is the amount of charge deposited Q is the amount of charge deposited

is the collection time constantis the collection time constant

is the ion track establishment constantis the ion track establishment constant

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Previous WorkPrevious Work Device-level simulation:Device-level simulation: Dodd et. al 1994, etc Dodd et. al 1994, etc

Accurate but very time consumingAccurate but very time consuming Not practical for circuit hardeningNot practical for circuit hardening

Logic-level simulation:Logic-level simulation: Cha et. al 1996 Cha et. al 1996 Abstract transient faults by logic-level modelsAbstract transient faults by logic-level models Gate-level timing simulators are usedGate-level timing simulators are used Highly inaccurate as a robustness metric for Highly inaccurate as a robustness metric for

hardening purposeshardening purposes

Circuit-level simulation:Circuit-level simulation: Intermediate between device and logic level Intermediate between device and logic level

simulationsimulation

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Previous WorkPrevious Work Shih et. al 1992 solve transistor non-linear Shih et. al 1992 solve transistor non-linear

differential equation using infinite power seriesdifferential equation using infinite power series Computationally expensiveComputationally expensive

Dahlgren et. al 1995 presented switch level simulatorDahlgren et. al 1995 presented switch level simulator Electrical simulations are performed to obtain the pulse Electrical simulations are performed to obtain the pulse

width of a voltage glitch, using the R and C values of a gatewidth of a voltage glitch, using the R and C values of a gate Pulse width for other R and C values are obtained using Pulse width for other R and C values are obtained using

linear relationship between the obtained pulse width and the linear relationship between the obtained pulse width and the new R and C valuesnew R and C values

Cannot be used for different values of Cannot be used for different values of Q Q

Mohanram 2005 reports a closed form model for SEU Mohanram 2005 reports a closed form model for SEU induced transient simulation for combinational induced transient simulation for combinational circuitscircuits Linear RC gate model is usedLinear RC gate model is used IgnoresIgnores the contribution of the contribution of in in iiseuseu(t) – (t) – we find that this we find that this

results in 10% errorresults in 10% error Results in Results in lower accuracylower accuracy

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ObjectiveObjective

Develop an Develop an analytical modelanalytical model for SEU for SEU induced transients in combinational circuitsinduced transients in combinational circuits Closed form analytical expressionClosed form analytical expression for the for the pulse pulse

widthwidth of voltage glitch of voltage glitch Accurate and efficientAccurate and efficient Applicable to Applicable to

Any logic gate Any logic gate Different gate sizes Different gate sizes Different gate loadingDifferent gate loading

IncorporatesIncorporates the contribution of the contribution of time constant time constant Can be Can be easily integratedeasily integrated in a design flow in a design flow

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Our ApproachOur Approach Radiation particle strike at the output of INV1Radiation particle strike at the output of INV1 Implemented using 65nm PTM with VDD=1VImplemented using 65nm PTM with VDD=1V Radiation strike: Radiation strike: QQ=150fC, =150fC, =150ps & =150ps & =50ps=50ps

Models Radiation Particle Strike

M1 in Linear

M2 in Cutoff

M1 in Saturation

M2 in Cutoff

M1 in Saturation

M2 in Saturation

M1 and M2 operate in different regions during radiation-induced transients

Our approach estimates the pulse width of the transient by modeling these regions

INV1 cannot be modeled accurately by a linear RC model (as was done in several previous approaches)

M1 in Saturation

M2 in Saturation

M2’s Drain-Bulk diode is ON

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Classification of Classification of Radiation StrikeRadiation Strike

INV1 can operate in INV1 can operate in 4 different cases4 different cases depending upon voltage glitch depending upon voltage glitch magnitude magnitude VVGM GM ((=V=Vaa))

Case 1: Case 1: VVGM GM ≥≥ VDD + 0.6V VDD + 0.6V

Case 2: VDD+|VCase 2: VDD+|VTPTP| | ≤≤ VVGM GM < VDD + 0.6V< VDD + 0.6V

Case 3: 0.5Case 3: 0.5**VDD VDD ≤≤VVGM GM <<VDD+|VVDD+|VTPTP||

Case 4: Case 4: VVGM GM < < 0.50.5**VDDVDD

Different analytical models are applicable to differentDifferent analytical models are applicable to different

cases to compute pulse width of the voltage glitchcases to compute pulse width of the voltage glitch

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Model OverviewModel OverviewGiven a gate G, its input

state, the gates in the fanoutof G and Q, and

Determine the value of VGM &case of operation

If Case==4Pulse Width is 0Yes No

Compute t1

If Case==1 use

its model to compute t2

If Case==2 use


If Case==3 use


Compute Pulse Width as t2-t1

Cell library data IDS(VDS)forVGS=1 and 0, CG and CD

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Voltage Glitch Voltage Glitch Magnitude (Magnitude (VVGMGM))

IIDSDS of NMOS transistor with gate terminal at VDD of NMOS transistor with gate terminal at VDD

Differential equation for radiation induced voltage Differential equation for radiation induced voltage transient at output of INV1transient at output of INV1

(1) (1)

t

Va(t)Green Known

Red Unknown

Integrate Equation 1 from

(0, 0) to (Vdsat, Tsat)

withnDS

VDS RVI a /

Tsat

Vdsat

Solve for Tsat

Again integrate Equation 1 with initial condition (Vdsat, Tsat) and with

DSVDS VKKI a 43

TVGM

VGM

Obtain TVGM by

differentiating Va(t) and solving dVa(t)/dt

= 0

Now VGM = Va(TVGM

)

* Details can be found in the paper

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VVGMGM = = VVaa(T(TVVGMGM) where) where

X’X’, , Y’Y’ and and Z’Z’ are constants defined in the paper are constants defined in the paper is the time when is the time when iiseuseu((tt) is at its maximum value) is at its maximum value

Diff. eq. for radiation induced voltage transient at output of Diff. eq. for radiation induced voltage transient at output of INV1INV1

Does not include the drain to source current of M2 (PMOS)Does not include the drain to source current of M2 (PMOS) Accurate for Case 3 and 4Accurate for Case 3 and 4 In some cases, Case 2 In some cases, Case 2 VVGMGM value can be diagnosed as Case 1- value can be diagnosed as Case 1-

PessimisticPessimistic

maxseuT

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Next StepsNext Steps

Once we know Once we know VVGMGM , we know which case is , we know which case is applicable (among cases 1, 2, and 3).applicable (among cases 1, 2, and 3).

The magnitude of the SET induced glitch is The magnitude of the SET induced glitch is tt22 – t– t11

Next, we find an expression for Next, we find an expression for tt11 (common for (common for all 3 cases)all 3 cases)

Then we will find expressions for Then we will find expressions for tt22 (separately for each of the 3 cases)(separately for each of the 3 cases)

Note that case 4 is not of interest since the Note that case 4 is not of interest since the glitch magnitude is less than VDD/2 in case 4.glitch magnitude is less than VDD/2 in case 4.

Lets do this over the next few slides…Lets do this over the next few slides…

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Expression for Expression for tt11

If If VVGMGM > 0.5*VDD then > 0.5*VDD then

there is a glitchthere is a glitch

t

Va(t)Green Known

Red Unknown

Tsat

Vdsat

TVGM

VGM

To obtain t1 , substitute Va(t1) =

0.5*VDD and solve for t1 using initial

guess t1

0.5*VDDat1

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Expression for Expression for tt22 : : Case 1Case 1 For Case 1, For Case 1, VVGMGM ≥ VDD+0.6V ≥ VDD+0.6V

VVaa((tt33) = VDD +|) = VDD +|VVTPTP|| IIDSDS of PMOS M2 is zero of PMOS M2 is zero

iiseu seu ((tt33) = ) = IIDSDS of M1of M1

Also ignore Also ignore

This gives us This gives us tt33 below below

Use, Use, VVaa((tt) = VDD +|) = VDD +|VVTPTP| |

at at t t = = tt3 3 as as initial condition initial condition

for integration. for integration.

VDD+|VTP|

t3

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Expression for Expression for tt2 2 : Case 1: Case 1

Approximate Approximate iiseuseu((tt) by a ) by a straight linestraight line

t

Va(t)

Green Known

Red Unknown

t3

VDD+|VTP|VGM

t1

0.5*VDD

t2

iseu(t)

Va(t)

t*

Integrate Equation 1 with initial condition (VDD+|VTP|, t3)

Substitute Va(t) = 0.5*VDD for t = t2 and

solve for t2 by performing a quadratic

expansion around initial guess

12at

P, Q, R and P, Q, R and t* t* are constants defined in the paperare constants defined in the paper Details of derivation of t2 can be found in the paper

)(5.0 2/|| VDDDS

VVDDDS II TP

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For Case 2: For Case 2: VDD+|VVDD+|VTPTP||

≤≤VVGMGM<<VDD+0.6VVDD+0.6V

Again use initial condition,Again use initial condition, VVaa((tt)=VDD+|)=VDD+|VVTPTP| at | at t t = = tt33

t

Va(t) Green Known

Red Unknown

t3

VDD+|VTP|

TVGM

VGM

t1

0.5*VDD

t2

Integrate Equation 1 with initial condition (VDD+|VTP|, t3)

To obtain t2 , substitute

Va(t2)=0.5*VDD and solve for t2

by using initial guess

22at

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For Case 3:For Case 3: 0.50.5**VDDVDD≤≤VVGMGM<<VDD+|VVDD+|VTPTP||

t

Va(t)Green Known

Red Unknown

Tsat

Vdsat

TVGM

VGM

To obtain t2 , substitute

Va(t2)=0.5*VDD and solve for t2

by using initial guess t1

0.5*VDD

t2

22at

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Experimental ResultsExperimental Results

Implemented our Implemented our modelmodel in in PerlPerl Library of INV, NAND and NOR gatesLibrary of INV, NAND and NOR gates

Using 65nm PTM model card with VDD=1VUsing 65nm PTM model card with VDD=1V Characterized each gate for Characterized each gate for IIDSDS, , CCGG and and CCDD

Applied our model to INV and NAND2Applied our model to INV and NAND2 For different values of For different values of QQ, , and and

Different gate sizes and loadsDifferent gate sizes and loads Our model is 1000X faster compared to Our model is 1000X faster compared to

SPICESPICE

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Radiation particle strike at the output INV1 Radiation particle strike at the output INV1 withwith Q Q=150fC, =150fC, =150ps and =150ps and = 50ps= 50ps

INV1 with input 1 INV1 with input 0

Load Size PWS(ps) PWM(ps) % Error PWS(ps) PWM(ps) % Error

1 1 533 533 0 517 522 0.97

1 2 414 415 0.24 404 410 1.49

1 4 292 296 1.37 285 298 4.56

1 6 213 223 4.69 208 231 11.06

1 8 142 146 2.82 140 141 0.71

3 1 552 553 0.18 535 533 -0.37

3 2 432 434 0.46 420 420 0

3 4 308 315 2.27 301 306 1.66

3 6 227 239 5.29 221 221 0

3 8 147 152 3.4 147 148 0.68

AVG 2.072.07 2.152.15

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NAND2 gate withNAND2 gate with Q Q=150fC, =150fC, =150ps and =150ps and = 50ps= 50ps

Average pulse width estimation error Average pulse width estimation error compared to SPICEcompared to SPICE

INPUT 11 INPUT 00 INPUT 01 INPUT 10

Load Size % Error % Error % Error % Error

1 1 0 -0.74 -0.19 -0.56

1 2 0.78 1.05 0.24 -0.24

1 4 3.05 0.71 2.41 1.67

1 6 10.34 - 7.55 -0.45

3 1 0.58 0.24 -0.55 -0.36

3 2 1.25 2.39 -0.24 0

3 4 4.01 0.69 1.64 1.27

3 6 3.8 - 0 0

AVGAVG 2.97 0.97 1.6 0.57

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ConclusionConclusion A SEU robustness metric is required to design radiation A SEU robustness metric is required to design radiation

tolerant circuits efficientlytolerant circuits efficiently We presented an analytical model to compute this We presented an analytical model to compute this

metric (which is the pulse width of the SEU induced metric (which is the pulse width of the SEU induced glitch)glitch) Pulse width of the glitch is a good measure of SEU robustnessPulse width of the glitch is a good measure of SEU robustness

Our model is accurate and efficientOur model is accurate and efficient Pulse width estimation error is 3% compared to SPICEPulse width estimation error is 3% compared to SPICE Our method is 1000X faster than SPICEOur method is 1000X faster than SPICE

Our model gains accuracyOur model gains accuracy By using the transistor current model (and avoiding a linear RC By using the transistor current model (and avoiding a linear RC

model for the gate)model for the gate) By including the contribution of By including the contribution of

Our model can be easily incorporated in a design flow to Our model can be easily incorporated in a design flow to test robustness. Based on the results, hardening can be test robustness. Based on the results, hardening can be performed.performed.

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Thank YouThank You

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BACKUP SLIDESBACKUP SLIDES

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IIDSDS of NMOS transistor with gate of NMOS transistor with gate terminal at VDDterminal at VDD

For 65nm PTM model card For 65nm PTM model card VVdsatdsat< < 0.5*VDD0.5*VDD Integrate Eq. 1 from Integrate Eq. 1 from VVaa((tt)=0 at )=0 at tt=0 to =0 to VVaa((tt)=)=VVdsatdsat

at at tt==TTsatsat using using IIDSDS = = VaVa//RRDSDS

Solve for Solve for TTsatsat by linearly expanding around initial by linearly expanding around initial guess guess TTaa

satsat, we get, we get

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To calculate To calculate TTaasatsat, , approximate the rising part of approximate the rising part of iiseuseu((tt) by ) by

a linea line Substitute Substitute iiseuseu((tt) in Eq. 1 by a line between origin and ) in Eq. 1 by a line between origin and IImaxmax

seuseu

Integrate Eq. 1 from Integrate Eq. 1 from VVaa((tt)=0 at )=0 at tt=0 to =0 to VVaa((tt)=)=VVdsatdsat at at tt==TTaasatsat

Solve for Solve for TTaasatsat by quadratic expansion around originby quadratic expansion around origin

Now, integrate Eq. 1 with initial condition Now, integrate Eq. 1 with initial condition VVaa((tt)=)=VVdsatdsat at at tt==TTsatsat

Use Use IIDSDS = = KK33 + + KK44.V.VDSDS for this integrationfor this integration

(2)(2)

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Differentiate Differentiate VVaa((tt) (Eq. 2) and solve ) (Eq. 2) and solve

dVdVaa((tt)/)/dt =dt =0 for0 for TTVVGMGM Linearly expand around Linearly expand around TTmaxmax

seuseu

Now, Now, VVGMGM = = VVaa(T(TVVGMGM))

If If VVGMGM > VDD + 0.6V then set > VDD + 0.6V then set VVGMGM = = VDD + 0.6VVDD + 0.6V Diode is not modeled in Eq. 2Diode is not modeled in Eq. 2

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Expression for Expression for tt11

If If VVGMGM > 0.5*VDD then there is a glitch > 0.5*VDD then there is a glitch

Substitute Substitute tt = = tt11 and and VVaa((tt11) = 0.5*VDD in Eq. ) = 0.5*VDD in Eq. 22 Expand linearly around Expand linearly around ttaa

1 1 = T= TsatsatVDD/(2VDD/(2VVdsatdsat))

(3)(3)

Eq. 3 is used to compute Eq. 3 is used to compute tt11 for Cases 1, 2 for Cases 1, 2 and 3 and 3

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Expression for Expression for tt22 : : Case 1Case 1

For Case 1, For Case 1, VVGMGM ≥ VDD+0.6V ≥ VDD+0.6V

VVaa((tt33) = VDD-|) = VDD-|VVTPTP|| IIDSDS of PMOS M2 is zero of PMOS M2 is zero

iiseu seu ((tt33) = ) = IIDSDS of M1of M1

Use, Use, VVaa((tt) = VDD-|) = VDD-|VVTPTP| |

at at t t = = tt3 3 as as initial conditioninitial condition

To calculate To calculate tt33, ignore , ignore in in iiseuseu((tt) ) is 3-4 times larger than is 3-4 times larger than

ee-t/-t/ around around tt33 will be close to 0 will be close to 0

VDD-|VTP|

t3

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Expression for Expression for tt2 2 : Case 1: Case 1 Model Model iiseuseu((tt) by a straight line for ) by a straight line for tt > >tt3 3 between between

((IIDSDSavgavg,,tt33) and (0, ) and (0, t*t*))

TBD what is ids avgTBD what is ids avg Obtain Obtain t*t* by equating charge deposited by by equating charge deposited by iiseuseu((tt)) and the and the

above straight line model for above straight line model for tt > >tt33

Integrate INV1 output node diff. equation (Eq. 1)Integrate INV1 output node diff. equation (Eq. 1) Initial condition: Initial condition: VVaa((tt) = VDD-|) = VDD-|VVTPTP| for | for t t = = tt33

Substitute Substitute VVaa((tt) = 0.5*VDD for ) = 0.5*VDD for tt = = tt2 2 and solve for and solve for tt22

tt22a1 a1 is the initial guess for is the initial guess for tt22

Integrate Eq. 1 with Integrate Eq. 1 with IIDSDSVaVa = = IIDSDS

VDD+|VTP|VDD+|VTP| and line mode for and line mode for iiseuseu((tt) ) Substitute Substitute VVaa((tt) = 0.5*VDD for ) = 0.5*VDD for tt = = tt22

a1a1 and solve for and solve for tt22a1a1

Closed form exp. of Closed form exp. of tt22a1 a1 isis

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In this case also, In this case also, VVaa((tt33) = VDD-|) = VDD-|VVTPTP|| Integrate INV1 output node diff. equation (Eq. 1)Integrate INV1 output node diff. equation (Eq. 1)

Initial condition: Initial condition: VVaa((tt) = VDD-|) = VDD-|VVTPTP| for | for t t = = tt33

Use original expressions for Use original expressions for iiseuseu((tt) and ) and IIDSDSVaVa

Substitute Substitute VVaa((tt) = 0.5*VDD for ) = 0.5*VDD for tt = = tt22

Expand around initial guess Expand around initial guess tt22a2a2 for for tt2 2 and solve for and solve for tt22

Calculate Calculate tt22a2a2 by solving equation by solving equation iiseuseu((tt22

a2a2)= )= IIDSDSVDD/2VDD/2

tt22a2 a2 > T> Tseuseu

max max (Time when (Time when iiseuseu((tt) reaches its maximum value)) reaches its maximum value)

Ignore Ignore ee-t/-t/term interm in iiseuseu((tt) )

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In this case, only M1 conductsIn this case, only M1 conducts Substitute Substitute VVaa((tt) = 0.5*VDD for ) = 0.5*VDD for tt = = tt2 2 in Eq. 2 in Eq. 2

VVaa((tt) equation as shown before) equation as shown before Solve for Solve for tt22 after e after expanding around initial guess xpanding around initial guess tt22

a2a2 for for tt22

where where

Now we can calculate the pulse width as Now we can calculate the pulse width as tt22 - - tt11

Documents

1 A Fast, Analytical Estimator for the SEU-induced Pulse Width in Combinational Designs By: Rajesh Garg Charu Nagpal Sunil P. Khatri Department of Electrical