1 Asynchronous Bit-stream Compression (ABC) IEEE 2006 ABC Asynchronous Bit-stream Compression Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar Technion

1 Asynchronous Bit-stream Compression (ABC) IEEE 2006

ABC

Asynchronous Bit-stream Compression

Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar

Technion – Israel Institute of Technology

MATRICS Research Group, Electrical Engineering DepartmentTechnion – Israel Institute of Technology

Haifa, Israel

MATRICSResearch

Group


Background

&

Motivation


Synchronous Serial Link

Fast Clock generation is problematic Sensitive to timing uncertainty on chip


Asynchronous Serial Link

Fast operation No need for clock Insensitive to timing uncertainty


Motivation

solution Compression

Bit-stream CompressionAsynchronous

(ABC)

Limited Bandwidth


ABC Concept


Data 0 1 0 1 1 0 0 1 0 1 1 1

0 1 0 1 1 0 0 1 0 1 1 1

0 0 0 0 1 0 1 0 0 0 1 0

S

PLEDR

Asynchronous Signaling

Level Encoded Dual Rail

• Each bit on two wires• One wire (S) is the state (0, 1)• The other wire (P) helps with

phase• To change from one value to

the next:– If different value, toggle S– If same value, toggle P

• Only one wire toggles • No need for Clock!

00 01

10 11

xS xP

0

1

0 1 0

LEDR

1


Data 0 1 0 1 1 0 0 1 0 1 1 1

0 1 0 1 1 0 0 1 0 1 1 1

0 0 0 0 1 0 1 0 0 0 1 0

S

PLEDR

ABC Concept

Level Encoded Dual Rail

• Each bit on two wires• One wire (S) is the state (0, 1)• The other wire (P) helps with

phase• To change from one value to

the next:– If different value, toggle S– If same value, toggle P

• Only one wire toggles • No need for Clock!

00 01

10 11

xS xP

0

1

0 1 0

LEDR

1

What if…both signals would toggle?

ABC

00 01

10 11

xS xP

0

1

1 0 1 0


ABC Concept

Asynchronous Bit-stream Compression

• Identify a sequence of identical bits• Mark the beginning of the sequence

by one of the ABC transitions• Transmit the length of the sequence• Mark the end of the encoding by one

of the ABC transitions.

ABC

00 01

10 11

xS xP

0

1

1 0 1 0

The new transitions can be used for:


Data 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0

0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0

0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1

S

P

sequence

1

1

0

1

1 1 0

0 1 1

ticks saved

LEDR

ABC

00 01

10 11

xS xP

0

1

1 0 1 0

0 1 0 1 1 0 0 1 0

0 0 0 0 1 0 1 0 0

S

PABC 0 1 1

1 1 0

1

0

Example of ABC Savings

Beginning of compression is marked by ABC transition

The length of the sequence is encoded and transmittedThe end of the compression is marked by ABC transition

Transmission continues in regular LEDR mode

Transmission starts in regular LEDR mode


ABC Architecture


ABC Transmitter16 XORs

Sequence detector

Sequence detector

Sequence registers

Sequence stapler

Dual -Railencoder

data

phase input

321

Com

pres

sion

ena

ble

Sequ

ence

leng

th

32 - 32 - bit register

16 XORs

Sequence detector

Sequence detector

Mux

Dual -Railencoder

data

phase input

32 32 1

inde

x

8 X

OR

s8

XO

Rs

Controller


ABC Transmitter

16 XORs

Sequence detector

Sequence detector

Sequence registers

Sequence stapler

Dual -Railencoder

data

phase input

321

Com

pres

sion

ena

ble

Seq

uenc

e le

ngth


16 XORs

Sequence detector

Sequence detector

Mux

Dual -Railencoder

data

phase input

32 32 1

inde

x

8 X

OR

s8

XO

Rs

Controller

Sequence Detectors

Scan Windows

• Eight 2-bit XORs• XORs compare sequent bits

Sequence Detectors

• Identify sequences• Store the indices and lengths in sequence registers


ABC Transmitter

16 XORs

Sequence detector

Sequence detector

Sequence registers

Sequence stapler

Dual -Railencoder

data

phase input

321

Com

pres

sion

ena

ble

Seq

uenc

e le

ngth


16 XORs

Sequence detector

Sequence detector

Mux

Dual -Railencoder

data

phase input

32 32 1

inde

x

8 X

OR

s8

XO

Rs

Controller

Controller

Sequence Stapler

• Combines sequences• Produce final indices

Controller

• Signals when compression starts and ends• Transmits the sequence length • Moves the pointer of MUX to next bit after the sequence


ABC Transmitter

16 XORs

Sequence detector

Sequence detector

Sequence registers

Sequence stapler

Dual -Railencoder

data

phase input

321

Com

pres

sion

ena

ble

Seq

uenc

e le

ngth


16 XORs

Sequence detector

Sequence detector

Mux

Dual -Railencoder

data

phase input

32 32 1

inde

x

8 X

OR

s8

XO

Rs

Controller

ABC State Machine

LEDR mode

• Standard protocol• One signal toggles each time

ABC mode

• Compression performed• ABC activated by Controller• ABC transitions symbolize the start and the end of compression


ABC Receiver

Clk generator

Register

Enablingdecoder

en

en

Data FSM

Phasecompression

Comp_till

Comp_from

Com

pres

sion

sta

rt

clk

clk


ABC Receiver

Clock Generator

• Translates the transitions in S and P signals into clock pulses.

• Synchronizes the data storage in the register, controls the FSM.

• Identify the ABC transitions used for compression beginning.

• Toggles the input to FSM when ABC starts, switching to a different operation mode.

Clock generator

Register

Enablingdecoder

en

en

PhaseReceiver

FSM

Statecompression

Comp_till

Comp_from

Com

pres

sion

sta

rt

clk

clk

Data


ABC Receiver

Enabling Decoder

• Converts the data from serial to parallel.

• Provides enable signals to all cells for data storage

• In LEDR only one cell is enabled in every cycle

• In ABC multiple cells are enabled according to from and till indices.

• All the cells in ABC get the same value in one cycle - fast storage

Clock generator

Register

Enablingdecoder

en

en

PhaseReceiver

FSM

Statecompression

Comp_till

Comp_from

Com

pres

sion

sta

rt

clk

clk

Data


COUNT

COMP_WRITE

Comp_startCOMP_DECODE

ABC Receiver

Count mode• With each clock an internal

counter is increased by one. • The counter controls the enabling

decoder.

Comp_Decode mode• Activated when the length is received• Creates the from and till signals for Enabling Decoder• Returns to Count at next clock

Comp_Decode mode• Activated when ABC identified • Stable while the sequence length

code is received

Receiver FSM


Design Considerations

Trade-offs

Add a register to contain two packets.

Detect sequences in one packet while transmitting the other packet.

+ Maximal throughput

- Increased area and power

Delaying the transmission by 8 clocks.

Allow the scanning of all the bits and detection of the sequences.

+ No additional register is needed

- Increased transmission time

Transmit the first 8 bits without ABC.

Scan and detect sequences in the remaining 24 bits.

+ Reduced latency, area and power - Reduced ABC compression efficiency

Alternative

our architecture


Results


ABC in Random Packets

0

100

200

300

400

500

600

700

1009080706050403020101

packet #

Pa

ck

et

tra

ns

mis

sio

n t

ime

[n

se

c]

• ABC system - transmitter, receiver and 32-bit registers - was designed using VHDL • Transmission time evaluation of the uncompressed packet was 655ns• For maximal compression rate, the transmission time was reduced by 55% to 295ns

Simulation of ABC with a series of 100 random packets with various number and lengths of sequences


Image Transmission by ABC

Image(a)(b)(c)

Image size [kb]25106.5

TX original [ms]0.510.200.13

TX by ABC [ms]0.470.130.06

TX reduction [%]93654

Images with various differentiation were used for ABC effectiveness evaluation


Summary

•Asynchronous Bit-stream Compression proposed

•ABC targets improvement of BW utilization

•Significant saving in transmission time and power

•ABC interfaces were implemented and simulated

•Number of transitions was reduced by up to 54%


Questions?

00 01

10 11

xS xP

0

1

0 1 0

LEDR

1

ABC

00 01

10 11

xS xP

0

1

1 0 1 0

Documents

1 Asynchronous Bit-stream Compression (ABC) IEEE 2006 ABC Asynchronous Bit-stream Compression Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar Technion