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1 19 Apr 2023
Electromagnetic compatibility of Integrated CircuitsINSA Toulouse - France
September 2013
www.ic-emc.org
www.alexandre-boyer.fr > Enseignement
Etienne SICARDINSA/DGEIUniversity of Toulouse31077 Toulouse - [email protected]
Alexandre BOYERINSA/DGEIUniversity of Toulouse31077 Toulouse - [email protected]
2 19 Apr 2023
Objectives
Through lectures (16 H) Understand parasitic emission mechanisms Introduce parasitic emission reduction strategies Give an overview of emission and susceptibility measurement
standards Power Decoupling Network modelling Basis of conducted and radiated emission modelling Basis of immunity modelling Understand the role of decoupling at printed-circuit-board level Acquire basic knowledge of design for improved EMC at PCB and IC
level
Illustrate basic concepts through simulation (10 H) IC modeling case study using DSPIC (10 H)
EMC of ICsAn overview
Outlines
Electromagnetic interference What is EMC EMC at IC level Origin of parasitic emission Trends towards higher emission Origin on susceptibility Emission issues Susceptibility issues Standardization issues Conclusion
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5
EMI ISSUES IN WIRELESS DEVICES
Numerous interference cases reported over the ISM band 2400 – 2483.5 MHz.
From Cisco, « 20 Myths of WiFi Interference », White Paper, 2008:
• “Interference contributes to 50 % of the problems on the customer’s Wi-Fi network. “
• “In a recent survey of 300 of their customers, a major Wi-Fi tools provider reported that
“troubleshooting interference won ‘top honors’ as the biggest challenge in managing a
Wi-Fi network.””
• “67 percent of all residential Wi-Fi problems are linked to interfering devices, such as
cordless phones, baby monitors, and microwave ovens.”
• “At 8m, a microwave oven degrades data throughput by 64%.”
Electromagnetic Interference
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« The ability of a component, equipment or system to operate satisfyingly in a given electromagnetic environment, without introducing any harmful electromagnetic disturbances to all systems placed in this environment. »
Essential constraint to ensure functional safety of electronic or electrical applications
Guarantee the simultaneous operation of every electrical or electronic equipment in a given electromagnetic environment
Reduce both the parasitic electromagnetic emission and the sensitivity or susceptibility to electromagnetic interferences.
What is EMC ?
DEFINITION
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100 mm10 mm
EMC at IC Level
ZOOM AT DEVICES
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Integrated
Circuits…
© Intel Xeon
1 µm
100 nm
1 V100 µA
10µm1mm
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EMC at IC Level
WHY EMC OF IC ?
• Until mid 90’s, IC designers had no consideration about EMC problems in their design..
• Starting 1996, automotive customers started to select ICs on EMC criteria
• Starting 2005, mobile industry required EMC in System in package
• Massive 3D integration will require careful EMC design
Technology
Complexity
Packaging
2004
130nm
100M
Core+ DSP
1 Mb Mem
Core+ DSP
1 Mb Mem
Embedded blocks
2006
90nm
250M
Core DSPs
10 Mb Mem
Core DSPs
10 Mb Mem
2008
45nm
500M
Dual coreDual DSP
RFGraphic Process.100 Mb Mem
Sensors
Dual coreDual DSP
RFGraphic Process.100 Mb Mem
Sensors
2010
32nm
2G
Quad CoreQuad DSP
3D Image ProcCrypto
processorReconf FPGA,
Multi RF1 Gb Memories Multi-sensors
Quad CoreQuad DSP
3D Image ProcCrypto
processorReconf FPGA,
Multi RF1 Gb Memories Multi-sensors
22nm
2012
7G
INCREASED INTEGRATED CIRCUIT COMPLEXITY
5nm
150 G
2020
??
EMC at IC Level
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Emission of EM wavesSusceptibility to EM waves
TWO MAIN CONCEPTS
Personnal entrainments
Safety systems
interferences
Hardware faultSoftware failureFunction Loss
Components
EquipementsCarbon airplane
Boards
Radar
EMC at IC Level
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Susceptibility
Chip
Chip
EmissionPCB
PCB System
Components
Components
System
Integrated circuits are the origin of parasitic emission and susceptibility to RF disturbances in electronic systems
Noisy IC
Sensitive IC
Interferences
THE ROLE OF ICS AS PERTURBATION SOURCE AND VICTIM
Radiation
Coupling
EMC at IC Level
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VDD
VSS
Output capa
Vin
Origin of Parasitic Emission
BASIC MECHANISMS FOR CURRENT SWITCHING
IDD
ISS
Switching current
Voltage Time
Time
Question: waveform, amplitude?CMOS inverter exempleCMOS inverter exemple
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Basic > interconnects > GateSwitching.schBasic > interconnects > GateSwitching.sch
Origin of Parasitic Emission
CMOS INVERTER IN IC-EMC
Switching current
Voltage Time
Time
Waveforms strongly depend on load
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Origin of Parasitic Emission
STRONGER SWITCHING CURRENT:
50ps
i(t)
Time
Switching gatesInternal
switching current
Vdd
Vss
i(t)
Main transient current sources: Clock-driven blocks, synchronized logic Memory read/write/refresh I/O switching
Very large Simultaneous Switching Current
i(t)
Time
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Origin of Parasitic Emission
EXAMPLE: EVALUATION OF DSPIC SWITCHING CURRENT
• ____ VDD, ___ technology• ____ mA / gate in ____ ps• ____ gates in ____ Bit Micro => ____ A• ____ % switching activity => ____ A• ____ % current peak spread (non synchronous switching) •____ in ____ ps
____
Current (A)
____ ns
time
Vdd
Vss
i(t)Current / gate
Current (A)
____ nstime
Current / Ic
____
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M. Ramdain, E. Sicard, “The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future”, IEEE Trans.
EMC, VOL. 51, NO. 1, Feb. 2009
Origin of Parasitic Emission
REFERENCES: CURRENT, DECAP VS TECHNOLOGY
Origin of Parasitic Emission
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Vss
Vdd
_V _V
Wires act as antennas
V(t)
Time
mmnHL /_ mmnHL /_
Origin of Parasitic Emission
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WIRES+CURRENT = NOISE DSPIC33F noise measurement with active probe on X10
Activation of the core by a 40 MHz internal PLL
Synchronous ADDR0..15 bus switching 0x0000, 0xFFFF
DSPIC_VDD_VofT.tranDSPIC_VDD_VofT.tran
Origin of Parasitic Emission
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WIRES RADIATE
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Stronger di/dt Stronger di/dt
Increase parasitic noiseIncrease parasitic noise
Time
New process
VoltOld process
WHY TECHNOLOGY SCALE DOWN MAKES THINGS WORSE ?
• Current level keeps almost constant but:
• Faster current switching
• Current level keeps almost constant but:
• Faster current switching
Time
Current
di/dt
New processOld process
Emission Issues
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Susceptibility issues
100 mV
margin
5.0
3.3
2.5
1.8
0.5µ 0.35µ 0.18µ 90n 65n
Technology
1.0
Supply (V)
1.2
45n
I/O supply
Core supply
32n
DECREASED NOISE MARGIN IN ICS
22n 17n130n
500 mV
margin
Adapted from ITRS roadmap for semiconductors, 2011
Thunderstorm impact
UNINTENTIONAL ELECTROMAGNETIC SOURCES
TV UHF
Radars
2-4G BS
1W
Frequency
1MW
1KW
1GW Weather Radar
3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 300 GHz
Power
1mW
HF VHF UHF SHF xHF THF
3G
TV VHF
2G4G
• Fields radiated
by electronic devices
• Continuous waves &
pulsed waves
25m 25mm0.25m 2.5mm2.5m /4 (ideal antenna)0.25mm
Susceptibility Issues
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EMC Level (dB)
-40
-30
-20
-10
0
10
20
30
40
50
1 10 100 1000
Sum of perturbations
Susceptibility level
High risk of interference
Safe interference
margin
Unsafe margin
Frequency (MHz)
Susceptibility Issues
SYSTEM-ON-CHIP, 3D STACKING: DANGER
Conclusion
EMI reported in all kinds of devices IC involved in many EMI problems IC technology evolution towards
higher complexity On-chip switching currents in the
10-100 A range ICs are good antennas in the GHz
range Increased switching noise Increased emission issues Reduced noise margins System-on-chips, systems-in-
package rise new EMC issues
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