1. CMOS Scaling

Dmitri Nikonov

Thanks to Kelin Kuhn

Dmitri.e.nikonov@intel.com

Nikonov 1. CMOS

Beyond CMOS computing

1

Outline

Moore’s law = scaling

Performance improvement with scaling

Latest: tri-gate transistors

Fundamental limits to scaling

2 Nikonov 1. CMOS

Moore’s Law

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Transistor size becoming smaller

Moore’s Law

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Gordon Moore becoming wiser

Scaling Falsifies Predictions

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IEDM Plenary Session 1980 (Broers)

How Far Scaling Went

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1980 SRAM Cell: 1700 um2 22nm SRAM Cell: 0.092 um2

Small enough that a 2011 22nm SRAM cell is dwarfed by a 1980 SRAM cell CONTACT

10000X

K. Kuhn, MIT invited seminar (MTL), 45nm High-k + Metal Gate Logic Technology, 5-19-08 (images from archives Mark Bohr, 2007)

Metal Interconnects

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9 levels of metal

Contacted Gate Pitch

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Transistor gate pitch continues to scale 0.7x every 2 years.

Proves to be 4*F. F is the label for process generations.

M. Bohr, ISCC, 2009.

Economics of Moore’s Law

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“Doubling of number of transistors per chip every 2 years”.

Lowers cost per transistor.

Self-fulfilling prophesy.

Original paper: G.E. Moore, Electronics 19, 114 (1965)

103

104

105

106

107

108

109

1010

’70 ’80 ’90 ’00

10

10-6

10-5

10-4

10-3

10-2

10-1

10-7

$ per

Transistor

As the

number of

transistors

goes UP

Transistors

per Chip

’10

Price per

transistor

goes DOWN

100

Year

Classic Scaling

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R. Dennard, IEEE JSSC, 1974

Device or Circuit Parameter Scaling Factor

Device dimension tox, L, W 1/κ

Doping concentration Na κ

Voltage V 1/κ

Current I 1/κ

Capacitance εA/t 1/κ

Delay time/circuit VC/I 1/κ

Power dissipation/circuit VI 1/κ2

Power density VI/A 1

Classical MOSFET scaling was first described by Dennard in 1974

Dennard, IEEE JSSC, 1974

Process Evolution

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Inflection in Scaling

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THEN

Scaling drove down cost

Scaling drove performance

Performance constrained

Active power dominates

Independent design-process

NOW

Scaling drives down cost

Materials drive performance

Power constrained

Standby power dominates

Collaborative design-process

65nm 45nm 32nm

Images from Bai, Mistry, Natarajan, Auth IEDM/VLSI, 2004/7/8/12 (see course required reading)

22nm

Short Channel Effects (SCE)

Degradation of short channel effects

V2 > V1

Decreasing L

ID

VG

~DIBL (mV/V)

~ 1 / Subthreshold

Slope (mV/dec)

13

Gate Voltage (V)

“On”

Current

“Off”

Current

Channel

Current (normalized)

Basic ID-VG

Poor

SCE

Reduced Threshold

Voltage

14

Good

SCE

Electrostatics Benefits

Threshold Voltage

9

~DIBL (mV/V)

~Subthreshold

Slope (mV/dec)

~VTlin

http://en.wikipedia.org/wiki/Threshold_voltage

On Current, Off Current

9

IDsat

Ioff

~DIBL (mV/V)

~Subthreshold

Slope (mV/dec)

~VTlin

IDsat IDsat

Idsat (=Ion)

Io

ff

Performance from Scaling

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Natarajan, Intel, IEDM, 2008

Where Performance Comes From

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K.J. Kuhn, Moore's Law past 32nm: Future Challenges in Device Scaling, Solid State Devices and materials conference, plenary, October 2009

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

90 65 45 32 22

PM

OS

Ieff

@ 0

.7V

(No

rmal

ize

d)

Generation (nm)

Tri-gate

HK-MG

Strain

Classic

Strain and High-k + metal gate are key enablers past the 90nm node

Intel Announced First Tri-Gate (2011)

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Close-Up on Tri-gate Transistors

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Nomenclature of Non-Planar Devices

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Where Non-Planar Can Go?

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Working With Atomic Dimensions

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International Technology Roadmap for Semiconductors

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Limits of Computing

Moving from fundamental limits given by the laws of

physics to practical limitations. These limits tend to

be broken. Fundamental limits

Material limits

Device limits

14nm inverter

neuron

Interconnect Limits Transistor Limits

Meindl, Proc. IEEE 83, 619 (1995).

Meindl, Chen, Davis, Science 293, 2044 (2001).

Meindl, J. Vac. Sci. Technol. B 14(1), 192 (1996).

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Equations for Fundamental Limits

Meindl, Proc. IEEE 83, 619 (1995).

Thermodynamics: if energy is less

than thermal – bit errors

4sw

E kT

Quantum Mechanics: energy time uncertainty

sw swE t h

Relativity: Signal no faster than the

speed of light

0/L c

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Better Fundamental Limits

* Zhirnov et al., Proc. IEEE 91, 1934 (2003) and Nikonov and Bourianoff, JSNM 21, 497 (2008).

2 2

2

3

2sw

Ema

3sw

E kT

sw swE t

3.8nma 27fssw

t 20

1.2 10 J 78meVsw

E

a a a

a

a

source gate drain

electron

OFF

ON

electron

Thermodynamic limit on bit error ratio

Higher energy = faster switching

Energy of electron in a transistor

is limited by quantum confinement

Gate raised = confined in the source.

Gate lowered = can travel to drain.

Solving equations together gives

limits

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MOSFET Scales Towards the Limit

* Data courtesy of Robert Chau (Intel)

Current CMOS device scaling close to the ideal limits

0.01

0.1

1

10

100

0.001 0.01 0.1 1LGATE (mm)

Gate

Delay

(ps)

0.000001

0.00001

0.0001

0.001

0.01

0.1

1

10

100

0.001 0.01 0.1 1

LGATE (mm)

Switching

Energy

(fJ)

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How long is left for Moore’s law

Intel’s generation to HVM

2013 14nm

2017 7nm

2021 3.5nm

ITRS start of production

2012 32nm

2018 15nm

2024 7.5nm

2030 3.8nm

Scaling might end between 2021 and 2030

But it is NOT the end of Moore’s law:

better architectures, 3D circuits.

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Summary

Moore’s law = 0.7 size every 2 years

Despite trends, Intel developers manage to improve performance

Tri-gate transistors = major advance

Fundamental laws limit size scaling to ~4nm

30 Nikonov 1. CMOS