Upload
malcolm-thompson
View
212
Download
0
Embed Size (px)
Citation preview
1
Delay Estimation
• Most digital designs have multiple data paths some of which are not critical.
• The critical path is defined as the path the offers the worst case delay.
• Several factors affect a design’s delay analysis. These could be at:– Architectural/micro-
architectural– Logical– Circuit and– Layout levels.
• Delay estimation is essential in the design of critical paths.
• Some parameters of note in delay estimation include:– Rise time– Fall time– Average delay (edge rate).– Propagation delay– Contamination delay
• When input changes the output maintains its old value for a duration called the contamination time.
2
Delay Time and Gate Delays
• In most CMOS circuits the delay of a single gate is dominated by the rate at which the output node can be charged and discharged.
• The delay can be approximated by:
tdr = tr/2 and tdf = tf/2• The average delay for rising and
falling output transitions is:
tav = (tdf+tdr)/2 • The delay equations presented use
only first order MOS equations for the calculations of drain currents and thus do not account for second order effects.
• The delay of simple gates maybe approximated by constructing an equivalent inverter. WHY?
• Consider a 3 input NOR gate with Wp = Wn for all transistors:
– When there is a path in the pull-up network from the output to VDD the effective gain factor of the series p-type transistors is:
321
1111
ppp
eff
βββ
β++
=
3
Gate Delays
• For the pull-down network only one n-type transistor need to be on in order for us to have a path from the output node to ground.
βeff =βn and this gain factor is improved by a factor of three if all the n-type devices conduct simultaneously.
• For the NOR gate example we can thus estimate the rise and fall times as follows:
• The gain factor of the three series p-type transistors is given by:
• The delay through this series connection is therefore given by:
• If all three parallel n-type devices are conducting we have that:
n
Lf
DDp
Lr
Ckt
V
Ckt
ββ == and
3
3p
series
ββ =
DDp
Lseries
V
Ck
3
βτ =
3f
f
tt =
4
RC Delays
• Transistors have complex non-linear current-voltage characteristics, but can be fairly approximated as a switch in series with a resistor.
• The effective resistance is chosen to match the amount of current delivered by the transistor.
• The transistor gates and the diffusion nodes have capacitance.
• An nMOS with and effective width of one unit has resistance R. The unit-width pMOS has higher resistance that depends on the mobility of holes and we will say 2R.
• If we double the unit-width of the pMOS so that it delivers the same current as a unit-width nMOS we end up with resistance R for the pMOS.
• Parallel and series transistors combine like resistors.
5
Effective Capacitance and Resistance
• Wider transistors have lower resistance.
• When multiple transistors are in series their resistance is the sum of each individual resistance.
• When transistors are in parallel and are ON the resistance is lowered.
• The capacitance consists of gate capacitance (Cg) and source/drain capacitance (Cdiff)
• We can approximate the capacitances to be Cg=Cdiff=C.
• Cg and Cdiff are proportional to the transistor width.
• The contacted diffusion has higher capacitance than the uncontacted diffusion. A 3-input NAND gate has 2 uncontacted diffusion terminals for the series devices and a single contact for the parallel pMOS devices.
6
RC Delay Model
• Our model will assume minimum device sizes for delay estimation– A minimum sized nMOS
has resistance R– Recall that in general the
mobility of electrons is twice that of holes.
– We have thus designed pMOS devices to have twice the widths of nMOS devices to attain symmetric rise and fall times.
– This fact allows us to estimate the resistance of a pMOS to be 2R.
• Transistors with increased widths have reduced resistance i.e. increase a minimum width transistor by k the resistance reduces to R/k.
• A pMOS device of double width therefore has a resistance value of 2R/2 = R.
• Parallel and series transistors combine just like resistors in parallel and resistors in series.
7
Delay Estimation (RC Models)
8
The Elmore Delay Model
• Transistors that are conducting must be viewed as resistors.
• The Elmore delay estimates the delay of an RC ladder as the sum over each node in the ladder resistance Rn-i between that node and the source multiplied by C the capacitance on the node.
VDD
VinR3R1 R2 RN
C2 C3C1 CN
9
AND Gate Intrinsic Capacitance
10
Two Input NAND Gate
11
CMOS-Gate Transistor Sizing
• It has been shown that to have symmetric switching in an inverter we need to make the width of the p-type device (Wp) at least 2->3 times that of the n-type device (Wn).
• This approach increases the area occupied by the p-type devices and dynamic power dissipation.
• Some structures can be cascaded to use minimum or equal sized devices without compromising the switching response.
• If Wp = 2Wn the delay response for an inverter pair:
• The above expression can be compared to one for equal sized inverter devices. The inverter pair delay becomes:
eqpairinv
eqeqpairinv
risefallpairinv
RCt
CR
CRt
ttt
6
32
23
_
_
_
∝
+∝
+∝
eqpairinv
eqeqpairinv
risefallpairinv
RCt
CRCRt
ttt
6
222
_
_
_
∝
+∝
+∝
12
Stage Ratio
• To drive large load capacitances such as long buses, I/O buffers, pads and off chip capacitive loads a chain of inverters can be used.
• With this configuration each successive gate is made large than the previous one until the last inverter in the chain can drive the large load within the required time.
• To maintain shorter delays between input and output, minimal area and maintain power dissipation to a minimum as well we can use the stage ratio approach (increase each stage)
• A cascade of n inverters with stage ratio a driving a load capacitance CL, with inverter 1 having minimum-sized devices, driving inverter 2 which is a times the size of inverter 1.
• Inverter 2 drives inverter 3 which is a2 the size of inverter 1.
• The delay through each stage is atd with td being the delay of the minimum sized inverter.
• The delay through n stages is natd
• If CL/Cg = R, then an = R, where Cg is the gate capacitance of the minimum sized inverter.