1

Designing for 65nm and BeyondDesigning for 65nm and Beyond

Where’s The Revolution ?!?Where’s The Revolution ?!?

Greg Spirakis Absolutely, positively not working for Intel (or anyone else)

EDP 2005

2

The Move To SOC Designs Was A Failure

The Move To SOC Designs Was A Failure

Source*: Collett International Research and Synopsys

11s

tst S

ilic

on

Su

cces

s S

ilic

on

Su

cces

s

1999 2002 2004

39%44%48%

33%

Myth of Hard IP Reuse + Reliance on 20 Year Old Design Flow

Failure

3

Closer LookCloser Look

2,000 engineer years to write 25M lines of RTL and 1 Trillion

simulation vectors to verify

GatesGates1M 10M 100M

20

200

2000 E

ng

inee

r Y

ears

En

gin

eer

Yea

rs

19951995

20012001

20072007 1,000B

10B

100M

Sim

ula

tio

n V

ecto

rsS

imu

lati

on

Vec

tors

And It’s Going to Get Worse

Source*: Synopsys

4

But Look Where We FocusDAC 2005 Session Summary

But Look Where We FocusDAC 2005 Session Summary

47 Paper Sessions (plus 8 panels)47 Paper Sessions (plus 8 panels)

9 Logic Design and Test9 Logic Design and Test Error Tolerant DesignError Tolerant Design Programmable ArchitecturesProgrammable Architectures SAT: Cool Algorithms and Hot Applications SAT: Cool Algorithms and Hot Applications Methods and Representations for Logic SynthesisMethods and Representations for Logic Synthesis Advances in SynthesisAdvances in Synthesis Advances in DFT Methods Advances in DFT Methods Testing for Process and Timing Related FaultsTesting for Process and Timing Related Faults New Directions in FPGA TechnologiesNew Directions in FPGA Technologies CAD for FPGACAD for FPGA

5 ESL5 ESL Tools and Methods for the Verification of Processors and Processor-Based Tools and Methods for the Verification of Processors and Processor-Based

Systems Systems Matlab(TM) -The Other Emerging System-Design LanguageMatlab(TM) -The Other Emerging System-Design Language Application Specific Architecture Design Tools Application Specific Architecture Design Tools Formally Verifying Your 10-Million Gate Design Formally Verifying Your 10-Million Gate Design Effective Formal Verification Using Word-level Reasoning, Bit-level Generality, Effective Formal Verification Using Word-level Reasoning, Bit-level Generality,

and Parallelismand Parallelism

75% Of Respins Due To Logic Problems

But…70% Of DAC Focused On

Everything Else

5

Highest Abstraction LevelHighest Abstraction LevelProduct family manuals & docsProduct family manuals & docs

What’s Wrong ?What’s Wrong ?

Layout polygonsLayout polygons

Schematic transistorsSchematic transistors

Schematic gatesSchematic gates

Library gatesLibrary gates

Structured RTLStructured RTL

Transistor physicsTransistor physics

Synthesizable RTLSynthesizable RTL

ArchitectureArchitecture Performance ModelPerformance ModelAbstract of “what” Abstract of “what” you will buildyou will build

Abstract of “what” Abstract of “what” you will buildyou will build

Architectural FamilyArchitectural FamilyUltimately, “what” you wantUltimately, “what” you wantUltimately, “what” you wantUltimately, “what” you want

Layout/Schematic Layout/Schematic netlist comparenetlist compare

Abstraction limitedAbstraction limitedby logic equivalenceby logic equivalence

capabilitiescapabilities

Formal Logic EquivalenceFormal Logic Equivalence

Design rule checkingDesign rule checking

Less details Less details allowing more allowing more

designed designed functionalityfunctionality

Abstracts of “how” Abstracts of “how” you built ityou built it

Abstracts of “how” Abstracts of “how” you built ityou built it

Lowest Abstraction LevelLowest Abstraction Level

We need a dramatic increase in We need a dramatic increase in design abstraction while design abstraction while

maintaining the link to the maintaining the link to the physical implementationphysical implementation

Need a new design Need a new design paradigmparadigm to further to further

raise the level of raise the level of abstraction!!!abstraction!!!

Need a new design Need a new design paradigmparadigm to further to further

raise the level of raise the level of abstraction!!!abstraction!!!

6

The RevolutionThe Revolution

Structured methodology that limits Structured methodology that limits the space of exploration, yet the space of exploration, yet achieves good results in the fixed achieves good results in the fixed time constraints of the design;time constraints of the design;

A formal mechanism for identifying A formal mechanism for identifying the most critical hand-off points in the most critical hand-off points in the design chain;the design chain;

A method for design re-use at all A method for design re-use at all abstraction levels based on abstraction levels based on assembling and configuring platform assembling and configuring platform components in a rapid and reliable components in a rapid and reliable fashion;fashion;

An intellectual framework for the An intellectual framework for the complete electronic design process.complete electronic design process.

A. Sangiovanni-Vincentelli, DAC June 04

Platform Based Design

Raise the level of abstraction by Raise the level of abstraction by creating a high level model (HLM)creating a high level model (HLM)

Successively refine the design Successively refine the design ensuring that each refinement is ensuring that each refinement is equivalent to the previous oneequivalent to the previous one

Tightly integrate logic and physical Tightly integrate logic and physical design domainsdesign domains

Enable extensive use of a repository Enable extensive use of a repository of trusted design transformations of trusted design transformations generated during the design process generated during the design process

Integrated Design and Verification

G. Spirakis, DATE Feb 04

7

Platform-based Designhttp://www.gigascale.org/pubs/141/platformv7eetimes.pdf

Platform-based Designhttp://www.gigascale.org/pubs/141/platformv7eetimes.pdf

Platform: An abstraction layer in the design flow that facilitates a number of possible refinements into a subsequent abstraction layer (platform) in the design flow.

Platform Stack: Every pair of platforms, the tools and methods that are used to map the upper layer of abstraction into the lower level one. A. Sangiovanni-Vincentelli

Top-Down:Top-Down:

Define a set of abstraction layersDefine a set of abstraction layers

From specifications at a given level, From specifications at a given level, select a solution (controls, components) select a solution (controls, components) in terms of components (Platforms) of in terms of components (Platforms) of the following layer and propagate the following layer and propagate constraintsconstraints

Bottom-Up:Bottom-Up:

Platform components (e.g., micro-Platform components (e.g., micro-controller, RTOS, communication controller, RTOS, communication primitives) at a given level are primitives) at a given level are abstracted to a higher level by their abstracted to a higher level by their functionality and a set of parameters functionality and a set of parameters that help guiding the solution selection that help guiding the solution selection process. The selection process is process. The selection process is equivalent to a covering problem if a equivalent to a covering problem if a common semantic domain is used.common semantic domain is used.

8

Integrated Design and VerificationIntegrated Design and VerificationIntegrated Design and VerificationIntegrated Design and Verification

Raise the level of abstraction by creating a high Raise the level of abstraction by creating a high level model (HLM)level model (HLM)

Successively refine the design ensuring that each Successively refine the design ensuring that each refinement is equivalent to the previous onerefinement is equivalent to the previous one

Tightly integrate logic and physical design domainsTightly integrate logic and physical design domains

Enable extensive use of a repository of trusted Enable extensive use of a repository of trusted design transformations generated during the design design transformations generated during the design process process

Integrated Design & VerificationIntegrated Design & Verification

Ensure Final Implementation Maintains Equivalence To HLM While

Meeting Design Goals

9

A higher level A higher level expressive languageexpressive language

• Visualize the code• Ungroup/group, move logic to make simple optimizations

An ExampleAn Example

f L L L L L LValidation Target

HLM Code

Use cross domain Use cross domain visibility between visibility between

HLM and schematicHLM and schematicEquiv

Verify Verify transformation transformation

is correctis correct

fa L L L L L Lfb

10

RefineRefine the design the design • Replace some blocks with circuits from libReplace some blocks with circuits from lib• Create new circuits and replace blocksCreate new circuits and replace blocks• Synthesize other blocksSynthesize other blocks• Apply Apply trusted transformationstrusted transformations• Determine Determine feasibilityfeasibility

EquivEquiv

An Example Successive Refinement

An Example Successive Refinement

fa L L L L L Lfb

f L L L L L L

• Visualize the code• Ungroup/group, move logic to make simple

optimizations

Validation Target

HLM Code

Equiv

fc L L L L L Lfd fe ff

11

fa L L L L L LfbEquivEquiv

Validation Target

HLM Code

Equiv

• RefineRefine the design the design • Replace some blks with circuits from libReplace some blks with circuits from lib• Create new circuits and replace blocksCreate new circuits and replace blocks• Synthesize other blocksSynthesize other blocks• Apply Apply trusted transformationstrusted transformations• Determine Determine feasibilityfeasibility

f L L L L L L

• Visualize the code• Ungroup/group, move logic to make simple optimizations

fc L L L L L Lfd fe ff

An Example Further Design Refinement

An Example Further Design Refinement

fl Lfg L fh L fi L fj L fk L

ManyIterations

IterativelyIteratively, further refine the design , further refine the design • Replace some blocks with circuits from libReplace some blocks with circuits from lib• Create new circuits and replace blocksCreate new circuits and replace blocks• Synthesize other blocksSynthesize other blocks• Apply Apply trusted transformationstrusted transformations• Determine Determine feasibilityfeasibility

Equiv

Today’s NetlistToday’s Netlist

Final Netlist Final Netlist equivalent to HLM !!!equivalent to HLM !!!

12

Key Is To Keep Track Of Every StepKey Is To Keep Track Of Every Step

RefinementRefinementTransformationTransformation

Start with a small Start with a small block of the designblock of the design

Circuit Circuit LibLib UseUse

Becomes a “Becomes a “TrustedTrusted” ” TransformationTransformation

Transf. Transf. LibLib

AddAdd

Refine to Refine to next levelnext level

Formally Formally VerifyVerify

Document every design change (transformation)Document every design change (transformation)

Use cross-domain visibility to Use cross-domain visibility to estimateestimate

impact on other domainsimpact on other domains

AnalyzeAnalyze

13

AddAdd

Build And Use Design IP Repository Store Every New Circuit And Trusted Transformation

Build And Use Design IP Repository Store Every New Circuit And Trusted Transformation

X

X

X XX

Transf. Transf. LibLib

UseUse

Circuit Circuit LibLib

UseUse

AddAdd

X

Does not Does not meet timing !meet timing !

Does not Does not meet power !meet power !

Add to the Add to the circuit libcircuit lib

X

Does not Does not meet area !meet area !

Does not meet Does not meet testability !testability !

14

15

The RevolutionThe Revolution

Platform Based Design

Structured methodology that limits Structured methodology that limits the space of exploration, yet the space of exploration, yet achieves good results in the fixed achieves good results in the fixed time constraints of the design;time constraints of the design;

A formal mechanism for identifying A formal mechanism for identifying the most critical hand-off points in the most critical hand-off points in the design chain;the design chain;

A method for design re-use at all A method for design re-use at all abstraction levels based on abstraction levels based on assembling and configuring assembling and configuring platform components in a rapid and platform components in a rapid and reliable fashion;reliable fashion;

An intellectual framework for the An intellectual framework for the complete electronic design process.complete electronic design process.

Raise the level of abstraction by Raise the level of abstraction by creating a high level model (HLM)creating a high level model (HLM)

Successively refine the design Successively refine the design ensuring that each refinement is ensuring that each refinement is equivalent to the previous oneequivalent to the previous one

Tightly integrate logic and physical Tightly integrate logic and physical design domainsdesign domains

Enable extensive use of a repository Enable extensive use of a repository of trusted design transformations of trusted design transformations generated during the design process generated during the design process

Integrated Design and Verification

A. Sangiovanni-Vincentelli, DAC June 04 G. Spirakis, DATE Feb 04

TransformIntractable CAD Engineering Problem

IntoTractable SW Engineering Problem

16

Next Steps/Call to ActionNext Steps/Call to Action

New design flow based on Platform Based Design New design flow based on Platform Based Design and IDV concepts must be developedand IDV concepts must be developed

EDA industry must restructure its investment to EDA industry must restructure its investment to embrace the new paradigmembrace the new paradigm

Academia MUST lead this effort and make it THE Academia MUST lead this effort and make it THE design flow at all universitiesdesign flow at all universities

This is a Design Flow andSW Engineering problem

NOT a traditional EDA problem