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Model-Based Controller Design
1. Introduction
2. Direct synthesis method
3. Internal model control (IMC)
4. IMC derived PID tuning rules
5. Simulink example
Model-Based Control
PID controller tuning
» Restrict controller to PID form
» Seek “best” tuning parameters
» Can perform with FOPTD model if available
Model-based controller design
» Controller is not restricted to PID form
» Requires a process model that is used to
determine the controller form as well as the
tuning parameters
» Not restricted to FOPTD models
» Makes full use of available model
» Generates PID controllers for many model types
Direct Synthesis Method
Closed-loop transfer function for setpoint changes
Simplification of CLTF
pvcm
pvcm
sp GGGG
GGGK
Y
Y
1
c
c
sp
pvmmmGG
GG
Y
YGGKGKG
1
Control Objective
Rearrange CLTF
Desired setpoint response
» Gd is the desired CLTF
» The controller Gc depends explicitly on the
inverse of the process model G
» The equation for Gc is known as the control law
sp
sp
c
c
c
sp YY
YY
GG
GG
GG
Y
Y
1
1
1
d
dcd
dspsp G
G
GGG
Y
Y
Y
Y
1
1
Desired Closed-Loop Transfer Function
The desired CLTF Gd is specified such that:
» The resulting Gc has a single tuning parameter with an easily understood effect on closed-loop stability and performance
» Gc is implementable – does not require prediction and has the appropriate properness
Properness
» If n >= m, the controller is proper no derivative control
» If n = m-1, the controller is improper derivative control
» If n = m-2, the controller is improper requires second derivative of measured output (not desirable)
» Seek controllers that are proper or improper with n = m-1
01
1
1
01
1
1
)(
)()(
sss
sss
sD
sNsG
n
n
n
n
m
m
m
m
c
cc
Selecting the Desired CLTF
Common choice
» tc > 0 is the desired closed-loop time constant
» Gd is stable for all tc > 0
» Gd has a steady-state gain of unity ensuring
offset-free performance due to integral action
in Gc
» Closed-loop speed of response is determined
by tc; typical choice is tc = 0.5t
Other choices of Gd may be required to
ensure that Gc is implementable
sGG
sG
c
c
c
dtt
11
1
1
Simple Examples
First-order system
» This is a PI controller
Second-order system
» This is a PID controller
sKs
Ks
s
KsGG
sG
s
KG
I
c
ccc
c
c
d
tt
t
t
t
t
t
tt
11)11(
1111
1
1
1
ss
Ks
sKs
ss
KsGG
sG
ss
KG
D
I
c
ccc
c
c
d
tttt
tt
ttt
tt
t
tt
t
ttt
11
)(
11
)1)(1(111
1
1
)1)(1(
21
21
21
2121
21
Systems with Time Delays
Model representation:
Desired CLTF must include time delay
FOPTD model
d
d
d
s
d
s
d
dc
s
d
c
s
dG
G
GG
eG
eGG
G
GGeG
s
eG
1
1
1
1
1
1
1
*
*
*
*
*
t
sesGsG )()( *
sK
sKss
s
KGse
es
s
K
s
es
s
KG
G
GG
eGs
eGeG
s
KeG
I
c
cc
c
s
s
c
c
s
c
d
dc
s
d
c
s
d
ss
ttt
t
t
t
t
t
tt
t
tt
11
11
1111
1
11
11)1(
11
1
1
11*
*
**
Non-Minimum Phase Systems
Process Model
Zeros: N(s) = 0 » Systems with right-half plane zeros can exhibit
inverse response
» Such systems are said to be non-minimum phase
Direct synthesis controller
» Zeros of model become poles of controller
» Controller is unstable if model is non-minimum phase not acceptable
01
1
1
01
1
1
)(
)()(
asasasa
bsbsbsb
sD
sNsG
n
n
n
n
m
m
m
m
sN
D
sGG
cc
ctt
111
Internal Model Control
Applicable to both minimum-phase and non-minimum phase systems
Does not invert non-invertible elements: time delays and right-half plane zeros
IMC approach
» Factor model into invertible and non-invertible parts
» Design IMC controller using the IMC control structure
» Convert IMC controller into standard feedback controller
» Implement standard feedback controller as usual
IMC Structure
GG
GG
c
cc ~
1 *
*
DGGGYGYGG
DGGG
GGY
GGG
GGY
cspc
c
csp
c
c
)1(~
)~
(1
~1
)~
(1**
*
*
*
*
DGG
YGG
GGY
c
sp
c
c
1
1
1
IMC Design
Factor the process model
» contains any time delays and right-half plane
zeros, has unity gain and is an all-pass element
Construct the IMC controller
» f is the IMC filter, tc is the desired closed-loop
time constant and r is chosen to make G*c proper
Resulting closed-loop relation
GGG~~~
G~
r
c
cs
ffG
G)1(
1~1*
t
fGGfGG
GGY
Yc
sp
~1*
First-Order System
This is a PI controller
Same result as direct synthesis method
Two methods always yield same result when G+ = 1
sKs
K
s
K
s
s
K
s
s
K
GG
GG
s
s
Kf
GG
s
KGGG
sf
s
KG
I
c
c
c
c
c
cc
c
c
c
tt
t
t
tt
t
t
tt
t
t
tt
11)11(
11
111
1
11
1
1
111
11
1
1
1
*
*
*
Non-Minimum Phase Examples
Right-half plane zero
Time delay
4
4
1
)3)(2(
4
11
)3)(2(
14
1
1
4
4
1
1
)3)(2(
14
*
41
ss
ssf
GG
ss
s
G
GG
s
sG
ssf
ss
sG
c
13
1
4
151
15
4
1
113
1
1
1
15
4
15
4
*
2
2
s
sf
GG
sG
GG
s
seG
sf
s
s
ss
eG
c
s
s
Example: IMC Design
ss
ss
sss
ssG
ss
s
ss
ssss
ss
GG
GG
ss
ssf
GG
ss
s
G
GG
s
sG
ssf
ss
sG
C
c
cC
c
9
)3)(2(
)1(4)4)(1(
)3)(2(
)3)(2(
14
4
4
1
)3)(2(
4
11
4
4
1
)3)(2(
4
1
1
4
4
1
)3)(2(
4
11
)3)(2(
14
1
1
4
4
1
1
)3)(2(
14
2
*
*
*
41
Example: Setpoint Tracking
0 2 4 6 8 10 12 14 16 18 20-0.5
0
0.5
1
1.5
Outp
ut
Time0 2 4 6 8 10 12 14 16 18 20
-2
-1.5
-1
-0.5
0
0.5
Input
Time