1-Introduction & Review

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2/6/2012 ACA Spring 2012 Shaftab Ahmed 1

Advanced Computer Architecture

Summer 2012

Week #1 Lecture 1&2

Introduction


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Introductory lecture

Computer Architecture

CPU, Memory, I/O, Secondary Storage

Registers cache memory ( static / dynamic ) secondary storage

Timing and control (IO / Memory Read / Write cycles)

Size of register address space Clock Speed of execution

Use of temporary registers, Stack etc


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8086 / 8088 Architecture


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Timing Diagram Bus Read 8088


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Intel 32 bit Processors 80486-Pentium


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Key concepts in State of Art Computer Architecture

Processor + Ram + Busses + I/O Devices Processor

Internal ALU / No of ALUs and Types Number of Registers General Purpose / Special Pipelining Register Aliasing

Caching / Re-Ordering Memory Management

External Busses / Hierarchy -- System / Special / Input Output

DMA -- Direct Memory Access Multiprocessor connectivity Peripheral connectivity


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Intel Processors review

AX, BX,CX,DX (Accumulator, Base, Count, Data)

Useable as AX AH and AL SP Stack Pointer

BP Base address of an array

DI Destination index used with string manipulation instructions

SI Source Index used with string manipulation instructions

CS, DS, ES,SS Segment Registers Flag register containing status information after an instruction

80386 Onwards CPUs have

32 bit Arithmetic Registers (EAX .. )

FS GS are two more segment registers available to programmer

32 bit Flag register, Stack pointer and special registers


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Significance of Flag Register

8088 /8086 CPUC CarryP Parity 0 Odd 1-- EvenA Auxiliary carry used for BCD additionZ 0 Result = Zero; 1 Result != 0S 0 Result Positive 1 Result NegativeT Trap used to exploit on chip debug featureI Interrupt enabled when set = 1; disabled when = 0D Direction D=1 Auto increment of SI or DI

D=0 Auto decrement of SI or DI80286 CPUO Overflow Used to indicate error in signed ADD,

SUB instructions

IOP (Input Output Privilege Level) Range from 00 to 11It determines I/O verses program priority

NT Nested Task

80386 CPURF ResumeVM Virtual Mode

80486 CPUAC Alignment check

Pentium CPUVIF Virtual Interrupt Flag used in multi tasking

VIP Virtual Interrupt Flag Pending used in multi taskingID Indicates that P4 CPU support CPUID instruction


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Intel Processors Memory Organization

Real mode

8088 / 8086 use Segment registers to support addressingin the range 1Mbyte of memory.

Real memory is divided into System area, TransitionProgram Area (TPA) and Interrupt Vector table (IVT) etc.

Protected mode

It was introduced to address memory beyond 1MB LDT, GDT are used for Memory Access beyond 1M

Memory interleaving was used in 80286 processoronwards to reduce memory latency

Subsequent slides show the progressive transition inmemory organization schemes used


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Intel Processors Memory Organization


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Transient Program Area

Interrupt Vector Table


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Interface logic

Interrupt vector table

There are 256 software interrupt vectors. First 32 vectors are

reserved the remaining may be used by the programmer Interrupt vector is a 4 byte number stored in the first 1K bytes

of memory (0 3FF).

Address of interrupt vector is derived by 4*interrupt number

For protected mode the vector table is replaced byinterrupt descriptor table that uses 8 byte entries foreach descriptor


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Interrupts

Hardware interrupt sources are NMI and INT

Mask able Interrupt INT is expanded to 8

hardware interrupts in XT and 16 hardwareinterrupts in AT architecture

Software interrupts may be generated by:

INT Two byte instruction codeinterrupt numberINT3 One byte instruction used to set trap

INTO Interrupt on overflow

All the interrupts use the same Vector table


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System Area


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Expanded Memory Windows


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Descriptor Tables for Protected Mode

In protected mode the segment register contains a selectornumber to use a Descriptor

There are 8192 Local Descriptors and 8192 Global Descriptors

available to a Task. The Global Descriptors are available to all tasks and the Local

Descriptors are available to a particular application or Task


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Example of GDT to Physical Address


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Program Invisible Registers of P4

Descriptor cacheis a set ofprogram invisibleset of registers

Corresponding tothe segmentregisters

They describe thephysical locationof the segment inthe memoryTask Register

Local Desc.Task Register

Global DTR

Interrupt DTR


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Virtual Memory Addressing in Pentium


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Page Directory and Page Table Entry

Linear address

Page Table Entry


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8088-8086-80386 and 80486 Memory

8086, 80286 etc.8088

80386, 80486 etc.


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Pentium 4 Processor Memory

Pentium Pro to Pentium 4


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I/O Address Space

Documents

1-Introduction & Review