(1) Introduction to IC Technology and Applications

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IntroductiontoICTechnology

&

EE405

Dr. Rizwan Akram

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Thesemiconductorindustryisapproaching$300B/yrinsales

Communications

24%

ary

2%

Computers

42%

Industrial

8%ranspor a on

8%

onsumer ec ron cs

16%

CourtesyofDr.BillFlounders,UCBerkeleyMicrolab

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In

1965,

Gordon

Moore

predicted

that

the

number

of

transistors

thatcanbeintegratedonadiewoulddoubleevery18to14months

i.e.,growexponentiallywithtime

Amazingvisionary milliontransistor/chipbarrierwascrossedinthe

1980s.

2300transistors,

1MHz

clock

(Intel

4004)

1971

42Million,2GHzclock(IntelP4)2001

Relativesizes

of

ICs

in

graph

140Milliontransistor(HPPA8500)

100

10

ELENGTH(nm)

Source:Intelwebpage(www.intel.com)7

2000 2005 2010 2015 20201

GA

Y E A R

H IG H P E R F O R M A N C E

InternationalTechnologyRoadmapforSemiconductors


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LimitsofMooresLaw?

Growthexpecteduntil30nmgatelength(currently:180nm)

.

2001+1.5log2((180/30)2)=2009

whatthen?

Paradigmshiftneededinfabricationprocess 8


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Goal:Massfabrication(i.e.simultaneousfabrication)

,

millionsor

billions

of

transistors

Approach: Formthinfilmsofsemiconductors,metals,andinsulatorsoveranentirewafer,andpatterneachlayerwithaprocessmuchlikeprinting(lithography).

Planarprocessingconsistsofasequenceofadditiveandsubtractivestepswithlateralpatterning

oxidation

deposition

ion im lantation

etching lithography

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Planar

Processin DEPOSITION ofathinfilm

(patentedbyFairchildSemiconductorin1959:J.A.Hoerni,USPatent3,064,167)

LITHOGRAPHY Selectivelyexposetheprotectivelayer

Develop

the

protective

layer

ETCH toselectively

remove

the

thin

film

Stri etch the rotective la er


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Test

EpitaxyBareSiliconWafer

Processed

Wafer

Deposition/growth

Anneal

Mask PatternCMP

IonImplantation

Generation

CD

SEMMetrologyDefect

Detection

Etch Lithography


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Whatareshownonpreviousdiagramscoveronlythesocalledfrontend

processing

fabrication

steps

that

go

towards

forming

the

devices

and

interconnectionsbetweenthesedevicestoproducethefunctioningIC's.The

endresultarewaferseachcontainingaregulararrayofthesameICchipor

die. The wafer then has to be tested and the chi s diced u and the ood chi s

mounted

and

wire

bonded in

different

types

of

IC

package

and

tested

again

beforebeingshippedout.

From Howe, Sodini: Microelectronics:An Integrated

Approach, Prentice Hall

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RecurringCosts

costofdie+costofdietest+costof acka in

decades,thebasiccostequationhasntchanged. Costofacircuitisdependentuponthe

chiparea.

var a ecos =

finaltest

yield

costofwafer

diesperwafer dieyield

=

Alphadependsuponthecomplexityofthemanufacturingprocess(andisroughlyproportional

tothenumberofmasks). AgoodestimatefortodayscomplexCMOSprocessisalpha=3.

Defectsperunitareaisameasureofthematerialandprocessinducedfaults. Avalue

between0.5and1defects/cm2 istypicaltodaybutstronglydependsuponthematurityofthe

process.

(waferdiameter/2)2 waferdiameterdies

per

wafer=

diearea 2 diearea 17


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Example

wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,

252 dies/wafer (remember, wafers round & dies square)

die yield of 16%

252 x 16% = only 40 dies/wafer die yield !

Die cost is strong function of die area

proportional to the third or fourth power of the die area

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(Continued)

StructuralExtractionand

PhysicalSynhtesis

Verification

Physical

Representation

Fabrication

Packaging

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Documents

(1) Introduction to IC Technology and Applications