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Lecture - 2

M.Tech. – Weekend Programme

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EDA Tools1. Design Entry

a. View Logic

b. Mentor Graphics (Renoir)

c. Cadence Design System

d. OrCAD

e. ALDEC (Active HDL)

f. SimuCAD (Silos-3)

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EDA Tools2.Design Simulation

a. Model Technology (Modelsim)

b.Synopsy

c. Cadence

d.SimulCAD (Silos-3)

e. Quick turn Design Systems (Power Suite)

f. View Logic (VHD Simulator)

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EDA Tools3. Logic Synthesis

1. Synopsisa. FPGA Expressway

b. FPGA Compiler

2. Synplify (Synplicity)

3. Exempler Logic (Leonardo Spectrum)

4. View Logic (Intelliflow)

5. Cadence Design System

6. Aldec (Active Synthesis)

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EDA Tools4. Programmable Logic (Vendors)

a. Xilinx – Xilinx Foundation Seriesb. Altera – MaxPlus IIc. Altera – Quartus II Ver. 4.0d. Lattice – isp Expert Compilere. Lucent – ORCA Foundary Developmentf. Actel – FPGA Development Systemg. Cypress- Warp2h. Atmel – FPGA Development Systemi. Quick Logic – Quick worksj. Gate Field – ASIC Master

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Other HDLs

1. ISPS (Instruction Set Processor Specification)

- Behavioral Language

- Used to design software based on specific hardware

- Statement level timing control, but no gate level control

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2. TI-HDL

• TI-HDL (Texas Instruction Hardware Description Language)– Created a Texas Instruments– Hierarchical – Models Synchronous and asynchronous circuits – Non-extendable fixed data types

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3. ZEUS

ZEUS

- Created at General Electric

- Hierarchical

- Functional Descriptions

- Structural Descriptions

- Clock Timing, but no gate delays

- No asynchronous circuits

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4. TEGAS

• TEGAS (Test Generation And Simulation)– Structural with behavioral extension– Hierarchical – Allows detailed timing specification

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5. Verilog

• Verilog– Essentially identical in function in VHDL– Simpler and syntactically different– Gateway Design Automation Co. 1983– Early de facto standard for ASIC programming– Open Verilog International Standard– Programming Language Interface to allow

connection to non-Verilog code

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6. ABEL

• ABEL– Simplified HDL– PLD Language– Dataflow primitives e.g. registers– Can use to Program Xilinx FPGA

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7. AHPL

• AHPL (A Hardware Programming Language)– Dataflow language– Implicit Clock– Does not support asynchronous circuits– Fixed data types– Non-hierarchical

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8. CONLAN

• CONLAN (CONsensus LANguage)– Family of Language for describing various

levels of abstraction– Concurrent– Hierarchical

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9. ALTERA

• ALTERA– Created by Altera Corporation– Simplified dialect of HDL

• (AHDL: Altera HDL)

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10. CDL

• CDL (Computer Design Language)– Academic Language for teaching digital

systems– Dataflow Language– Non-hierarchical– Contains conditional statements

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11. IDL

• IDL (Interactive Design Language)– Internal IBM Language– Originally for automatic generation of PLA

Structures– Generalized to cover other circuits– Concurrent– Hierarchical