1

LHO 12 Interfacing

2

A simple bus

bus structure

Processor Memoryrd'/wr

enable

addr[0-11]

data[0-7]

bus

• Wires:– Uni-directional or bi-directional

– One line may represent multiple wires

• Bus– Set of wires with a single function

• Address bus, data bus

– Or, entire collection of wires• Address, data and control

• Associated protocol: rules for communication

3

Timing Diagrams

write protocol

rd'/wr

enable

addr

data

tsetup twrite

• Most common method for describing a communication protocol

• Time proceeds to the right on x-axis• Control signal: low or high

– May be active low (e.g., go’, /go, or go_L)– Use terms assert (active) and deassert– Asserting go’ means go=0

• Data signal: not valid or valid• Protocol may have subprotocols

– Called bus cycle, e.g., read and write– Each may be several clock cycles

• Read example– rd’/wr set low,address placed on addr for at

least tsetup time before enable asserted, enable triggers memory to place data on data wires by time tread

read protocol

rd'/wr

enable

addr

data

tsetup tread

4

Microprocessor interfacing: I/O addressing

• A microprocessor communicates with other devices using some of its pins– Port-based I/O (parallel I/O)

• Processor has one or more N-bit ports• Processor’s software reads and writes a port just like a register• E.g., P0 = 0xFF; v = P1.2; -- P0 and P1 are 8-bit ports

– Bus-based I/O• Processor has address, data and control ports that form a single

bus• Communication protocol is built into the processor• A single instruction carries out the read or write protocol on

the bus

5

Types of bus-based I/O: memory-mapped I/O and

standard I/O• Processor talks to both memory and peripherals using

same bus – two ways to talk to peripherals– Memory-mapped I/O

• Peripheral registers occupy addresses in same address space as memory• e.g., Bus has 16-bit address

– lower 32K addresses may correspond to memory– upper 32k addresses may correspond to peripherals

– Standard I/O (I/O-mapped I/O)• Additional pin (M/IO) on bus indicates whether a memory or peripheral

access• e.g., Bus has 16-bit address

– all 64K addresses correspond to memory when M/IO set to 0– all 64K addresses correspond to peripherals when M/IO set to 1

6

Memory-mapped I/O vs. Standard I/O

• Memory-mapped I/O– Requires no special instructions

• Assembly instructions involving memory like MOV and ADD work with peripherals as well

• Standard I/O requires special instructions (e.g., IN, OUT) to move data between peripheral registers and memory

• Standard I/O– No loss of memory addresses to peripherals– Simpler address decoding logic in peripherals possible

• When number of peripherals much smaller than address space then high-order address bits can be ignored

– smaller and/or faster comparators

7

Consider a simple processor.

I call it the simple processing unit (SPU).

8

The memory read and I/O read timing for a simple processor is shown below.

9

The Memory write and I/O write timing for a simple processor is shown below.

10

I/O Ports

11

12

WRVMAMWR

WRVMAMRD

/

/

No separate I/O address space.

Some Real processors

13

WRMWR

WRMRD

/

/

No separate I/O address space.

14

MIOWRMIOWRIOWRMIORDMIORDIORD

MIOWRMIOWRMWRMIORDMIORDMRD

////

////

15

IOREQWRIOWRIOREQRDIORD

MREQWRMREQWRMWRMREQRDMREQRDMRD

16

WR

RD

IOMWRIOMWRIOWRIOMRDIOMRDIORD

IOMWRMIOWRMWRIOMRDIOMRDMRD

////

////

17

U4

8751

29

30

40

31

1918

9

3938373635343332

12345678

2122232425262728

1011121314151617

PSEN

ALE/PROG

VCC

EA/VPP

X1X2

RST

P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

P2.0/A8P2.1/A9P2.2/A10P2.3/A11P2.4/A12P2.5/A13P2.6/A14P2.7/A15

P3.0/RXDP3.1/TXDP3.2/INT0P3.3/INT1P3.4/T0P3.5/T1P3.6/WRP3.7/RD

The 8051 U1

AT90S8515

9

1819

2930

31

40

2122232425262728

1011121314151617

12345678

3938373635343332

RST

XTAL2XTAL1

OC1BALE

ICP

VCC

PC0/A8PC1/A9

PC2/A10PC3/A11PC4/A12PC5/A13PC6/A14PC7/A15

PD0/RXDPD1/TXD

PD2/INT0PD3/INT1

PD4PD5/OC1A

PD6/WRPD7/RD

PB0/T0PB1/T1PB2/AIN0PB3/AIN1PB4/SSPB5/MOSIPB6/MISOPB7/SCK

PA0/AD0PA1/AD1PA2/AD2PA3/AD3PA4/AD4PA5/AD5PA6/AD6PA7/AD7

Atmel AVR

18

19

8051

20

21

22

A basic memory protocol

• Interfacing an 8051 to external memory– Ports P0 and P2 support port-based I/O when 8051 internal memory

being used– Those ports serve as data/address buses when external memory is

being used– 16-bit address and 8-bit data are time multiplexed; low 8-bits of

address must therefore be latched with aid of ALE signal

P0

P2

Q

ALE

/RD

Adr. 7..0

Adr. 15…8

Adr. 7…0

Data

8051

74373

P0

HM6264

D Q

8P2

ALE G

A<0...15>

D<0...7>

/OE

/WE

/CS

/WR

/RD

/CS1

/PSEN

CS2

27C256

/CS

A<0...14>

D<0...7>

/OE

23

8051 instructions for addressing external code and data memory.

24

8051

74373

P0HM6264

D Q

8

P2

ALE G

A<0...15>

D<0...7>

/OE

/WE

/CS

/WR

/RD

/CS1

/PSE

N

CS2

27C256

/CS

A<0...14>

D<0...7>

/OE

Ex: XM(0) XM(1)MOV DPTR,#0MOVX A,@DPTRINC DPTRMOV R7,AMOVX A,@DPTRXCH A,R7MOVX @DPTR,ADEC DPTRXCH A,R7MOVX @DPTR,A

Ex: XM(0) XM(1)CLR P2CLR R0MOV R1,#1MOVX A,@R0MOV R7,AMOVX A,@R1MOVX @R0,AMOV A,R7MOVX @R1,A

25

AIN

BNC

1

2

D6

R450

D5

5 Vd

C82.2uF

D4

D0

U9

8751

29

30

40

31

1918

9

3938373635343332

12345678

2122232425262728

1011121314151617

PSEN

ALE/PROG

VCC

EA/VPP

X1X2

RST

P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

P2.0/A8P2.1/A9

P2.2/A10P2.3/A11P2.4/A12P2.5/A13P2.6/A14P2.7/A15

P3.0/RXDP3.1/TXD

P3.2/INT0P3.3/INT1

P3.4/T0P3.5/T1

P3.6/WRP3.7/RD

C92.2uF

R5200

D3

D1D2

PORTF0

C10

.1uF

D7

#busy

GND DIG

R/#C

U8

AD976/S0

1

2

3

4

5

26

28

27

2221201918171615131211109876

23

24

25

14

ANAIN

AGND1

REF

CAP

AGND2

BUSY

Vdig

Vana

D0D1D2D3D4D5D6D7D8D9

D10D11D12D13D14D15

BYTE

R/C

CS

DGND

5 Va

R633.2K

PORTF1

RnC EQU P1.1n_BUSY EQU P1.2BYTE EQU P1.3

26

RnC EQU P1.1n_BUSY EQU P1.2BYTE EQU P1.3

CLR RnCSETB RnCJNB n_BUSY,$MOV R7,P0CPL BYTEMOV R6,P0

27

The 8255

28

29

30

31

32

Change individual bits on Port C

33

D4

D7

U4

8751

29

30

40

31

1918

9

3938373635343332

12345678

2122232425262728

1011121314151617

PSEN

ALE/PROG

VCC

EA/VPP

X1X2

RST

P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

P2.0/A8P2.1/A9P2.2/A10P2.3/A11P2.4/A12P2.5/A13P2.6/A14P2.7/A15

P3.0/RXDP3.1/TXDP3.2/INT0P3.3/INT1P3.4/T0P3.5/T1P3.6/WRP3.7/RD

U2

82C55A

3433323130292827

536

98

356

432140393837

1819202122232425

1415161713121110

D0D1D2D3D4D5D6D7

RDWRA0A1RESETCS

PA0PA1PA2PA3PA4PA5PA6PA7

PB0PB1PB2PB3PB4PB5PB6PB7

PC0PC1PC2PC3PC4PC5PC6PC7

D2

D3

D7

D7

D2

D3

D3

D5

U1

82C55A

3433323130292827

536

98

356

432140393837

1819202122232425

1415161713121110

D0D1D2D3D4D5D6D7

RDWRA0A1RESETCS

PA0PA1PA2PA3PA4PA5PA6PA7

PB0PB1PB2PB3PB4PB5PB6PB7

PC0PC1PC2PC3PC4PC5PC6PC7

D1D0

D4

D2

D4

D0

ALE

D7

D5

D0

/WR

D0

U3

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

D3

D6D5

D5

D1

D6

/RD

D1

D4

D2

D6

D6

D1

34

RESET_8255 EQU P1.0CTL1 EQU 111111111011B ;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #1PRTA1 EQU 111111111000B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1PRTB1 EQU 111111111001B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1PRTC1 EQU 111111111010B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #1CTL2 EQU 111111110111B ;ONE POSSIBLE ADDRESS FOR CONTROL PORT OF 8255 #2PRTA2 EQU 111111110100B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2PRTB2 EQU 111111110101B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2PRTC2 EQU 111111110110B ;ONE POSSIBLE ADDRESS FOR PORT A OF 8255 #2

CLR RESET_8255 ;REMOVE RESET FROM 8255;DO ADDITION C2|C1 <-- A2|A1 + B2|B1 MOV DPTR,#(CTL1 AND CTL2);POINT DPTR TO CONTROL REG OF 8255 #1 AND #2 MOV A,10010010B ;PRTA, PRTB IN, PRTC OUT MOVX @DPTR,A ;OUTPUT TO BOTH CONTROL REGS AT SAME TIME MOV DPTR,#PRTA1 ;SELECT PORT A OF 8255 #1 MOVX A,@DPTR ;GET PRTA1 MOV R7,A ;SAVE IT MOV DPTR,#PRTB1 ;SELECT PORT B OF 8255 #1 MOVX A,@DPTR ;READ PORT B OF 8255 #1 ADD A,R7 ;ADD PRTA1 TO PRTB1 MOV DPTR,#PRTC1 ;SELECT PORT C OF 8255 #1 MOVX @DPTR,A ;OUTPUT TO PRTC1 END

35

A10

D0

D7

A11

/WR

D3

A12

D1

U1

82C55A

3433323130292827

536

98

356

432140393837

1819202122232425

1415161713121110

D0D1D2D3D4D5D6D7

RDWRA0A1RESETCS

PA0PA1PA2PA3PA4PA5PA6PA7

PB0PB1PB2PB3PB4PB5PB6PB7

PC0PC1PC2PC3PC4PC5PC6PC7

D2

/RD

D5A12

U4

8751

29

30

40

31

1918

9

3938373635343332

12345678

2122232425262728

1011121314151617

PSEN

ALE/PROG

VCC

EA/VPP

X1X2

RST

P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

P2.0/A8P2.1/A9P2.2/A10P2.3/A11P2.4/A12P2.5/A13P2.6/A14P2.7/A15

P3.0/RXDP3.1/TXDP3.2/INT0P3.3/INT1P3.4/T0P3.5/T1P3.6/WRP3.7/RD

D4

A13

D2

A9

A13

D5

D3

A8

A14

D0

D5D6

D4

A14

D6

A11

A9

D1

D6

A15

D4D3

A15 D7

D1D0

A10

D2

U2

82C55A

3433323130292827

536

98

356

432140393837

1819202122232425

1415161713121110

D0D1D2D3D4D5D6D7

RDWRA0A1RESETCS

PA0PA1PA2PA3PA4PA5PA6PA7

PB0PB1PB2PB3PB4PB5PB6PB7

PC0PC1PC2PC3PC4PC5PC6PC7

D7

A8

36

U1

AT90S8515

9

1819

2930

31

40

2122232425262728

1011121314151617

12345678

3938373635343332

RST

XTAL2XTAL1

OC1BALE

ICP

VCC

PC0/A8PC1/A9

PC2/A10PC3/A11PC4/A12PC5/A13PC6/A14PC7/A15

PD0/RXDPD1/TXD

PD2/INT0PD3/INT1

PD4PD5/OC1A

PD6/WRPD7/RD

PB0/T0PB1/T1PB2/AIN0PB3/AIN1PB4/SSPB5/MOSIPB6/MISOPB7/SCK

PA0/AD0PA1/AD1PA2/AD2PA3/AD3PA4/AD4PA5/AD5PA6/AD6PA7/AD7

37

38

D3

A15

A10

A13

D3

n_WR

D6

A13

D4

D5

A9

A0

D5

n_WR

A14

n_RD

A5A6

A12

D5A0

D6

A10

A12

D0U2

74LS373

111

3478

13141718

256912151619

OCC1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

D4

C122 pf

A3

D1

A4

D6 A6

D7

U4

AT49BV001N

22

2431

32

131415

121110

98765

27262325

42829

1718192021

32

CE

OEWE

VCC

I/O0I/O1I/O2

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14

I/O3I/O4I/O5I/O6I/O7

A15A16

n_RD

U1

AT90S8515

9

1819

2930

31

40

2122232425262728

1011121314151617

12345678

3938373635343332

RST

XTAL2XTAL1

OC1BALE

ICP

VCC

PC0/A8PC1/A9

PC2/A10PC3/A11PC4/A12PC5/A13PC6/A14PC7/A15

PD0/RXDPD1/TXD

PD2/INT0PD3/INT1

PD4PD5/OC1A

PD6/WRPD7/RD

PB0/T0PB1/T1PB2/AIN0PB3/AIN1PB4/SSPB5/MOSIPB6/MISOPB7/SCK

PA0/AD0PA1/AD1PA2/AD2PA3/AD3PA4/AD4PA5/AD5PA6/AD6PA7/AD7

A9A8

A11

D4

VCC

A1

D1A7

A3

D7

A1A2

A4

D2

Y18 MHz

D0

A5

A15

D1

C222 pf

A14

D3

A7

A2D2

VCC

A11

A8

D0

D2D7

Figure 1. AT90S8515 with expanded memory. What should we do with A16? Answer: connect it to an unused port pin.Question: How could we map the entire 128K bytes of memory to the top 32 Kbytes of the AVR address space.Answer: Connect AVR A15 to /CE on U4. Now the memory is selected only when the AVR addresses the top have of the memory address space where A15 = 1. Connect A15 and A16 of U4 to unused AVR port pins. By changing these port pin, any of the four 32 K byte pages of U4 memory can be switched in and out of the AVR address space.

39

40

41

42