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1
Optimizing multi-processor system composition
Characterization Presentation November 20th – 2007
Performing: Isaac YaromSupervising: Mony
Orbach
Annual project – Semester A (2007-1)
2
General
A few teams from HS DSL are developing a multi-processors system that implements a recognition algorithm (D0417, D0317, D0136).
The system is design as SOPC using: Gidel ProcstarII® Altera FPGA, implementing NiosII® soft core
based accelerators. System will be ready at the start of 2007-
2.
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General - The System
PC
I
Host/Genertor
Switch
NiosII® Processor
NiosII® Processor
FPGAUsing shared RAM on GIDEL card to communicate between switch and processing units.
NiosII® Processor
NiosII® Processor…..
4
General
o SOPC design provides us flexibility in later stages of the design process.
o More hardware equals greater throughput.
o Main constraint is fixed limited area for hardware upon the FPGA.
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Working environment
Sampling vectors 8-1024(2048B needs to be checked too) - derived from specification document. Arrive at fixed rate.
NiosII® configurations might differ in cache size and C2H Effecting throughput Effecting Area
Area is limited and fixed for system
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Project Goals
Developing and implementing performance study methods. Constraint is FPGA area. This will limit number
of configuration to study. Determining composition of NiosII® cores for
optimal system: Symmetric/Asymmetric system NiosII Configuration Memory defined for each NiosII
Optimizing the given system using the developed methods.
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Requirments
The NiosII® processors need to be categorized by cache size and area needed.
Designed and validated NiosII® processor (and algorithm) for basic configuration (1024B cache). Other configurations need to be setup in this
project. SWITCH must support at least one basic
algorithm for using asymmetric cores.
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Project expected outcomes
Performance evaluation methods and tools Might be integrated with Host software.
Software model (non functional simulator) + results
Recommendations for system configurations to check out in hardware
Dummy-system (+ performance study) Interface between SWITCH and NiosII® will
include fields to allow system asymmetric configuration.
Nice to have: Theoretical analytical recommendations for
hardware systems to check.
2007-1
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Project expected outcomes
“Starting point”: Basic system
Configurable NiosII® cores Configurable SWITCH
Performance evaluation methods and tools Software model + recommendations
Outcomes: Performance study for 2-3 configurations Optimized system
2007-2
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Workflow (2007-1)
Build NIOS over STARTEX
Choose and develop methods
to evaluate system performance
Evaluate performance of Dummy-system
2007-2
Project Start
This includes learning the tools needed to setup NIOS
on STARTEX FPGA.
Implement/”Borrow” Algorithm
in ANSI-C.Will work with
HOST
Debug/Validate Dummy-System
Define model for system
Define interface needed to allow
flexible number of processors and
their composition
Analyze a theoretical
(mathematical) model of the
system
Implement software model for
system (Simulation)
Run simulations for different
configurations and analyze results
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Workflow (2007-2)2007-2
Reestablish cost function according to actual system
End of 2007-2
At this point we should have a fully optimized system
Rerun software simulation according to new Area constraint and modify configuration to check
accordingly
Build and compare performance of 2-3
configurations and show superiority of preferred
configuration.
Write final report
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Schedule until midterm
3-Dec-07 3-Jan-08
16-Dec-07Specification for performance evaluation methods
16-Dec-07Specification of fields required in interface between SWITCH and proccessing units
23-Dec-07Build NiosII(R) over STARTEX system
9-Dec-07System model definition
30-Dec-07Run NiosII(R) with algorithm
1-Jan-08Define theoretical model and analyze it
3-Jan-08Mid-term presentation
10-Dec-07Characterization presentation