1

Progettazione di circuiti e sistemi VLSI

Anno Accademico 2011-2012

Prof. Adelio Salsano

6.3 e 8.3

Presentazione e programma del corso

2

Programma

• Cenni storici. Problematiche progettuali: costi, prestazioni, potenza.

• Tecnologie integrate CMOS: passi progettuali, regole di layout, packaging

• Richiami sui componenti elementari ideali e reali. Modelli SPICE del diodo, del transistor MOS e dei componenti passivi

• Interconnessioni, modelli RC. Modelli SPICE delle connessioni

• Nanotecnologie: aspetti tecnologici e modelli

3

Programma (segue)• Circuiti digitali elementari: inverter CMOS e

transmission gate. Caratteristiche statiche e dinamiche. Potenza, energia e ritardo dei circuiti elementari

• Porte logiche combinatorie. Logica statica e dinamica. Prestazioni e caratteristiche

• Circuiti logici sequenziali. Latch e registri. Pipeline

• Circuiti e sistemi digitali complessi e metodologie di implementazione: processori, PLA, FPGA, standard cell

• Memorie statiche e dinamiche. Memorie e non volatili

4

Programma (segue)• Affidabilità e tolleranza ai guasti dei circuiti

integrati. Circuiti integrati analogici: interruttori, riferimenti di corrente e tensione, specchi di corrente, amplificatori differenziali

• Strumenti per la progettazione di circuiti e sistemi: linguaggi descrittivi, i principali programmi di sintesi

• Progettazione custom, standard cell e componenti programmabili

• Progettazione ad alta affidabilità e/o basso consumo

5

Programma Esercitazioni (segue)

Sono previste esercitazioni sui seguenti temi:• Programmi simulazione (LTSpice…)• Calcolo parametri• Progettazione digitale RTL• Progetto circuiti e sistemi• FPGA e Xilinx• Linguaggi descrittivi• Progettazione FPGA

6

Notizie sul corso

Esercitazioni • Sono previste 25 ore di esercitazioni con l’uso di software di progetto

e simulazione di componenti e circuiti prevalentemente digitali.Collaboratori

• Prof. Stefano Bertazzoni; Salvatore Pontarelli e Marco Ottavi Materiale didattico Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Circuiti

Integrati Digitali: l’ottica del progettista”, Pearson Prentice Hall R. L. Geiger, P.E. Allen, N.R. Strader VLSI design techniques for

analog and digital Circuits, Mac Graw Hill Int. Ed. Diapositive lezione e esercitazioni

7

Notizie sul corso (segue)

ORARIOMartedì 9,30 – 11,15 Aula C8Giovedì 9.30 – 11.15 Aula C8Venerdì 9.30 - 11.15 Aula C1

RICEVIMENTO STUDENTILunedì e giovedì 15 – 16.30

8

What is this course/book about?

• Introduction to digital integrated circuits.– CMOS devices and manufacturing technology.

CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.

• What will you learn?– Understanding, designing, and optimizing digital

circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability

9

The First Computer

The BabbageDifference Engine(1832)

25,000 partscost: £17,470

10

ENIAC - The first electronic computer (1946)

11

The Transistor Revolution

First transistorBell Labs, 1948

12

The First Integrated Circuits

Bipolar logic1960’s

ECL 3-input GateMotorola 1966

13

Intel 4004 Micro-Processor

19711000 transistors1 MHz operation

14

Intel Pentium (IV) microprocessor

15

Moore’s Law

He made a prediction that semiconductor technology will double its effectiveness every 18 months

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

16

Moore’s Law

161514131211109876543210

19

59

19

60

19

61

19

62

19

63

19

64

19

65

19

66

19

67

19

68

19

69

19

70

19

71

19

72

19

73

19

74

19

75

LO

G 2 O

F T

HE

NU

MB

ER

OF

CO

MP

ON

EN

TS

PE

R I

NT

EG

RA

TE

D F

UN

CT

ION

Electronics, April 19, 1965.

17

Evolution in Complexity

18

Transistor Counts

1,000,000

100,000

10,000

1,000

10

100

11975 1980 1985 1990 1995 2000 2005 2010

8086

80286i386

i486Pentium®

Pentium® Pro

K1 Billion

Transistors

Source: Intel

Projected

Pentium® IIPentium® III

Courtesy, Intel

19

Moore’s law in Microprocessors

40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(M

T)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

Courtesy, Intel

20

Die Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

Courtesy, Intel

21

Frequency

P6Pentium ® proc

486386

28680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel

22

Power Dissipation

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

Courtesy, Intel

23

Power will be a major problem

5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Courtesy, Intel

24

Power density

400480088080

8085

8086

286386

486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

Courtesy, Intel

25

Not Only Microprocessors

Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband

(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

(data from Texas Instruments)

CellPhone

26

Challenges in Digital Design

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

?

27

Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

200

3

198

1

198

3

198

5

198

7

198

9

199

1

199

3

199

5

199

7

199

9

200

1

200

5

200

7

200

9

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty

Courtesy, ITRS Roadmap

28

Why Scaling?• Technology shrinks by 0.7/generation• With every generation can integrate 2x more

functions per chip; chip cost does not increase significantly

• Cost of a function decreases by 2x• But …

– How to design chips with more and more functions?– Design engineering population does not double every

two years…• Hence, a need for more efficient design methods

– Exploit different levels of abstraction

29

Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

30

Design Metrics

• How to evaluate performance of a digital circuit (gate, block, …)?– Cost– Reliability– Scalability– Speed (delay, operating frequency) – Power dissipation– Energy to perform a function

31

Cost of Integrated Circuits

• NRE (non-recurrent engineering) costs– design time and effort, mask generation– one-time cost factor

• Recurrent costs– silicon processing, packaging, test– proportional to volume– proportional to chip area

32

NRE Cost is Increasing

33

Die Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)

34

Cost per Transistor

0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.11

1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

cost: ¢-per-transistor

Fabrication capital cost per transistor (Moore’s law)

35

Yield%100

per wafer chips ofnumber Total

per wafer chips good of No.Y

yield Dieper wafer Dies

costWafer cost Die

area die2

diameterwafer

area die

diameter/2wafer per wafer Dies

2

36

Defects

area dieareaunit per defects

1yield die

a is approximately 3

4area) (die cost die f

37

Some Examples (1994)Chip Metal

layersLine width

Wafer cost

Def./ cm2

Area mm2

Dies/wafer

Yield Die cost

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 601

4 0.80 $1700 1.3 121 115 28% $53

HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

38

Reliability―Noise in Digital Integrated Circuits

i(t)

Inductive coupling Capacitive coupling Power and ground noise

v(t) VDD

39

DC Operation

Voltage Transfer Characteristic

V(x)

V(y)

VOH

VOL

VM

VIH

VIL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH = f(VIL)VOL = f(VIH)VM = f(V(X) per V(x) = V(y)

40

Mapping between analog and digital signals

VIL

VIH

Vin

Slope = -1

Slope = -1

VOL

VOH

Vout

“ 0” VOL

VIL

VIH

VOH

UndefinedRegion

“ 1”

41

Definition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

42

Noise Budget

Allocates gross noise margin to expected sources of noise

Sources: supply noise, cross talk, interference, offset

Differentiate between fixed and proportional noise sources

43

Key Reliability Properties

• Absolute noise margin values are deceptive– a floating node is more easily disturbed than a node driven by a

low impedance (in terms of voltage)• Noise immunity is the more important metric – the capability

to suppress noise sources• Key metrics: Noise transfer functions, Output impedance of the

driver and input impedance of the receiver;

44

Regenerative Property

v0

v1

v3

finv(v)

f(v)

v3

out

vRegenerative Non-Regenerative

v2

v1

f(v)

finv(v)

v3

out

v

45

Regenerative Property

A chain of inverters

v0 v1 v2 v3 v4 v5 v6

2

V (

Volt

)

4

v0

v1v2

t (nsec)0

2 1

1

3

5

6 8 10 Simulated response

46

Fan-in and Fan-out

N

Fan-out N Fan-in M

M

47

The Ideal Gate

Ri = ¥Ro = 0Fanout = ¥NMH = NML = VDD/2 g =

V in

V out

48

An Old-time Inverter

NMH

V in (V)

NM L

VM

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

49

Delay Definitions

Vout

tf

tpHL tpLH

tr

t

Vin

t

90%

10%

50%

50%

50

Ring Oscillator

v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 ´ tp ´ N

51

A First-Order RC Network

vout

vin C

R

tp = ln (2) t = 0.69 RC

Important model – matches delay of inverter

52

Power Dissipation

Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power: Ppeak = Vsupplyipeak

Average power:

Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1

53

Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav tp

Energy-Delay Product (EDP) =

quality metric of gate = E tp

54

A First-Order RC Network

Vdd

Vout

isupply

CL

E0->1 = CLVdd2

PMOS

NETWORK

NMOS

A1

AN

NETWORK

E0 1 P t dt

0

T Vdd isupply t dt

0

T Vdd CLdVout

0

Vdd

CL Vdd 2= = = =

Ecap Pcap t dt

0

T Vouticap t dt

0

T CLVoutdVout

0

Vdd 1

2---C

LVdd

2= = = =

vout

vin CL

R

55

SummaryDigital integrated circuits have come a long way and still

have quite some potential left for the coming decadesSome interesting challenges ahead

Getting a clear perspective on the challenges and potential solutions is the purpose of this book

Understanding the design metrics that govern digital design is crucialCost, reliability, speed, power and energy dissipation