1

Random-Access Random-Access Memory (RAM)Memory (RAM)

Note: We’re skipping Sec 7.5

Today:

• First Hour: Static RAM– Section 7.6 of Katz’s Textbook

– In-class Activity #1

• Second Hour: Dynamic RAM• Section 7.6 of Katz’s Textbook

– In-class Activity #2

2

RecapRecap1. Edge-triggered Flip Flops

2. Sequential Modules

• Registers: esp. shift registers

• Counters: esp., Self-Starting Counters

3. Counter Design Procedure:

1. Draw a State Transition Diagram

2. Derive the State Transition Table

3. Choose a Flip-Flop

4. Derive the Flip-Flop Input Functions

5. Sketch the circuit

6. Add Refinements such as Power-up Reset

3

670

Q4

D1

D4D3D2

Q3Q2Q1

GW

WAWB

GR

RARB

54

11

1413

12

15123

10976

Recap: Recap: 4-by-4 Register File4-by-4 Register File

To write Register 1, set GW = 0 and (WB, WA) to (0,1)

To read Register 2, set GR = 0 and (RB, RA) to (1,0)Can read and write simultaneously,

No clock. Read or write when enables asserted.

To write Register 1, set GW = 0 and (WB, WA) to (0,1)

To read Register 2, set GR = 0 and (RB, RA) to (1,0)Can read and write simultaneously,

No clock. Read or write when enables asserted.

Read enable

Data Out

Read Select

Data in

Write enable

Register 0

(4 bits)

Register 1

(4 bits)

Register 2

(4 bits)

Register 3

(4 bits)Write Select

4

How it worksHow it works

Register 0

Register 1

Register 2

Register 3

MUX

Re

ad

Se

lect

Data Out

DMUX

Re

ad

en

able

Write

Se

lect

Data in

Wri

te e

nab

le

5

Random Access MemoriesRandom Access Memories(RAM)(RAM)

• Same idea as a register file, but optimized for very many words.

– Small RAM: 256 4-bit words.

– Larger RAM: 4 million 8-bit words.

• Some Changes:– No separate Read and Write Selects

– Register select lines now called ADDRESS LINES

– DATA IN and DATA OUT use shared wires

– Designed such that multiple RAM chips can be connected together to build larger memory systems (e.g., 512 MB)

6

1024 x 4-bit RAM1024 x 4-bit RAM

Cell #0

Cell #1

Cell #2

Cell #1021

Cell #1022

Cell #1023

1024 = 210 cells

10 Address Bits

4 bits per cell

4 Data Bits

7

Typical RAM ChipTypical RAM Chip

To Read:

To Write:

To Read:

To Write:

1024 x 4 SRAM

A0A1A2A3A4A5A6A7A8A9WECS

IO0IO1IO2IO3

Chip SelectChip Select Write EnableWrite Enable

4 Bi-directional Data Lines (read & write)4 Bi-directional Data Lines (read & write)10 Address Lines10 Address Lines

Address...AA1,WE0,CS 09

Data...IOIOAddress...AA0,WE0,CS 0309 ,

8

Basic RAM StructureBasic RAM Structure

A0

A1

DM

UX READ

LINES

SELECT

LINES

Memory Buffer Register

IO0IO1IO2IO3

WE

WRITE

LINES

TRI-STATE LOGIC USED HERE

9

Practical RAM DesignsPractical RAM Designs

• 1024 x 4-bit RAM will have 1024 rows, and 4 columns– “Long, Thin Design”

– Not very practical to fabricate

– Long wires can make a chip run slowly

• Need to make the design more “square”.

10

A Squarer DesignA Squarer Design

AddressBuffers

for

RowDecoders

A9

A8

A7

A6

A5

A4

Storage Matrix

64 x 16 64 x 16 64 x 16 64 x 16

Sense Amplifiers

AddressBuffers

for

ColumnDecoders

A3

A2

A1

A0

Data BuffersCS

WE

I/O0 I/O1 I/O2 I/O3

64 x 64SquareArray

Amplifiers &Mux/Demux

Some Addrbits select

row

Some Addrbits selectwithin row

Tri-State Data Out

11

Timing DiagramsTiming Diagrams• We have 10 address bits, 4 data bits, and 2 control

signals– A conventional timing diagram will be much too big!

– Need some notation to represent groups of bits

A9 … A0

Bits Can Change Here

Bits Steady Here

(May be 0 or 1)

12

Read Operation Read Operation WE

CS

Address

Data Out Data Out

Valid Address

Access Time

Access Time

The time it takes for new data to appear at

the output

Access Time

The time it takes for new data to appear at

the output

New Notation!

Center line means

High-Z state (disconnected)

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Other Timing ConventionsOther Timing ConventionsInput Signal Output SignalInput Signal Output Signal

Must be steady Will be steady high or lowhigh or low

High-to-low Will be changing fromchanges permitted high-to-low during

designated interval

Low-to high Will be changing fromchanges permitted low-to-high during

designated interval

Don't-Care State changing

(Does not apply) Centerline represents high impedance (off) state

14

Write TimingWrite Timing

Input Data

Valid Address

Data In

Address

WE

CS

Memory Cycle Time

Data is sensed

during this time

15

Do Activity #1 NowDo Activity #1 NowExplore the data sheet for a RAM chip, and answer a few questions

The complete data sheets are on the course website (calendar tool, today’s date)

For Qns 6 & 7, please stay consistent with the truth table on the third page of the data sheet.

The circuit diagram on the first page may be a bit confusing.

16

Types of RAMTypes of RAM1. Static RAM (from first hour)

• Easy to understand/use: One D-type Flip Flop for each bit

• Fast

• Hard to scale up

• Occupies a lot of chip area

• Expensive

• Dynamic RAM• Scalable: One tiny capacitor, and one transistor for each bit

• Slower than SRAM, but very cheap, and dense

• Hassles:

• Destructive readout

• Bit contents decay, so need to be refreshed periodically

17

SRAM CellSRAM Cell

Data Data

Word Enablei

j

Basic Idea:

Try to minimize the complexity of each cell

A fancy Master/Slave JK would be inappropriate here!

18

Dynamic RAMs (DRAMs)Dynamic RAMs (DRAMs)

Word Line

Bit Line

To Read: assert Word LineWord Line, sense Bit LineBit Line

To Write: assert Word LineWord Line, drive Bit LineBit Line

Single TransistorSingle Transistor (a switch), and a capacitor memory element

Read-Out is Destructive! Read-Out is Destructive! Extra circuits needed to write back what was read

Capacitor leaks, so Capacitor leaks, so Storage decays in msms

Refresh CyclesRefresh Cycles needed

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DRAM RefreshDRAM Refresh

Refresh FrequencyRefresh Frequency

4096 word RAM -- refresh each word once every 4 ms

Assume 120 ns memory access cycle

This is one refresh cycle every 976 ns (1 in 8 DRAM accesses1 in 8 DRAM accesses)!

But this RAM is really organized into 64 rows

This is one refresh cycle every 62.5 µs (1 in 500 DRAM 1 in 500 DRAM accessesaccesses)

Large capacity DRAMs have 256 rows, refresh once every 16 µsrefresh once every 16 µs

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Do Activity #2 NowDo Activity #2 NowDue: End of Class Today.

RETAIN THE LAST PAGE(S) (#3 onwards)!!

For Next Class:• Bring Randy Katz Textbook, & TTL Data Book

• Required Reading:– Sec 8.1, 8.2 of Katz

• This reading is necessary for getting points in the Studio Activity!