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Instruction Set Architecture (ISA)• The ISA is the interface between hardware and software.
• The ISA serves as an abstraction layer between the HW and SW– Software doesn’t need to know how the processor is implemented– Any processor that implements the ISA appears equivalent
• An ISA enables processor innovation without changing software– This is how Intel has made billions of dollars.
• Before ISAs, software was re-written/re-compiled for each new machine.
Software
Proc #1
ISA
Proc #2
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What is instruction set architecture (ISA)?
• Instruction set of a computer: the portion of the computer visible to the assembly level programmer or to the compiler writer ISA– Defines registers
– Defines data transfer modes (instructions) between registers, memory and I/O
– There should be sufficient instructions to efficiently translate any program
• Next, define instruction set format – binary representation used by the hardware– Variable-length vs. fixed-length instructions
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Growth/Variations of Processors1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
01998 2000 2001 20021999
Other
SPARC
Hitachi SH
PowerPC
Motorola 68K
MIPS
IA-32
ARM
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Instruction Set Instruction Set ArchitecturesArchitectures
• There are 4 classes of ISA
– Stack
• Embedded processors
– Accumulator
• Embedded processors
– Register-memory
• Pentium
– Register-Register (Load-store)
• Sparc
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Instruction Set Instruction Set ArchitectureArchitecture
• For a general purpose high-performance computer
– Register-Register (Load-store) is the preferred choice
• CPI uniform for most instructions
– Better pipelining
• Fixed length instructions
– Simpler encoding
• The complier is more complicated
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Important issues to Important issues to consider for designing an consider for designing an
ISAISA
• What are the different addressing modes that should be used
• What is the length of instructions
• What are the different instructions used
• What is the type and size of operands
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Addressing Modes
Addressing mode Example Meaning
Register Add R4,R3 R4 R4+R3
Immediate Add R4,#3 R4 R4+3
Displacement Add R4,100(R1) R4 R4+Mem[100+R1]
Register indirect Add R4,(R1) R4 R4+Mem[R1]
Indexed / Base Add R3,(R1+R2) R3 R3+Mem[R1+R2]
Direct or absolute Add R1,(1001) R1 R1+Mem[1001]
Memory indirect Add R1,@(R3) R1 R1+Mem[Mem[R3]]
Auto-increment Add R1,(R2)+ R1 R1+Mem[R2]; R2 R2+d
Auto-decrement Add R1,–(R2) R2 R2-d; R1 R1+Mem[R2]
Scaled Add R1,100(R2)[R3] R1 R1+Mem[100+R2+R3*d]
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Addressing Modes
0 10 20 30 40 50 60
Displacement
I mmediate
Register indirect
Scaled
Memory indirect
Frequency of addressing mode
avggccspiceTeX
75%
85%
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Addressing Modes
Register (direct) mode
Example: ADD $r1, $r2, $r3
op: opcode
rs: first source register
rt: second source register
rd: destination register
op rs rt rd
register
op 1 2 3
100
$r1 = 100
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Addressing Modes
Immediate mode
Example: ADDI $r3, $r1, 12
op rs rt immed
op 3 1 12
op: opcode
rs: source register
rt: destination register
immed: constant
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Addressing Modes
Displacement mode
Example: LOAD $r1, 100($r2)
op rs rt immed
register
Memory
+
$r2 = 150; 100($r2) = 88
op 2 1 100
150
Memory
88+Address = 250
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Displacement and Immediate Displacement and Immediate ValuesValues
• Important addressing modes: Register, immediate, displacement, register indirect. Account for 88% of workload.
• Through measurements, 12-16 bits are enough to cover the majority of cases for the value of immediate
• This will allow to have instruction sets of fixed size of 32 bits – most microprocessors
opcode rs rt
6 5 5
rd
5
shamt
5
func
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R-Type Format
opcode rs rt immediate
6 5 5 16
I-Type Format
opcode immediate
6 26
J-Type Format
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Instruction Usage Instruction Usage Example:Example:
Top 10 Intel X86 Top 10 Intel X86 InstructionsInstructions
Rank Integer Average Percent total executed
1
2
3
4
5
6
7
8
9
10
instruction
load
conditional branch
compare
store
add
and
sub
move register-register
call
return
Total
Observation: Simple instructions dominate instruction usage frequency.Observation: Simple instructions dominate instruction usage frequency.
22%
20%
16%
12%
8%
6%
5%
4%
1%
1%
96%
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Instruction Set Instruction Set EncodingEncoding
Considerations affecting instruction set encoding:
– To have as many registers and address modes as possible.
– The Impact of the size of the register and addressing mode fields on the average instruction size and on the average program.
– To encode instructions into lengths that will be easy to handle in the implementation. On a minimum to be a multiple of bytes.
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Instruction FormatInstruction Format• Fixed
– Operation, address specifier 1, address specifier 2, address specifier 3.– MIPS, SPARC, Power PC.
• Variable– Operation & # of operands, address specifier1, …, specifier n.– VAX
• Hybrid– Intel x86– operation, address specifier, address field.– Operation, address specifier 1, address specifier 2, address field.– Operation, address field, address specifier 1, address specifier 2.
• Summary:– If code size is most important, use variable format.– If performance is most important, use fixed format.
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Three Examples of Instruction Set Three Examples of Instruction Set EncodingEncoding
Variable: VAX (1-53 bytes)
Operations &no of operands
Addressspecifier 1
Addressfield 1
Address specifier n
Address field n
Operation Addressfield 1
Addressfield 2
Addressfield3
Fixed: DLX, MIPS, PowerPC, SPARC
Operation Address Specifier
Addressfield
Operation AddressSpecifier 1
AddressSpecifier 2
Address field
OperationAddress Specifier Address
field 1
Address field 2
Hybrid : IBM 360/370, Intel 80x86
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Summary: ISASummary: ISA• Use general purpose registers with a load-store
architecture. • Support these addressing modes: displacement,
immediate, register indirect.• Support these simple instructions: load, store, add,
subtract, move register, shift, compare equal, compare not equal, branch, jump, call, return.
• Support these data size: 8-,16-,32-bit integer, IEEE FP standard.
• Provide at least 16 general purpose registers plus separate FP registers and aim for a minimal instruction set.
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• Design alternative:
– provide more powerful operations
– goal is to reduce number of instructions executed
– danger is a slower cycle time and/or a higher CPI
• Let’s look (briefly) at IA-32
Alternative Architectures
–“The path toward operation complexity is thus fraught with peril.
To avoid these problems, designers have moved toward simpler
instructions”
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IA - 32• 1978: The Intel 8086 is announced (16 bit architecture)• 1980: The 8087 floating point coprocessor is added• 1982: The 80286 increases address space to 24 bits, +instructions• 1985: The 80386 extends to 32 bits, new addressing modes• 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)• 1997: 57 new “MMX” instructions are added, Pentium II• 1999: The Pentium III added another 70 instructions (SSE)• 2001: Another 144 instructions (SSE2)• 2003: AMD extends the architecture to increase address space to 64 bits,
widens all registers to 64 bits and other changes (AMD64)• 2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds
more media extensions• “This history illustrates the impact of the “golden handcuffs” of compatibility:
“adding new features as someone might add clothing to a packed bag”“an architecture that is difficult to explain and impossible to love”
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IA-32 Overview• Complexity:
– Instructions from 1 to 17 bytes long
– one operand must act as both a source and destination
– one operand can come from memory
– complex addressing modese.g., “base or scaled index with 8 or 32 bit displacement”
• Saving grace:
– the most frequently used instructions are not too difficult to build
– compilers avoid the portions of the architecture that are slow
“what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”