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Transistors, Boolean AlgebraTransistors, Boolean Algebra

Lecture 2Digital Design and Computer Architecture

Harris & HarrisMorgan Kaufmann / Elsevier, 2007

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OverviewOverview

• Review

• Beneath the digital abstraction

• Transistors

• Boolean expressions

• Boolean algebra

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Logic GatesLogic Gates

NOT

Y = A

A Y0 11 0

A Y

BUF

Y = A

A Y0 01 1

A Y

AND

Y = AB

A B Y0 0 00 1 01 0 01 1 1

AB

Y

OR

Y = A + B

A B Y0 0 00 1 11 0 11 1 1

AB

Y

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More Two-Input Logic GatesMore Two-Input Logic Gates

XNOR

Y = A + B

A B Y0 00 11 01 1

AB

Y

XOR NAND NOR

Y = A + B Y = AB Y = A + B

A B Y0 0 00 1 11 0 11 1 0

A B Y0 0 10 1 11 0 11 1 0

A B Y0 0 10 1 01 0 01 1 0

AB

Y AB

Y AB

Y

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Multiple-Input Logic GatesMultiple-Input Logic Gates

NOR3

Y = A+B+C

B C Y0 00 11 01 1

AB YC

A0000

0 00 11 01 1

1111

AND4

Y = ABCD

AB YCD

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Beneath the Digital AbstractionBeneath the Digital Abstraction

• Suppose: 5 V = 1, 0 V = 0

• What does 4.99 V = ?

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Logic Levels and Noise MarginsLogic Levels and Noise Margins

ForbiddenZone

NML

NMH

Input CharacteristicsOutput CharacteristicsVDD

VO L

GND

VIH

VIL

VO H

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Logic Levels and Noise MarginsLogic Levels and Noise Margins

ForbiddenZone

NML

NMH

Input CharacteristicsOutput CharacteristicsVDD

VO L

GND

VIH

VIL

VO H

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DC Transfer CharacteristicsDC Transfer Characteristics

VDD

V(A)

V(Y)

VOH VDD

VOL

VIL, VIH

0

A Y

VDD

V(A)

V(Y)

VOH

VDD

VOL

VIL VIH

Unity GainPoints

Slope = 1

0

(a) (b)VDD / 2

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DC Transfer CharacteristicsDC Transfer Characteristics

A Y

VDD

V(A)

V(Y)

VOH

VDD

VOL

VIL VIH

Unity GainPoints

Slope = 1

0

ForbiddenZone

NML

NMH

Input CharacteristicsOutput CharacteristicsVDD

VO L

GND

VIH

VIL

VO H

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The Static DisciplineThe Static Discipline

Logic Family

VDD VIL VIH VOL VOH

TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4

CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84

LVTTL(Low Voltage)

3.3 (3 - 3.6) 0.8 2.0 0.4 2.4

LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7

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Logic GatesLogic Gates

NOT

Y = A

A Y0 11 0

A Y

BUF

Y = A

A Y0 01 1

A Y

AND

Y = AB

A B Y0 0 00 1 01 0 01 1 1

AB

Y

OR

Y = A + B

A B Y0 0 00 1 11 0 11 1 1

AB

Y

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How do we build logic gates?How do we build logic gates?

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SiliconSilicon

Silicon Lattice

Si SiSi

Si SiSi

Si SiSi

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

Free electron Free hole

n-Type p-Type

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Transistors: nMOSTransistors: nMOS

n

p

gatesource drain

substrate

n

gate

source drain

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Transistors: pMOSTransistors: pMOS

n

gatesource drain

p p

gate

source drain

substrate

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Transistor FunctionTransistor Function

g

s

d

g

d

s

nMOS

pMOS

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CMOS Gates: NOT GateCMOS Gates: NOT Gate

VDD

A Y

GND

N1

P1

NOT

Y = A

A Y0 11 0

A Y

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CMOS Gates: NAND GateCMOS Gates: NAND Gate

A

B

Y

N2

N1

P2 P1

NAND

Y = AB

A B Y0 0 10 1 11 0 11 1 0

AB

Y

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CMOS Gate StructureCMOS Gate Structure

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

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NOR GateNOR Gate

How do you build a two-input NOR gate?

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Other CMOS GatesOther CMOS Gates

How do you build a two-input AND gate?

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Boolean ExpressionsBoolean Expressions

A B Y0 00 11 01 1

minterm

A BA BA B

A B

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Boolean ExpressionsBoolean Expressions

A B Y0 00 11 01 1

minterm

A BA BA B

A B

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Sum-of-Products FormSum-of-Products Form

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Boolean ExpressionsBoolean Expressions

A + BA B Y

0 00 11 01 1

maxterm

A + BA + BA + B

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Product-of-Sums FormProduct-of-Sums Form

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Next TimeNext Time

• Combinational Logic– More Boolean Expressions / Boolean

Algebra– Karnaugh maps– X’s and Z’s