10-bit 1 GS/s Single-Channel Asynchronous SAR ADC

in 28 nm CMOS-Bulk Technology

Ayça Akkaya

Master Thesis

2016

Supervised by

Prof. Yusuf Leblebici

Tuğba Demirci

Microelectronic Systems Laboratory STI/LSM

Electrical and Electronic Engineering Section

5 August 2016

i

Acknowledgements

First of all, I would like to thank Prof. Yusuf Leblebici for giving me the opportunity to

work at LSM during my Master’s education. Thanks to the opportunity that he provided, I

had a chance to involve in various projects including my master’s thesis which helped me

to improve myself and gain a great experience.

I also would like to thank Tuğba Demirci for supervising me and sharing her knowledge

with me during my thesis and all the other projects.

I am thankful to my Turkish friends in Lausanne for enjoyable activities and fun times we

had. Also, I would like to thank all my friends at LSM for providing such a nice working

environment.

I would like to thank Fırat Çelik for always supporting me and encouraging me. Finally, I

would like to thank my parents for all their support and love.

Lausanne, 05.08.2016 Ayça Akkaya

ii

iii

Abstract

Low power consumption is one of the main design goals in recent electronic systems. Many

of those systems require analog-to-digital converters (ADCs) to convert the analog signals

to digital. Among the other ADC topologies, Successive-approximation-register (SAR)

ADCs are known for their low-power consumption and being suitable for deep submicron

CMOS technology nodes.

In this work, 10-bit single channel asynchronous SAR ADC is designed in 28nm CMOS-

Bulk technology. It exploits asynchronous operation in addition to two comparators work-

ing alternately in order to increase the sampling rate. Bootstrapped sampling switches pro-

vides better linearity. Binary weighted capacitive DAC with fractional reference voltages

is used for decreasing the number of capacitors within the DAC. For low-power consump-

tion, DAC utilizes an energy efficient switching sequence. In addition, StrongARM latches

are used as comparators for low-power operation and offset calibration is also included.

The designed 10-bit asynchronous SAR ADC runs at 500 MS/s and consumes 2.674mA at

0.9V power supply and achieves 58.76 dB SNDR and 9.468 bits ENOB near Nyquist rate.

Keywords

ADC, analog-to-digital-converter, SAR, successive approximation, charge redistribution,

asynchronous, alternate comparators, offset calibration.

iv

v

Contents

Acknowledgements ............................................................................................................. i

Abstract .............................................................................................................................. iii

Keywords ........................................................................................................................... iii

Contents .............................................................................................................................. v

List of Figures ................................................................................................................... vii

List of Tables ..................................................................................................................... ix

Introduction ........................................................................................... 1

1.1 Motivation ......................................................................................................... 1

1.2 Thesis Organization .......................................................................................... 2

Theoretical View of SAR ADCs ........................................................... 3

2.1 Traditional SAR ADC Architecture .................................................................. 3

2.2 Error Sources and Performance Metrics in SAR ADCs ................................... 6

Design and Implementation of Asynchronous SAR ADC ............... 11

3.1 Architecture Overview .................................................................................... 11

3.2 Building Blocks............................................................................................... 13

3.2.1 Sampling Switch .................................................................................... 13

3.2.2 Comparator with Offset Calibration ...................................................... 17

3.2.3 Capacitive DAC ..................................................................................... 20

3.2.4 SAR Logic ............................................................................................. 26

3.2.5 Asynchronous Clock Generator............................................................. 28

3.3 Layouts ............................................................................................................ 31

3.4 Simulation Results .......................................................................................... 33

Conclusion ............................................................................................ 39

4.1 Achieved Results............................................................................................. 39

4.2 Future Work .................................................................................................... 39

References ......................................................................................................................... 41

vi

vii

List of Figures

Figure 1.1 FoMs vs. sampling rate plot (the data is taken from [1]). .............. 1

Figure 2.1 Block diagram of a SAR ADC. ..................................................... 3

Figure 2.2 Example SAR conversion (4 bits). ................................................ 4

Figure 2.3 Binary search algorithm of a 4-bit SAR ADC. ............................. 4

Figure 2.4 Charge redistribution SAR ADC (Single ended). ......................... 5

Figure 2.5 Ideal input-output characteristic of a 3-bit ADC and the

quantization noise. .......................................................................................... 6

Figure 2.6 Offset error in an ADC transfer function. ..................................... 7

Figure 2.7 Gain error in an ADC transfer function. ....................................... 7

Figure 2.8 DNL in an ADC transfer function. ................................................ 8

Figure 2.9 INL in an ADC transfer function. ................................................. 9

Figure 2.10 Non-monotonicity and missing code in an ADC transfer

function. .......................................................................................................... 9

Figure 3.1 Asynchronous SAR ADC............................................................ 12

Figure 3.2 Asynchronous SAR ADC timing sequence. ............................... 12

Figure 3.3 Transmission gate as a sampling switch. .................................... 13

Figure 3.4 On-resistance Ron vs. input voltage Vin graph for

Transmission Gate, PMOS and NMOS. ....................................................... 14

Figure 3.5 Bootstrapping scheme, (a) precharging phase, (b) sampling

phase, (c) implementation of gate bootstrapping with ideal switches. ......... 15

Figure 3.6 Bootstrapping waveforms. .......................................................... 15

Figure 3.7 Transistor level implementation of bootstrapped switch. ........... 16

Figure 3.8 StrongARM latch. ....................................................................... 17

Figure 3.9 Transient response of StrongARM latch outputs. ....................... 18

Figure 3.10 Comparator offset calibration circuit. ....................................... 19

Figure 3.11 CDAC topology, (a) CDACP, (b) CDACN. ............................. 21

Figure 3.12 Example waveforms of CDACP and CDACN outputs. ............ 22

Figure 3.13 CDAC topology with constant common mode. ........................ 23

Figure 3.14 Using fractional voltages to adjust the weight. ......................... 24

viii

Figure 3.15 CDAC switches, (a) switch circuit for 2 ≤ N ≤ 8, (b) switch

circuit for N=1, 0. ......................................................................................... 25

Figure 3.16 Error due to incomplete CDAC settling. ................................... 26

Figure 3.17 Memory cell. ............................................................................. 27

Figure 3.18 Memory block used for implementing the SAR logic. ............. 28

Figure 3.19 Asynchronous clock generator circuit. ...................................... 29

Figure 3.20 Adjustable delay circuit for asynchronous clock generation. ... 30

Figure 3.21 Layout of CDAC with bottom plate switches. .......................... 31

Figure 3.22 Layout of the memory block. .................................................... 31

Figure 3.23 Layout of the comparator with calibration differential pair. ..... 32

Figure 3.24 Top-level layout plan. ............................................................... 33

Figure 3.25 DNL and INL graphs................................................................ 34

Figure 3.26 Output Spectrum for fs=500MHz and fin=243.65MHz. ............ 34

Figure 3.27 SNDR vs. input amplitude. ....................................................... 35

Figure 3.28 ENOB vs. sampling frequency. ................................................. 36

Figure 3.29 ENOB vs. input frequency. ....................................................... 36

ix

List of Tables

Table 3.1 SNDR and ENOB values for different delay levels of the

asynchronous clock. ...................................................................................... 33

Table 3.2 Simulation results for different supply voltages. .......................... 36

Table 3.3 SNDR and ENOB vs. RREF for delay level 2. ............................... 37

Table 3.4 SNDR and ENOB vs. RREF for delay level 0. ............................... 37

Table 3.5 Monte Carlo simulation results for unit capacitor. ....................... 37

x

1

Introduction

1.1 Motivation

Digital systems have an advantage of having less sensitivity to noise and being more robust

against process and supply variations compared to analog systems. Therefore, processing

and storage of data is performed in digital domain in most of the modern electronic systems

and analog-to-digital converters (ADCs) are necessary for interfacing digital processors

with the analog signals in real world.

While the technology scaling provides significant performance improvement in digital cir-

cuits, the performance of the analog circuits which employs gain stages does not benefit in

the same way. Successive-approximation-register (SAR) ADCs could be designed in a way

that they do not consume any static currents and do not require any gain stages. Even the

comparator inside a SAR ADC could be implemented in a fully dynamic fashion. There-

fore, they are compatible with low supply voltages and new technologies besides being

power efficient.

Figure 1.1 FoMs vs. sampling rate plot (the data is taken from [1]).

100,0

110,0

120,0

130,0

140,0

150,0

160,0

170,0

180,0

190,0

1,00E+04 1,00E+05 1,00E+06 1,00E+07 1,00E+08 1,00E+09 1,00E+10 1,00E+11

FoM

(d

B)

Sampling frequency (Hz)

SAR

SAR,TI

Flash

Flash,TI

Pipelined

Pipeline,TI

Sigma-Delta

Sigma-Delta,TI

Others

2

SAR ADCs have a wide usage ranging from low-bandwidth applications to high-speed

communication systems. In Figure 1.1, Schreier Figure-of-Merit (FoMS) versus sampling

rate plot for different ADC topologies published in leading IEEE conferences is given [2]

[1]. The definition of FoMS is given below where SNDR is the signal-to-noise-and-distor-

tion ratio, BW is the bandwidth of the signal and P is the power consumption of the ADC.

𝐹𝑜𝑀𝑆 = 𝑆𝑁𝐷𝑅 + 10𝑙𝑜𝑔𝐵𝑊

𝑃

SAR ADC architecture offers power efficient and compact solution; however, its sampling

rate is generally lower compared to other architectures such as flash ADCs. While sampling

rates of SAR ADCs continues to improve with technology scaling, sampling rates of SAR

ADCs with time interleaving technique which uses multiple ADC channels running in par-

allel have reached very high frequencies. As seen in the plot, sampling frequencies of time

interleaved SAR ADCs could reach up to 100Gb/s today. Moreover, recent works have

shown that innovative design approaches, such as asynchronous design and alternate com-

parators, have provided significant improvement in addition to time interleaving [3].

As a result, it is planned to design a 10-bit 1GS/s single-channel asynchronous SAR ADC

in his work. The aim of this work is to apply the innovative approaches used in recent works

and investigate the limits of performance in 28nm CMOS-Bulk technology.

1.2 Thesis Organization

The thesis is organized as follows. In Chapter 2, theoretical view of SAR ADCs is given.

It includes the traditional SAR ADC structure, charge redistribution SAR ADCs in partic-

ular and explains their operation. In addition, error sources and fundamental limitations of

SAR ADCs are given along with the performance metrics. In Chapter 3, general structure

of the 10-bit single-channel asynchronous SAR ADC design is described first, then the

building blocks of the design are examined in detail and the simulation results are given.

Finally, achieved results and future work are given in the Conclusion part.

3

Theoretical View of SAR

ADCs

2.1 Traditional SAR ADC Architecture

Analog-to-digital converters are used for interfacing between analog and digital domains.

Analog signals which are continuous-time and have continuous-amplitude are transformed

into discrete-time and quantized-amplitude signals. In order to obtain discrete-time signals

from continuous-time analog input, value of the input voltage is sampled first. Then, the

sampled voltage value is hold and quantized according to the chosen algorithm.

N-bit DAC

Sample and Hold

N-bitReg.

SARlogic

Analog Input

N-bit Digital Output

Vin

VDAC

Figure 2.1 Block diagram of a SAR ADC.

A/D conversion with successive approximation algorithm has advantages such as reducing

the circuit complexity and power consumption. However, these advantages are obtained in

exchange for lower sampling rate. Successive approximation algorithm uses the previously

determined bit to decide the next significant bit. Thus, N-bit SAR operation requires N-

comparison, in other words N-clock cycles.

Basic SAR ADC architecture which consists of Sample and Hold, Comparator, N-bit SAR

logic, N-bit register and N-bit digital-to-analog converter (DAC) is shown in Figure 2.1.

Sample and hold circuit samples the input voltage at one instance and holds it during the

rest of the conversion. The comparator compares the sampled input voltage Vin and the

output voltage VDAC of the DAC. VDAC successively approximates to the sampled input

voltage. Each bit at the output is acquired successively based on comparator decisions at

each clock cycle one by one starting from the most significant bit (MSB). In order to decide

the MSB, VDAC is set to VREF/2 which is the half of the full-scale voltage, then the first

4

comparison takes place. Depending on the comparator decision CDAC is set to either

VREF/4 or 3VREF/4. If comparator decides Vin<VDAC, then VDAC is set to VREF/4; otherwise,

VDAC is set to 3VREF/4. Similar pattern continues until the least significant bit (LSB) is

obtained. At the end of the conversion, the difference between VDAC and Vin should be less

than VLSB/2 which is equal to VREF/2(N+1). Example VDAC waveform in a SAR conversion

is illustrated in Figure 2.2. In addition, all possible binary search paths for 4-bit resolution

are shown in Figure 2.3.

VREF/2

VREF/4

3VREF/4

VREF

VDAC

Vin

t

Digital Output = 0101

MSB LSB

Figure 2.2 Example SAR conversion (4 bits).

SAR Steps

Figure 2.3 Binary search algorithm of a 4-bit SAR ADC.

There are different SAR architectures with different DAC implementations. Charge redis-

tribution SAR ADC is one of the most common implementations. It employs a charge re-

distribution DAC which consists of a capacitor array controlled by switches and creates an

5

analog output voltage. Generally, the capacitor array inside the capacitive DAC (CDAC)

composed of binary weighted capacitors with one extra dummy capacitor whose size is

equal to the LSB capacitor.

2N Cu 2N-1 Cu 2 Cu Cu. . . Cu

VinVREFGND

SAR logic

Figure 2.4 Charge redistribution SAR ADC (Single ended).

In Figure 2.4, N-bit single ended charge redistribution SAR ADC schematic is shown. It

consists of N-bit binary weighted CDAC, comparator and SAR logic. Sample and Hold

operation is also performed inside the CDAC.

During the sampling phase, all bottom plate switches of the CDAC are connected to the

analog input signal Vin and the top plate switch is connected to GND. After the sampling

phase, top plate switch is disconnected from GND and the output voltage,

𝑉𝐷𝐴𝐶 = −𝑉𝑖𝑛 + 𝑉𝑅𝐸𝐹/2

is generated at the output of the CDAC by connecting the bottom plate of the MSB capac-

itor to VREF. If VDAC<0, it means Vin>VREF/2 and the MSB at the output of SAR ADC is

“1”. Also, bottom plate of the MSB capacitor is kept at VREF and the bottom plate of the

second MSB is set to VREF in the second SAR step. On the other hand, if VDAC>0, it means

Vin<VREF/2 and the MSB at the output of SAR ADC is “0”. In this case, bottom plate of the

MSB capacitor is switched from VREF to GND and the bottom plate of the second MSB is

set to VREF in the next step.

In every SAR step, the capacitor which is previously connected to VREF is either kept con-

nected to VREF or switched back to GND depending on the comparator decision and the

next capacitor is connected to VREF. SAR steps continue until all the bits have been deter-

mined and the VDAC voltage is successively approximated to GND at the end.

Regarding the operation of charge redistribution SAR ADC, each bit decision takes one

clock cycle; in addition, sampling also requires one clock cycle. As a result, (N+1) clock

cycles per conversion are needed for N-bit SAR ADC with bottom plate sampling.

CDAC and comparator are the two critical components of a SAR ADC. Besides, settling

time of the CDAC, comparator decision time and the delay of the SAR logic are the limiting

factors of SAR ADC’s speed. Since the voltage transition at the output of the CDAC is the

largest for the switching of the MSB capacitor, the first SAR step takes longest time to

settle which makes it the main limiting factor on the CDAC settling time.

6

2.2 Error Sources and Performance Metrics in SAR ADCs

Continuous-amplitude signal is changed into finite set of discrete values with quantization.

Analog input voltage range of the ADC is divided into 2N equal intervals in N-bit resolution

ADC and each interval corresponds to one code. Where VFS is the full-scale analog input

range of the ADC, each quantization step is equal to VLSB=VFS/2N. Mid-point of each in-

terval represents all the interval amplitudes within that interval. Therefore, an input voltage

in an interval which is different from the mid-point value causes quantization error in the

conversion since there is finite number of quantization levels. Transfer function of a 3-bit

ADC and quantization error is illustrated in Figure 2.5. Quantization error has a saw tooth

shape and it is bounded by ±VLSB/2.

Dig

ital

Ou

tpu

t

111110101100011010001000

Qu

anti

zati

on

Err

or

+VLSB/2

-VLSB/2

Quantization step

Full-scale analog input

Analog input

Analog input

Figure 2.5 Ideal input-output characteristic of a 3-bit ADC and the quantization noise.

kT/C sampling noise is also a fundamental limit in ADCs [4]. It is dependent on tempera-

ture and the total sampling capacitance. Generally, the noise budget allocated for kT/C

noise is decided to be equal to the quantization noise which is VLSB2/12. Therefore, the

minimum total sampling capacitance of an ADC is limited by kT/C noise.

Signal-to-Noise Ratio (SNR) is the ratio between the signal power and the total noise power

at the output. Both quantization noise and the electronic noises in the circuit affect the SNR

[5]. SNR value also depends on the frequency of the input signal and the amplitude of the

input signal.

7

Signal-to-Noise-and-Distortion Ratio (SNDR) is the ratio between the signal power and the

total noise and distortion power at the output [6]. Effective Number of Bits (ENOB) of an

ADC is derived from SNDRp value which corresponds to the peak SNDR value of the

ADC.

𝐸𝑁𝑂𝐵 = 𝑆𝑁𝐷𝑅𝑝 − 1.76

6.02

Offset error in ADC transfer function is described as the measure of how much the transfer

function is linearly shifted from the ideal transfer function. The effect of offset error on the

transfer function of an ADC is illustrated in Figure 2.6. Offset error does not degrade the

linearity since it is signal independent. However, it could be a problem in time interleaved

architectures when the gain errors of different channels do not match. The charge injected

from sampling switches and comparator offset could be the source of the offset error.

Offset

Analog Input

Dig

ital

Ou

tpu

t

Ideal

Figure 2.6 Offset error in an ADC transfer function.

Analog Input

Dig

ital

Ou

tpu

t

Ideal

Gain Error

Figure 2.7 Gain error in an ADC transfer function.

8

Gain error quantifies the deviation of the slope of the transfer function from the ideal value

which is unity. Parasitic capacitance at the CDAC output is the source of this error. Gain

error decreases the full-scale analog input voltage in SAR ADCs.

Gain error and offset error do not introduce nonlinearity. Depending on the application,

they could be neglected. Generally, errors related to linearity are more essential.

Differential non-linearity (DNL) is a measure of the deviation in the range of input that

corresponds to a particular output code. In staircase characteristic of an ADC, DNL corre-

sponds to the deviation of the step-width from the ideal value. DNL is measured in terms

of LSBs and DNL which corresponds to ith digital output code could be calculated using

the formula below, where Vin(i) is the analog input voltage corresponds to the transition

from (i-1)th digital output code to ith digital output code and VLSB is the ideal spacing

between two successive codes.

𝐷𝑁𝐿𝑖 =(𝑉𝑖𝑛(𝑖 + 1) − 𝑉𝑖𝑛(𝑖))

𝑉𝐿𝑆𝐵𝐼𝐷𝐸𝐴𝐿

− 1

When there is a missing code in an ADC transfer function, DNL value corresponds to that

output code is -1LSB. For an ADC, DNL value cannot be less than this value and it is

guaranteed that there is no missing code in the transfer function of an ADC when the DNL

is within ±LSB range.

Dig

ital

Ou

tpu

t

111110101100011010001000

Ideal LSB size

Analog input

DNL error

DNL error

Figure 2.8 DNL in an ADC transfer function.

Integral non-linearity (INL) is a measure of the deviation of an ADC transfer function from

the straight line which connects the endpoints. INL is also measured in terms of LSBs and

INL value which corresponds to a particular digital output code could be calculated using

cumulative sum of DNL information of previous steps as shown below.

9

𝐼𝑁𝐿𝑘 = ∑ 𝐷𝑁𝐿𝑖

𝑘

𝑖=1

DNL and INL are the measures related to uniformity. Therefore, they are independent of

offset and gain errors.

Dig

ital

Ou

tpu

t

111110101100011010001000

Analog input

INL errors

Figure 2.9 INL in an ADC transfer function.

Monotonicity is a feature of the transfer function of an ADC which implies that the output

code increases or remains the same but does not decrease as the input signal increases. A

non-monotonic ADC transfer function is illustrated in Figure 2.10.

Dig

ital

Ou

tpu

t

111110101100011010001000

Analog input

Non-monotonicity

Missing code

Figure 2.10 Non-monotonicity and missing code in an ADC transfer function.

10

Uncertainty in the sampling clock and unpredictable delay between sampling clock and the

effective sampling are the two factors that may cause jitter in the sampling instants [7].

This jitter causes an error in the value of sampled signal and the amount of error changes

depending on the time derivative of input signal and the amount of jitter.

Mismatches between unit capacitors of CDAC due to process variations in a charge redis-

tribution SAR ADC leads to incorrect charge redistribution. Therefore, it causes errors in

the static behavior of the ADC. Similarly, mismatches in the comparator causes offset er-

rors in comparisons and affects the static behavior.

An error occurring in a certain step of the successive approximation modifies the binary

search path so that the error propagates through all the following successive approximation

steps till the end of the conversion and it cannot be recovered at the end of the search pro-

cess. This error could be related to comparator noise or incomplete settling of CDAC out-

put. Each comparison should be done correctly during the search operation in order to as-

sure the correct operation. As a result, settling should be completed before any comparison

occurs and comparator noise should be low enough not to degrade precision of the ADC.

11

Design and Implementation of

Asynchronous SAR ADC

3.1 Architecture Overview

Building blocks of the asynchronous SAR ADC architecture is shown in Figure 3.1. It is a

differential SAR ADC which has differential input signals. Differential input signals are

sampled into differential capacitive DACs, namely CDACP and CDACN using two boot-

strapped sampling switches which are controlled by external clock signal CKEXT. Differ-

ential architecture has some advantages over single-ended design such as doubling the input

range, suppressing the even order harmonics and providing common-mode rejection de-

pending on the chosen switching sequence, while it has the disadvantage of increasing the

area.

CDAC outputs are directly connected to comparator inputs. There are two comparators

working in an alternating fashion and each of them has an internal offset calibration circuit.

While one of them is being reset the other one makes comparison. Therefore, reset time is

evaluated by making a decision using the other comparator. In addition, these two compar-

ators work asynchronously for faster operation. Depending on the differential input voltage

of the comparator, the time required for comparator to make its decision changes. Compar-

ison takes more time for smaller input voltages compared to larger ones. For example, de-

cisions closer to LSB side are generally harder and slower. The advantage of using asyn-

chronous clocks for the comparators is that we do not have to wait for a full cycle for every

easy decision. Generally, if one of the comparisons is hard, the following ones are easier

because of the nature of the SAR algorithm. Therefore, more time is allocated to harder

decisions and the total time required for each conversion is close to each other’s.

Asynchronous clock generator takes the comparator outputs as its inputs and generates the

asynchronous comparator clocks. Comparator clocks are generated internally using the data

derived from the comparator outputs, which indicates if the comparator decision is done or

not.

Comparator outputs also go to the SAR logic which is a memory in order to generate the

control bits for the bottom plates of the CDACs. SAR logic also gives the SAR ADC out-

puts and keeps them in the memory until the new conversion cycle starts.

12

The timing of the SAR ADC is shown in Figure 3.2. Each conversion cycle starts with the

external clock signal CKEXT. During the interval that CKEXT is logic-1, the input voltage

is sampled into the capacitive DACs. After CKEXT falls, first clock signal, which is CLK1

rises, and then the first comparison starts. After the comparison is done, related CDAC

bottom plates switch and CLK1 falls back. After the switching, CDAC outputs should be

settled and then, CLK2 rises. CLK1 and CLK2 rise and fall back alternately until the last

SAR decision is done. Then, CDAC bottom plates are switched to the reset states with

CRES signal and CDAC outputs are shorted with CKCAL signal via the calibration switch.

After the shorted CDAC voltages are settled, calibration starts. In each conversion one of

the comparators is calibrated and it alternates in the next one. After the calibration, the

conversion cycle is completed and the new conversion starts with the CKEXT signal rising

again. CRES signal is kept in logic-1 during the calibration and sampling phases and it falls

before sampling ends because SAR ADC output bits kept in the memory loop with this

signal in order output bits to be sampled with CKEXT signal.

CDACP

CDACN

Sampling Switch

Sampling Switch

Calibration Switch

CKEXT

CKEXT

VINP

VINN

Asynch. CLK Gen.

CK1

CK2

SAR Logic

(Memory)

OUT

18

18

10

Figure 3.1 Asynchronous SAR ADC.

CKEXT

CLK1

CLK2

CKCAL

CRES

1

2

3 5 7 9

4 6 8 10

cal

Figure 3.2 Asynchronous SAR ADC timing sequence.

13

3.2 Building Blocks

3.2.1 Sampling Switch

The first step of analog to digital conversion is the sampling. In this phase, output voltage

of the sample and hold circuit follows the continuously varying analog input signal and it

holds the voltage value at the end of the sampling phase until the successive approximation

algorithm ends.

Commonly used and a very basic implementation of a sampling switch is a MOS transistor.

However, simple MOS switch suffers from some non-idealities. Considering an NMOS

transistor, its on-resistance Ron is dependent on the input voltage Vin.

𝑅𝑜𝑛 = 𝐿

𝜇𝐶𝑜𝑥𝑊(𝑉𝑖𝑛 − 𝑉𝑇𝐻)

As Vin approaches to VDD-VTH, on-resistance Ron increases significantly and goes to infinity

as it goes to VDD. Therefore, this limits the input voltage range. Similar limitation applies

to PMOS switch but while its on-resistance is finite at high voltages, it increases as Vin

approaches to VTH and goes to infinity as it goes down to GND. Therefore, using PMOS

and NMOS transistors in parallel as a transmission gate as shown in Figure 3.3 solves the

input range limitation problem. However, on resistance of a transmission gate still has a

dependence on the input voltage Vin as shown in Figure 3.4 and this causes distortion on

the signal.

Vin Vout

CLK_B

CLK

Figure 3.3 Transmission gate as a sampling switch.

Moreover, there is another problem with transmission gate as a sampling switch. Inversion

layer charge Qch is stored in the channel of the transistors when they are on, then this charge

is injected through the source and drain of the switch when the transistors are turned off.

Amount of charge injected into the sampling capacitor is not constant at each sampling

because it depends on the input voltage.

𝑄𝑐ℎ = (𝑊𝐿)𝐶𝑜𝑥(𝑉𝐺,𝑜𝑛 − 𝑉𝑇𝐻)

A solution to above issues is to keep VGS voltage of the MOS transistor used as sampling

switch constant to get rid of input voltage dependence using switch bootstrapping tech-

nique. Generally, a precharged capacitance is used for bootstrapping the gate of the NMOS

switch by connecting one terminal of the capacitance to the gate and the other terminal to

the source of the switch. In Figure 3.5, the basic idea behind the bootstrapping is depicted.

14

Bootstrapping consists of two phases: precharging phase and sampling phase. First, boot-

strapping switch is precharged to VDD while the gate of the NMOS switch connected to

GND, so sampling switch is off in this phase. In the sampling phase, precharged capaci-

tance is connected between the source and the gate of the NMOS sampling switch, so sam-

pling switch turns on with its VGS equal to VDD. Since the gate voltage of the sampling

switch always follows the input voltage by a voltage difference of VDD as in Figure 3.6,

VGS voltage of the sampling switch, therefore the on-resistance Ron is always kept constant

during the sampling.

Figure 3.4 On-resistance Ron vs. input voltage Vin graph for Transmission Gate, PMOS and

NMOS.

In Figure 3.5 (c), implementation of bootstrapped switch with ideal switches is shown [8]

[9]. This simple scheme shows that we need at least fıve switches and a capacitor to apply

gate bootstrapping. In precharging phase, bootstrapping capacitor should be precharged to

VDD by turning on S3 and S4, also sampling switch MNSW should be off by turning on S5

connecting the gate of MNSW to GND. In sampling phase, S3, S4 and S5 is turned off and

bootstrapping capacitor is connected between the gate and source terminals of MNSW by

turning on S1 and S2, so MNSW is turned on with VGS=VDD.

15

vdd

Vin Vout

+VDD

-

vdd

Vin Vout

+VDD

-

(a) (b)

vdd

Vin Vout

S1

S3 S4

S2

S5

MNSW

Φpch

Φsamp

Φpch

Φsamp Φpch

(c)

Figure 3.5 Bootstrapping scheme, (a) precharging phase, (b) sampling phase, (c) implementation

of gate bootstrapping with ideal switches.

Figure 3.6 Bootstrapping waveforms.

16

One of the most important things to be considered when choosing a bootstrapped switch

topology is that the gate oxide of the transistors should not be exposed to voltages higher

than VDD. In transistor level implementation in Figure 3.7 [9] [10], there are some extra

switches compared to Figure 3.5 (c) in order to prevent stress on transistors that could

shorten device lifetime, also these extra switches are needed to assure that the gate boot-

strapping works properly in full input range. Considering the worst case for bootstrapping

switch operation happens when Vin is equal to VDD, MN5 will not have 2VDD between its

source and drain thanks to MNT5 in sampling phase. Gates of MN1 and MN6 transistors

are connected to node G instead of constant VDD in sampling phase, so they can be properly

turned on with their VGS voltages equal to VDD. Also, the gate of MP4 is connected to node

G instead of VDD to turn it off in sampling phase because node B reaches to 2VDD and it

causes MP4 to be turned on and discharge the capacitor. In addition, the gate of MP2 should

not be connected to clock signal since voltage difference between its gate and source ter-

minals reaches to -2VDD. Gate-source voltage of MP2 is kept –VDD thanks to MN6 transis-

tor. Finally, bulks of MP4 and MP2 is connected to node B instead of VDD not to forward

bias the well junction. However, well capacitance causes parasitic capacitance to be large

at node B and bigger bootstrapping capacitor is needed to eliminate the effect of parasitic

capacitances at node B.

vdd

VDD

Cboot

CLK_B

CLK

CLK

CLK_B

Vin Vout

MN3 MP6MP4

MN6S

MN6

MN1

MNSW

MNT5 MN5

MP2

A B

G

Figure 3.7 Transistor level implementation of bootstrapped switch.

Bootstrapping technique is a robust solution for better tracking linearity and higher speed.

In addition, bootstrapped sampling switch size could be smaller compared to transmission

gate; therefore, we have less parasitic capacitance, less gain error and higher VLSB in top

plate sampling which relaxes the constraints on noise and minimum unit capacitor size of

the CDAC.

17

3.2.2 Comparator with Offset Calibration

Comparator is one of the key components that requires special attention in a SAR ADC. In

order to provide low-power operation, StrongARM latch circuit is used as a comparator as

shown in Figure 3.8 [10]. It is a fully dynamic comparator topology and it draws current

only while making decision. It consists of a clocked differential pair transistors M1 and M2

that feeds current into a latch which is basically two cross-coupled inverters M3-M5 and

M4-M6, and precharge transistors M7, M8, M9 and M10. The tail transistor MCLK which

is turned on or off by CLK signal supplies current to the differential pair.

Since the comparator in this design is used in a sampled data system, continuous time com-

parator is not needed. Power consumed by StrongARM latch is used for charging and dis-

charging the capacitances and StrongARM latch consumes zero static power. Therefore,

using a dynamic comparator structure provides significant advantage in terms of power

consumption.

vdd

CLK

Vin1 Vin2

Vo1 Vo2

Vc1 Vc2

CLK CLKCLK CLK

CL1

CC1 CC2

CL2

M1 M2

M3 M4

M5 M6M7 M8M9 M10

Figure 3.8 StrongARM latch.

In order to understand the operation of the StrongARM latch better, its operation could be

divided into four parts [11]. In the reset state, CLK signal is low, so MCLK transistor is off.

Internal node capacitances are precharged to VDD. This resets the internal nodes to a fixed

value, so the next decision is not affected by the previous decision. It is important to reset

all four internal node capacitances CC1, CC2, CL1, and CL2 to avoid any memory effect.

In amplification phase, CLK signal is high, so tail transistor MCLK turns on. M1 and M2

transistors discharges the CC1 and CC2 while input voltages Vin1 and Vin2 are applied to the

18

gates of M1 and M2. Currents flowing through M1 and M2 are proportional to the applied

input voltages. The differential input voltage (Vin1-Vin2) creates a voltage difference be-

tween the nodes VC1 and VC2 with a voltage gain. Relationship between differential input

voltage is given below where gm1,2 is the transconductance of differential pair transistors

M1 and M2.

|𝑉𝐶1 − 𝑉𝐶2| = (𝑔𝑚1,2|𝑉𝐶1 − 𝑉𝐶2|/𝐶𝐶1,𝐶2)𝑡

Propagation phase starts when the internal node voltages VC1 and VC2 fall to VDD-VTHN and

cross coupled NMOS transistors M3 and M4 turn on. Then, output nodes VO1 and VO2 also

start to be discharged.

Regeneration phase which is the last phase starts when the output voltages VO1 and VO2 fall

to VDD-VTHP causing M5 and M6 to turn on. Then, differential voltage is regenerated at the

output nodes, and one of the outputs goes to VDD while the other one goes to GND thanks

to the positive feedback. Regenerated output voltages control the latch and there is no static

power. Waveforms of comparator output signals are shown in Figure 3.9.

Figure 3.9 Transient response of StrongARM latch outputs.

Analyzing the operation of StrongARM latch is important to understand the effect of mis-

matches on the comparator offset. Main source of the offset is the mismatch between the

differential pair transistors because it directly creates imbalance between the differential

currents that discharges the internal node capacitances. Moreover, mismatch between the

internal node capacitances is also important in terms of offset since the comparator opera-

tion based on discharging the internal node capacitances by certain amounts. Assuming the

threshold voltages of PMOS and NMOS is both equal to VTH, the offset due to capacitance

mismatches only could be expressed as below [12]:

19

𝑉𝑂𝑓𝑓𝑠𝑒𝑡 =𝑉𝑇𝐻

(1 − 𝐶𝐶/𝐶𝐿) ∆𝐶𝐿 + 2∆𝐶𝐶

𝐶𝐿

Mismatch of the internal nodes should be considered while drawing the layout. However,

making the design perfectly symmetrical is not enough. Process mismatches also causes

offset. Moreover, there are two comparators running in an alternating fashion and compar-

ators having different offsets cause non-linearity in the ADC characteristic. Therefore, off-

sets of the comparators should be minimized by calibration.

VREF VCAL

Vc1

Vc2

CLKvdd

vdd

CCAL

VCAL

ΦCAL

ΦCAL_B

ΦCAL

ΦCAL_B

COMP_OUTP

COMP_OUTN

CSW

CSW

M11 M12

Figure 3.10 Comparator offset calibration circuit.

Calibration circuit is shown in Figure 3.10 [3]. There is a second differential pair to com-

pensate the differential imbalance in StrongARM latch. Gate of M11 is connected to refer-

ence voltage VREF and the gate of M12 is connected to calibration voltage VCAL. By adjust-

ing VCAL, imbalance of StrongARM latch could be compensated. VCAL voltage value is

adjusted using a negative feedback loop. After each conversion, calibration phase starts and

calibration voltage VCAL is refreshed. In calibration phase, zero differential input voltage is

applied between the inputs of comparator. In order to do that, comparator inputs are shorted

via calibration switch. Depending on the corresponding output decision which is decided

by the polarity of the mismatch, the charge is either added or subtracted from the CCAL

capacitor. The amount of the charge added or subtracted depends on the ratio between ca-

pacitors CSW and CCAL. In addition, the amount of this charge should be kept small enough

that the change in VCAL voltage is very small to assure the residual offset is negligible when

VCAL value is settled. As the ratio CSW/CCAL decreases, residual offset decreases. Resulting

VCAL voltage is applied to gate of M12 to calibrate the offset. As the offset increases, the

difference between VREF and VCAL increases.

20

Calibration switch should be robust; however, the voltage that this switch should pass is

around the common mode voltage and on-resistance of a transmission gate type switch is

high at that voltage. Therefore, the performance of the transmission gate is not enough for

this purpose. Bootstrapping the gate could increase the performance of that switch. On the

contrary, the bootstrapped switch should be completely symmetrical not to degrade the

matching of differential operation; in addition, the charge in CDAC capacitors should be

reserved. Hence, using the bootstrapped topology in Figure 3.7 which is used for the sam-

pling switches does not satisfy these requirements. Since the input voltage of that switch is

always very close to the common mode voltage, the NMOS switch could be bootstrapped

with the fixed common mode voltage. The bootstrapped topology shown in Figure 3.7

could be used with a small modification: the reference voltage for gate bootstrapping is

taken from a voltage source instead of the input node. In addition, the switch size gets

smaller with bootstrapping and gain error decreases since the parasitic capacitance that the

calibration switch adds to the CDAC output decreases.

There is a fixed time interval for calibration phase. Since differential input voltage of the

comparator is zero in the calibration phase, this comparison could take more time. In some

calibration phases, calibration may not be completed, but skipping the refreshing of the

calibration capacitance time to time is not a problem unless it happens very often and lets

the leakage current cause offset errors. Therefore, the duration of the calibration phase

should be decided regarding this issue.

3.2.3 Capacitive DAC

Binary weighted capacitive DAC structure used in the design is shown in Figure 3.11. It

uses Set-and-Down principle [13] and it is a slightly different version of the CDAC topol-

ogy in [3]. First comparison occurs right after the top plate sampling, before any switching

action happens, so 9-bit CDAC is used instead of 10-bit. Therefore, it provides area, speed

and power consumption advantage. Also, comparator outputs are directly used in switching

without any extra logic and delay coming from that logic. Another advantage is that less

power is consumed in switching because only one switching occurs in each cycle.

21

16Cu

VREF

PN8

16Cu

VREF

PP8

8Cu

VREF

PN7

8Cu

VREF

PP7

4Cu

VREF

PN6

4Cu

VREF

PP6

2Cu

VREF

PN5

2Cu

VREF

PP5

Cu

VREF

PN4

Cu

VREF

PP4

Cu

VREF

PN3

Cu

VREF

PN2

Cu

VREF/2

PN1

Cu

VREF/4

PN0

Cu Cu Cu

VDACP

16Cu

VREF

NN8

16Cu

VREF

NP8

8Cu

VREF

NN7

8Cu

VREF

NP7

4Cu

VREF

NN6

4Cu

VREF

NP6

2Cu

VREF

NN5

2Cu

VREF

NP5

Cu

VREF

NN4

Cu

VREF

NP4

Cu

VREF

NN3

Cu

VREF

NN2

Cu

VREF/2

NN1

Cu

VREF/4

NN0

Cu Cu Cu

VDACN

(a)

(b)

Figure 3.11 CDAC topology, (a) CDACP, (b) CDACN.

There are two replicas of the same CDAC circuit for differential operation. CDACP is con-

nected to positive input of two asynchronous comparators and CDACN is connected to the

negative inputs of them. When switching operation of CDACP create a voltage change in

the output by +ΔV, -ΔV voltage change should happen at the output of CDACN by keeping

the common mode constant except for the switching of last four capacitors as shown in

Figure 3.12. Since last four capacitors at the LSB side only have the bottom capacitor array,

switching of them causes a change in the common mode. However, this common mode

change is very small, because the weight of these last four capacitors is small; therefore,

the voltage change they could create at the output is small. Normally, common mode of the

comparator has an effect on the comparator performance, but small common mode change

does not have a significant effect on the comparator performance in our case.

22

Figure 3.12 Example waveforms of CDACP and CDACN outputs.

During the top plate sampling, bottom plates of the capacitors are connected to VREF for the

top arrays, GND for the bottom arrays. After sampling is over, first comparison starts. If

comparator decides VP is higher than the output voltage of VN at the (9-N)th decision

where 4 ≤ N ≤ 8, then PP<N> goes from VREF to GND and NN<N> goes from GND to

VREF while PN<N> and NP<N> switches remain still. This switching causes VP to decrease

and VN to increase by the same amount keeping the common mode constant. If comparator

decides the other way around, output voltage of VN is higher than the output voltage of

VP, then NP<N> goes from VREF to GND and PN<N> goes from GND to VREF while

PP<N> and NN<N> switches remain still. Therefore, only one of them, top or bottom one

switches while the other one is kept the same, considering one CDAC and first five switch-

ing action. After the settling of the DAC output, the next comparison takes place. Again,

either top capacitor or the bottom one switches depending on the comparator output in the

next switching. Similar pattern is repeated until the last four LSB capacitor switch.

There is only bottom array for last four capacitors. If comparator decides VP is higher than

the output voltage of VN at the (9-N)th decision where 6 ≤ N ≤ 9, then NN<N> goes from

GND to VREF while PN<N> remains still. This switching causes VN to increase and VP

not to change; therefore, common mode changes. If comparator decides the other way

around, VN is higher than the output voltage of VP, then PN<N> goes from GND to VREF

while NN<N> remains still. At each step, only one of the CDAC outputs could be increased

while the other one is kept the same. Since either VP or VN is increased, compared to

23

increasing one of them and decreasing the other in the first five switching operation, weight

of the last four capacitances is half of the first five capacitances comparing the capacitances

with the same size. Therefore, absence of the top array for the last four bits decreased the

area. As seen in Figure 3.13, total number of capacitors is more than double compared to

the topology with constant common mode in Figure 3.11.

32Cu

VREF

PN8

32Cu

VREF

PP8

16Cu

VREF

PN7

16Cu

VREF

PP7

8Cu

VREF

PN6

8Cu

VREF

PP6

4Cu

VREF

PN5

4Cu

VREF

PP5

2Cu

VREF

PN4

2Cu

VREF

PP4

Cu

VREF

PN3

Cu

VREF

PN2

Cu

VREF/2

PN1

Cu

VREF/4

PN0

Cu Cu Cu

VDACP

Cu

VREF

PP4

Cu

VREF

PP4

Cu

VREF/2

PP4

Cu

VREF/4

PP4

Cu Cu Cu

Figure 3.13 CDAC topology with constant common mode.

Using fractional reference voltages is a useful method to reduce the total number of capac-

itors [3]. Aside from the size of the capacitor, the voltage difference applied to the bottom

plate of the capacitor also affects the weight of that switching action. For example, chang-

ing the bottom plate voltage of a capacitor Cu by ΔVbp changes the CDAC output voltage

by ΔVDAC as shown in Figure 3.14 (a), while changing the bottom plate voltage of the

capacitor sized Cu/2 by ΔVbp changes the CDAC output voltage by ΔVDAC/2 as shown in

Figure 3.14 (b). This is the method used in traditional binary weighted CDAC. Another

method to get ΔVCDAC/2 voltage change at the output of CDAC by keeping the capacitor

size the same is to reduce the bottom plate switching voltage by ΔVbp/2. Therefore, the

resulting CDAC output voltage change is the same for Figure 3.14 (b) and (c). As a side

note, initial bottom plate voltages of the CDAC do not have any effect on the weight of the

capacitors; only the voltage difference between the first and last state matters. Using this

method, the sizes of the last three capacitors are kept the same and their bottom plate volt-

ages are changed in switching by VREF, VREF/2 and VREF/4 respectively. Since fractional

voltages directly affect the CDAC output voltage change, the precision of fractional volt-

ages is important.

Another method used for reducing the total number of capacitors is using unit sized capac-

itors in series to reduce the capacitor size by half. This method used only for last three

switching and provide a huge decrease in the total number of unit capacitors when com-

bined with the fractional reference voltages. Disadvantage of using capacitors in series is

that good matching of the series capacitors with the ones which are not in series is hard to

achieve. Parasitic capacitance on the middle node of the series capacitance causes its weigh

to decrease compared to other capacitances and it affects the precision negatively. There-

fore, it is another point that should be considered in the design phase carefully.

24

Ct Cu

Vinit

VDAC

Vinit+ΔVbp

Ct Cu

Vinit

VDAC+ΔVDAC

Vinit+ΔVbp

(a)

Ct Cu/2

Vinit

VDAC

Vinit+ΔVbp

Ct Cu/2

Vinit

VDAC+ΔVDAC/2

Vinit+ΔVbp

(b)

Ct Cu

Vinit

VDAC

Vinit+ΔVbp/2

Ct Cu

Vinit

VDAC+ΔVDAC/2

Vinit+ΔVbp/2

(c)

Figure 3.14 Using fractional voltages to adjust the weight.

CDAC switches are shown in Figure 3.15. Simple inverter type switches are used for

switches numbered 2 ≤ N ≤ 8 as in Figure 3.15 (a). NMOS transistor is used when switching

to GND and PMOS transistor is used when switching to VREF. Complementary of the con-

trol signal is not needed since complementary transistors are used for switching between

two states which makes the switches simpler and smaller. For the last two switches, inverter

type switch is not enough since switching happens between GND and VREF/2 or VREF/4.

Therefore, NMOS transistor is used for switching to GND and transmission gate for switch-

ing to VREF/2 and VREF/4 as shown in Figure 3.15 (b). Switch resistances should be low

enough to minimize the switching and the settling time of the CDAC.

25

Vout

VREF

Vsw Vout

VREF/2

Vsw

Vsw_B

(a) (b)

Figure 3.15 CDAC switches, (a) switch circuit for 2 ≤ N ≤ 8, (b) switch circuit for N=1, 0.

While deciding the unit capacitor size kT/C sampling noise limitation should be considered.

Using the equation below, total sampling capacitor size to keep kT/C noise less than quan-

tization noise 𝑉𝐿𝑆𝐵/√12 could be derived [4]. In binary weighted CDACs, normally the

calculated minimum unit capacitor size is so small that it is not restrictive for the design.

However, sampling noise restricts the minimum unit capacitor size in this CDAC topology

since the methods mentioned above are used for reducing the total number of capacitors. If

we assume that full scale input voltage VFS is 700mV, minimum unit capacitor size is found

as approximately 2fF at 100 °C for 9-bit CDAC design in Figure 3.11. However, unit ca-

pacitor size Cu determined is 2.4fF since it is the closest available MOM capacitor size

satisfying the limitation. Another issue related to the unit capacitor size is that the matching

degrades as the capacitor size gets smaller. On the other hand, as the unit capacitor size

gets larger, the bandwidth gets lower.

𝑘𝑇

𝐶𝑡𝑜𝑡=

(𝑉𝐹𝑆/2𝑁)2

12

Parasitic capacitances at the output of the CDAC causes the voltage change on that node

after each SAR step to be smaller than the ideal case without affecting the ratio of the

voltages. This introduces gain error to the ADC characteristic. Having gain error is unde-

sirable since it reduces VLSB. As a result, noise constraints gets harder to achieve and min-

imum unit capacitor size to satisfy kT/C sampling noise limitation increases.

In order to avoid errors coming from incomplete CDAC settling, maximum CDAC output

settling error should be VLSB/2. Therefore, asynchronous clocks should be delayed until

CDAC outputs settle if needed. Settling error tends to occur especially when the second

comparison is a critical one with the differential input voltage of the comparator that has

opposite sign compared to the previous decision as illustrated in Figure 3.16. Because, the

largest transition occurs at the first step and settling requires more time at that step.

26

CLK

VDACP

VDACN

Figure 3.16 Error due to incomplete CDAC settling.

3.2.4 SAR Logic

SAR logic generates control bits for CDAC switches using comparator decisions. In this

design, comparator outputs are directly used for providing the control bits of the CDAC

without needing any additional logic for logic manipulation.

The delay of the SAR logic should be minimized since we want CDAC output to be settled

as soon as possible. Implementing the SAR logic using memory block instead of a state

machine structure, which is generally used in traditional SAR ADCs, allows faster opera-

tion. Structure of the SAR memory block is shown in Figure 3.18 [3]. In this structure, there

are two memory cells which is shown in Figure 3.17 in each memory block. Both differen-

tial outputs of the comparator are written into two separate memory cells after each decision

since they both needed for controlling bottom and top capacitor arrays of the CDAC. Even

numbered memory cells are connected to the output of the first comparator while the odd

numbered ones are connected to the output of the second comparator.

The operation of the memory cell is based on dynamic logic. All the memory cells are reset

to logic-0 with the rising edge of the CRES signal just before the calibration. Since the

DCAP signals go to the bottom plate switches of the CDACs, CRES signal is used for

resetting the CDAC bottom plates and DCAP signal stays at logic-0 until the SAR operation

starts. While CRES is logic-1, the comparator decision which corresponds to the ADC out-

put bit is kept in the memory loop. After CRES goes down, the comparator decision is

written into the cells one by one. Therefore, each memory cell should be activated with

CWR signal when its turn comes. CWR signal allows comparator output DCOMP to pass

through the gate of PMOS that pulls the memory output to logic-1 when the corresponding

comparator output is logic-0. If the comparator output DCOMP is logic-1 then the PMOS

is not turned on and the memory output stays at logic-0. The loop at the output keeps the

value of DCAP signal during the CDAC reset phase and the calibration phase until the next

conversion starts. DMEM_B signals corresponds to the SAR ADC output bits. CMRES_B

signal is used for resetting the loop and SAR ADC output bits before the next conversion.

27

vdd

CWR

CWR_B

DM

EM_B

CMRES_B

CRES_B CRES

vdd

vdd

CRESCWR_B

CWR

DCAP

DCOMP

Figure 3.17 Memory cell.

Comparator decisions should be written into separate memory cells one by one. Therefore,

CWR signals for each cell should be generated depending on the previous cell’s CWR sig-

nal. CWR signal of the first memory cell is activated by CKEXT_B after the sampling ends.

When the write operation of a specific memory cell ends, either DMEMP_B or DMEMN_B

should be logic-0 while the other one is logic-1. Using those signals CDEC signal which

indicates the write operation has ended is generated. When CDEC signal is logic-0, CWR

signal of that cell is deactivated and CWR signal of the next cell gets activated.

When differential input voltage of the comparator is very small, both comparator outputs

might go down together and then one of them goes back to VDD. However, if amount of the

voltage drop is enough to trigger the buffers at the output of the comparator, then wrong

data could be written into the memory. This problem causes switching of the capacitor

which should not be switched. As a result, serious errors which cannot be fixed later might

happen in the successive approximation. In order to prevent this, simple logic that takes

comparator outputs as an input and does not let both of its outputs to go down together to

GND is added after the comparators.

28

Memory<0>

DCAPP

DCAPN

DMEMP_B

DMEMN_B

DCOMPPDCOMPN

CWRCRESCMRES

CWR<0>

DCAPP<0>

DCAPN<0>

CDEC<0> CWR<0>

Memory<1>

DCAPP

DCAPN

DMEMP_B

DMEMN_B

DCOMPPDCOMPN

CWRCRESCMRES

CWR<1>

DCAPP<1>

DCAPN<1>

CDEC<1> CWR<1>

Memory<2>

DCAPP

DCAPN

DMEMP_B

DMEMN_B

DCOMPPDCOMPN

CWRCRESCMRES

CWR<2>

DCAPP<2>

DCAPN<2>

CDEC<2> CWR<2>

Memory<3>

DCAPP

DCAPN

DMEMP_B

DMEMN_B

DCOMPPDCOMPN

CWRCRESCMRES

CWR<3>

DCAPP<3>

DCAPN<3>

CDEC<3> CWR<3>

CK

EXT_

BCK

EXT_

B

CR

ES

.

.

.

.

.

.

DC

OM

PP

1

DC

OM

PN

1

DC

OM

PP

2

DC

OM

PN

2

Figure 3.18 Memory block used for implementing the SAR logic.

3.2.5 Asynchronous Clock Generator

Asynchronous clock signals of the comparators are generated internally using the circuit

illustrated in Figure 3.19. Clock signal generation is controlled by COMP1 and COMP2

signals. These signals indicate if the comparator has made its decision or not. When com-

parator decision is completed, one of the outputs goes from VDD to GND while the other

one stays at VDD. Therefore, COMP1 signal should be logic-1 if the first comparator made

its decision or logic-0 if it is not.

During the sampling, reset and calibration phases, both clock signals are kept at GND by

NMOS transistors which are controlled by CKEXT and CKRES signals. After the sampling

phase, first comparator clock should rise. INIT1 pulse is used for initiating the first clock.

After sampling phase has ended, INIT1_B goes to logic-0 and the first clock rises, then

INIT1_B goes back to logic-1. Until the comparison is done and COMP1 signal goes to

logic-1, CLK1 is kept floating to pull it down faster with COMP1 later. As soon as COMP1

rises, CLK1 goes down. COMP1 also causes CLK2 to rise. However, rising edge of CLK2

is delayed in order to prevent kickback noise to affect the next comparison. Therefore,

asynchronous clock signal should rise after the previous clock signal completely goes down

29

to GND and the clock signals should not overlap. After CLK2 rises, the same operation

continues until the last SAR decision is made. CDEC_LAST signal prevents

COMP1/COMP2 signals to pull CLK2/CLK1 up, so clock generation is stopped. Then,

CDAC is reset and during this phase, CLK1 and CLK2 is kept at GND. In calibration phase,

only one of the clock signals rises because only one of the comparators is calibrated at each

conversion and it always alternates. In order to generate the clock signal for calibration,

corresponding PMOS transistor is turned on by CAL1_B/CAL2_B to pull CLK1/CLK2 up.

After the calibration, sampling phase starts and clock signals are kept at GND.

A comparison should start after the CDAC output settles in order to avoid settling errors.

Therefore, COMP1/COMP2 signals that pulls the CLK2/CLK1 signals to VDD are delayed

by an adjustable delay circuit in order to assure the settling condition. Adjustable delay

circuit is shown in Figure 3.20. It is controlled by 2 control bits and provides 4 different

delay options.

Adjustable DelayCOMP2

vdd

VDD

COMP1 CKEXT CKRES

CAL1_BINIT1_BCDEC_LAST

COMP1

CLK1 COMP_CLK1

COMP1COMP_OUTP1

COMP_OUTN1

COMP2COMP_OUTP2

COMP_OUTN2

Adjustable DelayCOMP1

vdd

VDD

COMP2 CKEXT CKRES

CAL2_BINIT2_BCDEC_LAST

COMP2

CLK2 COMP_CLK2

Figure 3.19 Asynchronous clock generator circuit.

30

vdd

D0

D0_B

vdd

(D1|D2|D3)_B

D1|D2|D3

vdd

D1

D1_B

vdd

(D2|D3)_B

D2|D3

vdd

D2

D2_B

vdd

D3

D3_B

IN OUT

Figure 3.20 Adjustable delay circuit for asynchronous clock generation.

31

3.3 Layouts

Layouts of CDAC with bottom plate switches, memory block and comparator is drawn.

Top-level layout plan of the single-channel asynchronous SAR ADC is given in Figure

3.24. In this layout plan, the blocks of which layouts have not been drawn yet are illustrated

as empty boxes with the estimated layout sizes.

Figure 3.21 Layout of CDAC with bottom plate switches.

Figure 3.22 Layout of the memory block.

32

Figure 3.23 Layout of the comparator with calibration differential pair.

33

Figure 3.24 Top-level layout plan.

3.4 Simulation Results

The layouts of CDACs with bottom plate switches, memory block and the comparator have

been drawn and their extracted views have been included in the simulations of which results

are given in this part.

Table 3.1 shows SNDR and ENOB values obtained for different adjustable delay levels of

the rising edges of the asynchronous clocks in given conditions. Increasing delay level al-

lows CDACs to have more time for their outputs to settle before the comparison. There is

not a dramatic change between the results obtained for different delay levels because

CDAC outputs settle fast enough. However, the difference could be more significant after

top-level layout is completed and new parasitic capacitances added to the simulations.

Supply voltage 0.9 V

Sampling frequency 500 MS/s

Input frequency 243.65 MHz

Input amplitude 0.72 Vpp

Input common mode 0.45 V

Temperature 100 °C

Async. CK delay level 0 1 2 3

SNDR (dB) 58.21 58.58 58.78 58.75

ENOB (bits) 9.376 9.439 9.471 9.466

Table 3.1 SNDR and ENOB values for different delay levels of the asynchronous clock.

34

Figure 3.25 DNL and INL graphs.

Figure 3.26 Output Spectrum for fs=500MHz and fin=243.65MHz.

35

Simulations of which results are given below has been run using the values given in Table

3.1 and setting the delay level to 2. Only the variables indicated are swept.

In Figure 3.25, INL and DNL plots are given. DNL value is between -0.3LSB and +0.7LSB,

and INL value is between +0.8LSB and -0.8LSB without any missing codes or non-mono-

tonicity.

Output spectrum of the SAR ADC is given in Figure 3.26 and it shows that 9.468 bits

ENOB and 58.76 dB SNDR is acquired for 243.65 MHz 720 mVpp sinusoidal input signal.

In order to decide the input range, ENOB values for different input amplitudes are obtained

and plotted. As seen in Figure 3.27, SNDR increases as the amplitude increases until the

amplitude of the sinusoidal input signal reaches to 370mV. After that value, SNDR starts

to decrease drastically because of the distortion caused by clipping.

Figure 3.27 SNDR vs. input amplitude.

The response to the variation of sampling frequency is presented in Figure 3.28. Since, this

design is asynchronous, changing the sampling frequency does not affect the internal asyn-

chronous clocks. As the sampling frequency increases, some of the SAR steps could remain

incomplete starting from the LSB and this is the reason why ENOB starts to decrease.

ENOB values obtained by sweeping the frequency of the input signal is plotted in Figure

3.29.

20,00

25,00

30,00

35,00

40,00

45,00

50,00

55,00

60,00

65,00

0 50 100 150 200 250 300 350 400 450 500

SND

R (

dB

)

Input Amplitude (mV)

36

Figure 3.28 ENOB vs. sampling frequency.

Figure 3.29 ENOB vs. input frequency.

Sampling frequency 476 MHz 500 MHz 555 MHz

Supply voltage 0.85 V 0.85V 0.9V 0.95V 0.95V

Input amplitude 340 mV 340 mV 360 mV 380 mV 380 mV

SNDR 58.66 dB 54.86 dB 58.76 dB 58.75 dB 58.96 dB

ENOB (bits) 9.451 8.821 9.468 9.467 9.5

Current consumption 2.365 mA 2.45 mA 2.674 mA 2.92 mA 3.134 mA

Table 3.2 Simulation results for different supply voltages.

7,5

8

8,5

9

9,5

10

440 460 480 500 520 540 560 580 600

ENO

B (

bit

s)

Sampling frequency (MHz)

9,44

9,46

9,48

9,5

9,52

9,54

9,56

9,58

9,6

9,62

9,64

9,66

0 100 200 300 400 500 600

ENO

B (

bit

s)

Input frequency (MHz)

37

Results shown in Table 3.2 are derived with the supply voltages 50 mV above and below

the nominal value which is 0.9 V. ENOB is lower for 0.85 V supply voltage because the

SAR operation gets slower and it cannot be completed properly for 500 MHz sampling rate.

For 0.95 V supply voltage SAR operation is faster and at even 555 MHz SAR operation is

properly completed.

RREF

0 Ω 5 Ω 10 Ω

SNDR (dB) 58.76 58.83 58.79

ENOB (bits) 9.468 9.48 9.473

Table 3.3 SNDR and ENOB vs. RREF for delay level 2.

RREF

0 Ω 5 Ω 10 Ω

SNDR (dB) 58.21 58.17 54.23

ENOB (bits) 9.376 9.369 8.715

Table 3.4 SNDR and ENOB vs. RREF for delay level 0.

In order to simulate the effect of non-ideal reference voltage on SNDR and ENOB, RREF

resistors are connected in series to the ideal voltage sources which generate VREF, VREF/2

and VREF/4. Simulation results for different values of RREF resistance when the delay level

is chosen as 2 is given in Table 3.3. Addition of resistors causes glitches on reference volt-

ages in switching instances. However, increasing RREF value does not have a significant

effect on ENOB and SNDR since reference voltage settles back to a value which is very

close to its ideal value before the comparison starts. Therefore, same simulations have been

repeated for delay level 0 and results are shown in Table 3.4. In this results, effect of

glitches caused by RREF is more significant because the time allowed for VREF to settle

back is less than the case with delay level 2.

Mismatch of CDAC unit capacitors due to process variations changes the static behavior

of the SAR ADC. Variation of the unit capacitance value has been simulated by running

Monte Carlo simulations and results are shown in Table 3.5. In order to find out the effect of

mismatch on ENOB and SNDR, the mismatch simulation has been run by adding 12 aF parasitic

capacitors in parallel to all MSB unit capacitors. As a result of this simulation, ENOB is found as

8.82 bits and SNDR as 54.89 dB.

Minimum Maximum Mean Sigma

2.41 fF 2.467 fF 2.439 fF 11.97 aF

Table 3.5 Monte Carlo simulation results for unit capacitor.

To sum up, SAR operation is properly completed at typical process corner, nominal 0.9V

supply voltage and 100 °C with 450mV input common mode by achieving 9.468 bits ENOB

and 58.76 dB SNDR and it consumes 2.674mA current in average at 500MS/s sampling

rate.

38

39

Conclusion

4.1 Achieved Results

Transistor level design of 10-bit asynchronous SAR ADC has been done in 28nm CMOS-

Bulk technology. Layouts of CDAC with bottom plate switches, SAR logic (memory) and

comparator have been drawn and their extracted views are included in the simulations.

Targeted sampling rate was 1Gb/s in this project; however, the sampling rate achieved is

500 MS/s. As a result, the designed 10-bit asynchronous SAR ADC runs at 500 MS/s and

consumes 2.674mA at 0.9V power supply and achieves 58.76 dB SNDR and 9.468 bits

ENOB near Nyquist rate.

4.2 Future Work

The main limitation of speed is the settling time of the CDAC in this design. Therefore, it

is possible to improve the speed by introducing redundancy. Redundancy enables us to

recover the incomplete settling errors during the successive approximation and errors due

to noise; therefore, it allows faster SAR operation. Using redundancy, sampling rate of the

one-channel design could be increased. In this case, it is beneficial to improve the delay of

the asynchronous clock generator in order to maximize the speed.

Voltage references should be designed for providing fractional voltages to CDAC. These

references should be power efficient and have low output impedance.

There should be a delay line to provide different phases of the external clock. Resetting or

activation of different blocks within the SAR ADC is operated using the clock signals gen-

erated from the phases taken from this delay line.

In order to observe the effect of process and temperature variations, further simulations

should be run.

Noise is an important bottleneck in high resolution SAR ADC designs. Therefore, noise of

the comparator should be investigated in detail. In addition, the effect of common mode on

noise and the overall ADC performance should be simulated.

Finally, the layouts of the remaining blocks should be completed.

40

41

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