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8/2/2019 10 Memory Organization
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Lecture 10: Memor Or anization
Direct Map
M. Safayani
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Localit
empora oca y: you use some a a recen y, you
will likely use it again
Spatial locality: if you used some data recently, you
will likely access its neighbors
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Memor Hierarch
e as er memor es are more expens ve per an
the slower memories and thus smaller.
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Memor Hierarch
s you go ur er, capac y an a ency ncrease
Registers1KB
1 cycle
instructionCache32KB
L2 cache2MB
15 c cles
Memory1GB
300 cyclesDisk
80 GB
2 cycles 10M cycles
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Cache
y o cac es wor
assume that there are two-level memory
No hierarchy: average access time for data = 300 cycles
32KB 1-cycle L1 cache that has a hit rate of 95%:average access time = 0.95 x 1 + 0.05 x (301)
= cyc es
Main MemoryCPU
512 x 8Wordaccess
Blocktransfer
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Accessin the Cache direct-ma ed
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Accessin the Cache direct-ma ed
122000000
234000 1220
77700000
3450
456077701
00002 5670
671077727777
Cache
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7Main memory
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Exam le direct-ma ed
22(10110)
22(10110)
26(11010)
3 (00011)16(10000)
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Exam le direct-ma ed
22(10110)
22(10110)
26(11010)
3 (00011)16(10000)
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Direct-ma ed
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Direct-ma ed
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Exam le Bits in a cache
-data and 4-word blocks, assuming a 32-bit address?
um er o oc s=Number of bits in each block:128 bitsTag=32-10-2-2
Valid bit=1Total cache size:
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Com utin Cache blocks
=
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Direct-ma ed
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Handling Cache Misses
1. Send the original PC value (current PC 4) to the memory.
2. Instruct main memory to perform a read and wait for the memory tocom lete its access.
3. Write the cache entry, putting the data from memory in the data,
ALU) into the tag field, and turning the valid bit on.
. ,the instruction, this time finding it in the cache.
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Handling Write
1. Write-through
Example:10% of the instructions are storesthe CPI without cache misses was 1.0100 extra cycles on every write
CPI becomes: 1.0 + 100 * 10% = 11
2. Write-back
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