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MEM
MEM
AGP
AGP
MAC
MEM
MEM
AGP
AGP
MUL
read[0:7]
read[0:7]
write[8:15]
a[0:7]
b[0:7]
read[0:7]
read[0:7]
write 8
a[0:7]
b[0:7]
dot(a,b)
c[0:7]
c[i]=a[i] b[i]
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+
-
fa
fbcb
ca
fout
levelgen
network stage satellite stage
max
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+
- +-
0
cb
ca
network stage satellite stage
fa
fb+
-
typeA
typeB
max(typeA,typeB) - level
max
gen
fout
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SATELLITE
CORE
INPORT1 Data
INPORT2 Data
INPORT1 HS
INPORT2 HS
Data
Clocks
OUTPORT HS
OUTPORT Data
HANDSHAKE INTERFACE
Control Feedback
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delay
eventpulse
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4x delay 2x delay 1x delay
1x delayin
out
dly[1]dly[2] dly[0]
"0"
"1"
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reset
a
b
outC
a
b
out
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TL
TL out0
out1
in
sel reset
in
out1
out0F
T
SELECT
sel
FORK
sel
ai
ao1
ao0
T
F
ro1
ro0
ri
ri
ro1
ro0F
T
SELECT
sel
aiao1
ao0
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CALL rori1
ri0
ai1
ai0
ao
C
C
ri0
ai0
ri1
ai1
ao
ro
riai
roao
FILL
full
riro
aoai
full
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Criaiti
PIPE ro
aoto
riai
roao
clk
PIPE_
ND
ti to
delay
clk
ri
ai ro
ao
register
ti1
ti2 to2
to1 ti1
ti2 to2
to1
Mode 1 Mode 2
ti1
ti2 to2
to1
Mode 3
constant (from configuration)
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ro2ao2to2
ro1
ao1to1
ro2ao2to2
MODE1
F
T
DCALL
FORKai1
T
F
ri1
ai2ri2
ti2
ti1
pipe_empty || MODE1
PIP
E
ext_strobe const
ti1
ti2
ri1ai1
ri2ai2
ro1ao1to1
configuration external load
SPLITTER
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C
ri1ai1
ai2
ri2generate_outputMERGE
fi1
fi2
ri1ai1
ri2ai2
configuration
fo
roao
PORTS
F
ILL
MODE3
FORKT
F
ro
ao
configurationconsume_input
fi2
fi1
fo
generate_output
controlMERGE
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MERGE
PORTS
ti1
ti2
ri1ai1
ri2ai2
SPLITTERX
Y
f1
f2
generate
output
fo
X
Y
reg
reg
acc
CSA
CPA/shift
CSAarray
dataout
tout
roao
clk1
clk3
clk2
reset
external load
configuration
MAC
handshake
Configregister
handshake interface
reg
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stage 1 delay
delay
clk2
reg
reg
reg
reg
riai
PIPE_
ND
FORKT
F
clk1
PIPE
_ND
stage 2 delay
clk3
generateoutput reset
Stage 1 Stage 2
fi fo
ro
ao
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MERGEPORTS
ti1
ti2
ri1ai1
ri2ai2
SPLITTER A
B
f1
f2
fo
dataout
tout
roao
external load
configuration
ALUhandshake
Configregister
handshake interface
generate
output
A
B
reg ALU
datapath
clk
reg
reg
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reg
reg
riai
PIPE_
ND
FORKT
F
clk
generateoutput
fi
ALU delay
roao
fo
FORK
wb = ta[15]
aa
MERGEPORTS
CALL SRAMhandshake
F
T
ra
fa
rdad
fd
wb = ta[15]
SRAMcore
external
interface
external access / configuration
roao
tout
configuration
fo
address=ta[14:0]
data=td[15:0]
wb = ta[15]clk done
handshake interface
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reg
FORKT
F
roao
toggle
FF
done
Criai
PI
PE_
ND
clk
wb
delay
AGPCore
instr.memory
ia
instroao
done
vadd
clk
tout
ri (="start") ai (="done")
AGPhandshake
external configuration / load
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FORK
done
FORK
vadd
aoT
F
ro
riai
F
T
delay cycle delay
clk
tout
roao
FPGA
core
FPGA handshake interface
ack1
ack2
rqst
ti1
ti2
ri1ai1
ri2ai2 clk
fpgai2
fpgai1
configuration load
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ri1ai1ti1
PIPE
FILL
ri2ai2ti2
PIPE
FILL
FORKF
T
FORKF
T
latch
latchreset
reset
C cycle delay FORK
rqst
aoT
F
ro
ack1
ack2
clk
fpgai1
fpgai2
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+-
+-
MEM
MEM
MEM
MAC
MAC
MUL SUB
MUL
MUL
MUL
MACDIV
MEM
v[0],a[0]
v[1],a[1]
v[2],a[2]
a[0]
v[0]
v[1]
a[1]
y[*]
y[0]/v[0]
v[*],a[*]v[*]
v[1]
v[*],a[*]
y[1,
2]
y[1,2]
y[2]
v[
3]
v[
2]
v[
0]
v[0]
SUB
a[*] |v[*]|^2
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22
2
2
22
1 2
SAT
SW
5x6 2
2
22
2
2
1 2
SAT
SW
7x8 2
2
22
2
2
1 2
SAT
SW
7x8
22
2
2
1 2
SAT
SW
5x6
2 2
22
2
2
1 2
SAT
SW7x8
2 2
2
2
22
2
2
1 2
SAT
SW9x10
2 2
2
22
2
1 2
SAT
SW9x10
2 2
2
2
22
1 2
SAT
SW7x8
2 2
2
2
1 2
SAT
SW5x6
2 2
2
22
2
1 2
SW7x8
2 2
2
22
2
1 2
SAT
SW
2 2
2
2
1 2
SAT
SW5x6
SAT
00 10 20 30
01 11 21 31
02 12 22 32
7x8
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MEM1
MEM2
MEM3
switch 1 switch 3
switch 4
v[*],a[*]
v[0],a[0]
v[1,2],a[1,2]
v[2],a[2]
v[1],a[1]switch 2
SUB
switch 1 switch 3
switch 4
v[*]
y[0]
v[1,2]
v[1]
v[2]switch 2
SUBMAC
switch 5switch 4
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simple switching broadcasting splitting selecting
selecting+broadcastingsplitting+broadcasting
toggle toggle
ri
ai
latchdata in data out
r_inta_int
ao
ro
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toggle toggle
ri
ai
latch data1 out
r_int
data2 out
data in
latch
toggle
a_int
ao1
ro1
ro2
ao2
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6
5
4
3
2
1
0
1 765432
6
5
4
3
2
1
0
triangular array layout square array layout
2 3 4 5 6 710
0-1 0-2 0-3 0-4 0-5 0-6 0-7
1-2 1-3 1-4 1-5 1-6 1-7
2-3 2-4 2-5 2-6 2-7
3-4 3-5 3-6 3-7
4-5 4-6 4-7
5-6 5-7
6-7
7
0-1 0-3 0-5 0-7
1-2 1-4 1-6
2-3 2-5 2-7
3-4 3-6
4-5 4-7
5-6
6-7
0-2
0-4
0-6
1-3
1-5
1-7
2-4
2-6
3-5
3-7
4-6
5-7
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1
0 0-2
1-3
7
6
1-2
0-3
2-4
3-5
2-6
3-7
0-4
1-5
0-6
1-7
1-6
0-7 0-5
1-4
2-7
3-6
2-5
3-4
4-6
5-6
5-7
4-7
2 3
4 5
join 2
join 0
join 1
join 3
join 5
join 4
join 6
join 7
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aiA_inaiA_out
bitb
aoB aiB_inaiB_out
bitb
aoA
clrbA
setA
setB
clrbB
riAriB
robA robB
clrAclrB
clrbA clrbB
bit
bitb
clr
set
clrb
ai_vert_in
ai_horiz_inai_out
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toggle
ri
ai
latch data1 out
latch
toggle
ao1
ro1
ro2
ao2
data in
toggle
rob2
ao2
ai ri
ao1
rob1
delay
delay
data2 outrouting
table
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.
.
.
.
.
.
Output 1
Output 2
Output M
Latch 1
Latch 2
Latch M
Data 1
Data 2
Data N
Arbiter 1
Arbiter 2
Arbiter N
Client 1
Client 2
Client N
Token Ring Controller
Routing table
TDM bus
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id
id
einb
ein
eoutb
eout
portdata[i] busdata[i]
aobb
0.5
0.5
1.0
1.0
1.2
0.8
0.5
0.5
0.4
0.4/0.5
0.4
0.4
0.4
0.4
0.8
1.8
0.8
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reset
hold_initial
rqst grantai
ro
hold
ri
ao
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arb-
ri+ full-
arb+
agb-
ri- agb+full+
clkb-
clkb+
rob- eout+ clkb- full+
ao-
rob+eout-clkb+full-
ao+
ai-ai+
ainrin
routaout
routing table interface
input port handshake
output port handshake
data receive
data send
shared bus
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arbiter_rqst
hsin
hsout
idid
adjustible delay
arbiter_grant
eout
eoutb
rob
ai
ri
clk
arbiter_ao
reset
ein
einb
ao
aobb
full
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clrb[7:0]
clkb[7:0]
dract
drclk
drclr clr[7:0]
set[7:0]
configuration/instruction
drport[7:0]
dynamic router
mux
mux
decoder
busdata[17:16]
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reset
clk
3 instructionmemory
2
routinglogic
busdata[17:16]
drclk
drclr
clr
dract
delay
set[7:0]
addrreg
dract
8
cycle delay
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port 3
port 2
port 5
port 4
port1
port0
port7
port6
/ arbiterport controller /
port buffer
routing table
90u
200u
dynamicrouter
?
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ao
aobb
rob
eout
eoutb
550 555 560 565
0 200 400 600 800 1
0V
0.5V
1V
0V
0.5V
1V
0V
0.5V
1V
0V
0.5V
1V
0V
0.5V
1V
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from 6 to 4
full6
ein6
einb6
ri6
rob4
eout4
eoutb4
full4
from 0 to 3
full0
ein0
einb0
ri0
rob3
eout3
eoutb3
full3
530 535 540
0 200 400 600 800 1
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
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from 6 to 4
rin6
full6
ain6
ri6
rob4
eout4
eoutb4
full4
rout4
520 530 540 550 560
0 200 400 600 800 1
0V
1V
0V
1V
0V
1V
0V
1V
0V
1V
0V
1V
0V
1V
0V
1V
0V
1V
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MUL
MEM
MAC
MAC SUB MUL SUB
MEM
SUB
MEM
ADDe
ys
Zx
dx
x[n+1]
y[n]
Zs
yx
x[n]
+-
+-
Z
c
+
-
s
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MUL
MEM
SUBMAC
MAC SUB MUL SUB
MEM
MEM
ADDe
Z
ys
Zx
dx
x[n]
y[n]
Zs
yx
x[n+1]
x[0]c
s
+-
+- +
-
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MUL SUBMAC
MAC MUL SUB
MEM
MEM
MEM
MEM
SUB +-+
-
MEM
MEM
ADDe
Z
ys
Zx
dx
Zs
yx
x[n+1]
s1
s2
port1:y[n]
x[n]
+-
x[0]
port2:x[0],c
c
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x1,y1 x2,y2 x3.y3 x4,y4 x5,y5
y1 y2 y3 y4
x1 x2 x3 x4
MACXY
SUBX
SUBY
MX1
MX2
MY1
MY2
write y1 read y1 write y3 read y3
write y2 read y2 write y4 read y4
write y5
write x3 read x3read x1write x1 write x5
write x2 read x2 write x4 read x4
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CB
CB
CB
CB
SATO O
I2
I1
SW
SW SW
SW
broadcasting 3-way broadcasting 3 connections
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port 0
port 1
port 2
port 3
input port
output port
c[0] c[1]
c[2] c[3]
c[4]c[5]
c[6]
clkinput latch
output buffer
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C
C
ack1
c1
ack2
c2
ack
c
hsin1
c[0]
hsin3
c[1]
c[4]
c[3]
c[2]
c[5]
c[6]
hsout2
hsout0
delay
ai
ri
clk
hsin0
hsout1
hsin2
hsout3
ro
c[0] c[1]
c[2] c[3]
c[4]c[5]
c[6]
ao
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0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
6
7
2 3
4 5
0
1
2
4
0
1
2
4
0
1
2
4
0
1
6
7
2 3
4 5
01
67
2 3
4 5
0
1
6
7
2 3
4 5
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1 3
0 2
1 3
0 2
1 3
0 2
1 3
0 2
1 3
0 2
1 3
0 2
1 3
0 2
3 2
01
3 2
01
3 2
01
3 2
01
3 2
01
3
1
2 3
10
2 3
10
2 3
10
2 3
10
2 3
10
2
0
2
0
3 2
01
L
H
L
H
L
H
L
AGP0
AGP5 AGP4
AGP1
SRAM0
SRAM1 SRAM2
SRAM4SRAM5
AI
AI
AIAI
AI
DI
DI DO DIDO
DI DO DO
MAC0
ALU0 MAC1 MAC2
MAC3ALU1 ALU2
ALU3
O OI1
O
I2
O
O O I1
O
I2
O
O O I1
O
I2
O
O OI1
O
I2
O
DO
OUT2
IN1 IN2
0 1 2 3
5 6 7 8
10 11 12 13
15
15
15
I2
I1
I2
I1
I2
I1
I2
I1
Zx
Zx
Zs
Zs
Zs Z Z
e
e
dx dx
ys
ys
yx
yx
y
y
y
y
y
y
s2
s2
s1
s1
c
x[0],c
x[0]
x[n+1]
x
x
yx
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AGPSAT specification
AGP instructions (microprogram):
field PORT I0 I1 S1 S3 COND NIT NIF DEST NOP KOP K0OP
INST bits [0:2] [3:4] [5:6] [7:8] [9:10] [16:17] [18:19] [20]
[21:28] [11] [13] [14:15]
AGP configurations:
current AGP has three 32-bit configuration registers addressed
at 0x0, 0x1, 0x2 of thesatellite address space
I0 S0 S1 I1 S2 S3 N K0 IPC cycle delay
0x1:[8:19]
0x0:[0:7]
0x2:[8:15]
0x1:[20:31]
0x0:[8:15]
0x2:[16:23]
0x1:[0:7]
0x2:[0:7]
0x0:[16:23]
0x0:[22:20]
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MACSAT specification
operation modes:
performed on two internal streams X,Y;
OP1 MPY OUT = X * Y for each element of X,Y
OP2 MAC OUT = sum (X*Y) at the end of X,Y
OP3 MPY with accumulationOUT = sum (X*Y) for each element
ofX,Y
input modes:
MACSAT has two ports: I1,I2; size(I1)
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ALUSAT specification
operation modes:
performed on two internal streams A, B;
OPCODE operation allowed input mode
00000 A INMODE3, const ignored
00001 A+B any
00010 A-B any
00011 abs(A) INMODE3, const ignored
00100 A>B any
00101 A>=B any
00110 A
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SRAMSAT specification
operation modes:
2 ports: ADDR, DATA
OP1 - write ADDR = 0write DATA into ADDR (512)
or ADDR (1024)
OP2 - read ADDR = 1 OUT = mem(ADDR)
input modes for write:
INMODE1DATA port active
size(DATA)
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