10/7/05 IOSCA 2005 Tutorial 1 Using the M5 Simulator Nathan Binkert and Ali Saidi Ron Dreslinski, Lisa Hsu, Thanks also to Ron Dreslinski, Lisa Hsu, Kevin

10/7/0510/7/05 IOSCA 2005 TutorialIOSCA 2005 Tutorial 11

Using the M5 SimulatorUsing the M5 Simulator

Nathan Binkert and Ali SaidiNathan Binkert and Ali Saidi

Thanks also to Ron Dreslinski, Lisa Hsu, Ron Dreslinski, Lisa Hsu, Kevin Lim, Kevin Lim, Steve Raasch, Erik Hallnor,and Prof. Steve Reinhardtand Prof. Steve Reinhardt


Welcome!Welcome!

This tutorial is for This tutorial is for youyou Feel free to ask questionsFeel free to ask questions

We’ve got a lot to coverWe’ve got a lot to cover Lots of cool stuff didn’t even make the slidesLots of cool stuff didn’t even make the slides Don’t be offended if we have to move onDon’t be offended if we have to move on Come talk to us laterCome talk to us later


OutlineOutlineIntroduction & OverviewIntroduction & OverviewRunning M5Running M5Full-System WorkloadsFull-System Workloads


Introduction & OverviewIntroduction & Overview

Nathan BinkertNathan Binkert


Introduction & OverviewIntroduction & Overview

What M5 is and is notWhat M5 is and is notA brief peek insideA brief peek insideCurrent status & future developmentsCurrent status & future developments


What is M5?What is M5?

A tool for simulating A tool for simulating systemssystems Not just CPU cores: memory, I/ONot just CPU cores: memory, I/O Not just SPEC apps: full OS codeNot just SPEC apps: full OS code Not just single machines: client/server, etc.Not just single machines: client/server, etc.


Two Views of M5Two Views of M5

A framework for event-driven simulationA framework for event-driven simulation Events, objects, statistics, configurationEvents, objects, statistics, configuration

A collection of predefined object modelsA collection of predefined object models CPUs, caches, busses, devices, etc.CPUs, caches, busses, devices, etc.


Where Did M5 Come From?Where Did M5 Come From?

Born of frustration with existing toolsBorn of frustration with existing tools Did not do what we wantedDid not do what we wanted Did not scale with added complexityDid not scale with added complexity

Desire to simulate TCP/IP performanceDesire to simulate TCP/IP performance Full-system supportFull-system support Multiple system simulationMultiple system simulation

Almost entirely original codeAlmost entirely original code Old CPU model based on SimpleScalar sim-outorderOld CPU model based on SimpleScalar sim-outorder Full-system support used SimOS as referenceFull-system support used SimOS as reference

No premeditated distribution plansNo premeditated distribution plans Just hacking together the system Just hacking together the system wewe wanted wanted


Key M5 AttributesKey M5 Attributes

Heavily object-orientedHeavily object-oriented Key to modularity, flexibilityKey to modularity, flexibility

Necessarily complexNecessarily complex ~90K lines of C++, ~10K lines of Python~90K lines of C++, ~10K lines of Python

Modular enough to hide the complexityModular enough to hide the complexity We hope!We hope!

Free! All the code we wrote is open sourceFree! All the code we wrote is open source BSD-style licenseBSD-style license


What M5 is What M5 is NotNot

A hardware design languageA hardware design language Higher level for design space exploration, Higher level for design space exploration,

simulation speedsimulation speed

A restrictive environmentA restrictive environment Just C++/Python with an event queue and a Just C++/Python with an event queue and a

bunch of APIs you can choose to ignorebunch of APIs you can choose to ignore

Finished!Finished! Always room for improvement…Always room for improvement…


What We Would Like M5 to BeWhat We Would Like M5 to Be

Something that spares you the pain we’ve Something that spares you the pain we’ve been throughbeen through

A community resourceA community resource Modular enough to localize changesModular enough to localize changes Contribute back, and spare others some painContribute back, and spare others some pain

A path to reproducible/comparable resultsA path to reproducible/comparable results A common platform for evaluating ideasA common platform for evaluating ideas


A Peek Inside: ObjectsA Peek Inside: Objects

Everything you care about is an object Everything you care about is an object (C++/Python)(C++/Python)

Derived from SimObject base classDerived from SimObject base class Common code for creation, configuration parameters, Common code for creation, configuration parameters,

naming, checkpointing, etc.naming, checkpointing, etc.

Uniform method-based APIs for object typesUniform method-based APIs for object types CPUs, caches, memory, etc.CPUs, caches, memory, etc. Plug-compatibility across implementationsPlug-compatibility across implementations

Functional vs. detailed CPUFunctional vs. detailed CPU Conventional vs. indirect-index cacheConventional vs. indirect-index cache

Easy replication: MPs, multiple systems, …Easy replication: MPs, multiple systems, …


A Peek Inside 2: EventsA Peek Inside 2: Events

Standard event queue timing modelStandard event queue timing model Global logical time (in “ticks”)Global logical time (in “ticks”) No fixed relation to real timeNo fixed relation to real time

Objects schedule their own eventsObjects schedule their own events Flexibility for detail vs. performance tradeoffsFlexibility for detail vs. performance tradeoffs

E.g., a CPU typ. schedules an event every cycleE.g., a CPU typ. schedules an event every cycle Simple CPU won’t schedule self if stalled/idle Simple CPU won’t schedule self if stalled/idle Can also schedule every nCan also schedule every nthth cycle to model other cycle to model other

clock ratesclock rates e.g., non-integer CPU/bus clock ratiose.g., non-integer CPU/bus clock ratios


Current Model StatusCurrent Model Status

Three CPU modelsThree CPU models One functional & two detailed OOOOne functional & two detailed OOO

old SimpleScalar-based & new in developmentold SimpleScalar-based & new in development CPUs support Alpha ISACPUs support Alpha ISA

Others “easily” addedOthers “easily” added

Two major cache modelsTwo major cache models Conventional & indirect-indexConventional & indirect-index

Bus-based interconnectBus-based interconnect Split transactions, snooping coherenceSplit transactions, snooping coherence


Current Status (cont’d)Current Status (cont’d)

Syscall emulation modeSyscall emulation mode Alpha Tru64 or Linux application binariesAlpha Tru64 or Linux application binaries Host-based or SimpleScalar EIO tracesHost-based or SimpleScalar EIO traces

Full-system modeFull-system mode Models Compaq “Tsunami”-based systemModels Compaq “Tsunami”-based system

Boots Linux 2.4 & 2.6, FreeBSD and L4Boots Linux 2.4 & 2.6, FreeBSD and L4 Ask us if you want Tru64Ask us if you want Tru64

Extensions for >4 CPUsExtensions for >4 CPUs Ethernet, IDE disk adaptersEthernet, IDE disk adapters Handful of pre-built benchmarks availableHandful of pre-built benchmarks available


Short-term Wish ListShort-term Wish List

Finish new detailed OOO CPU modelFinish new detailed OOO CPU model Add full system, SMT supportAdd full system, SMT support Obsolete SimpleScalar-based modelObsolete SimpleScalar-based model

Minor re-architecting of memory systemMinor re-architecting of memory system Support non-bus interconnects, directory coherenceSupport non-bus interconnects, directory coherence

More ISAsMore ISAs PowerPC, ARM likely candidatesPowerPC, ARM likely candidates Heterogeneous system support (?)Heterogeneous system support (?)

More full-system benchmarksMore full-system benchmarksBetter C++/Python integrationBetter C++/Python integration


OutlineOutlineIntroduction & overviewIntroduction & overviewRunning M5Running M5Full-System WorkloadsFull-System Workloads


Running M5Running M5

Ali SaidiAli Saidi


Running M5Running M5

Source treeSource treeBuilding executablesBuilding executablesRunning simulationsRunning simulationsSpecifying configurationsSpecifying configurationsOutput filesOutput filesCheckpointingCheckpointingSampling & warm-upSampling & warm-up


Source Tree OrganizationSource Tree Organization

m5: actual simulator sourcem5: actual simulator sourcem5-test: regression testsm5-test: regression testsext: 3ext: 3rdrd-party packages-party packages

dnet, libelf, plydnet, libelf, ply

linux-dist: source for disk imageslinux-dist: source for disk images


Building ExecutablesBuilding Executables

PlatformsPlatforms Linux, BSD, CYGWIN (most UNIX like systems?)Linux, BSD, CYGWIN (most UNIX like systems?)

Linux is primary, others may take a tiny bit of workLinux is primary, others may take a tiny bit of work Little endian machines!Little endian machines! 64-bit machines help a lot64-bit machines help a lot

ToolsTools GCC/G++ 3.0+GCC/G++ 3.0+

Recently tested with 3.3,3.4,4.0Recently tested with 3.3,3.4,4.0 Python 2.3+Python 2.3+ SCons (we use 0.96+)SCons (we use 0.96+)

http://www.scons.orghttp://www.scons.org


% cd m5% cd m5% cd build% cd build% scons % scons ALPHA_FS/m5.optALPHA_FS/m5.optscons: Reading SConscript files ...scons: Reading SConscript files ...Checking for C header file fenv.h... yesChecking for C header file fenv.h... yesCompiling in ALPHA_FS with MySQL support.Compiling in ALPHA_FS with MySQL support.scons: done reading SConscript files.scons: done reading SConscript files.scons: Building targets ...scons: Building targets .../z/saidi/work/m5/build/m5/arch/isa_parser.py m5/arch/alpha/isa_desc /z/saidi/work/m5/build/m5/arch/isa_parser.py m5/arch/alpha/isa_desc

ALPHA_FS/arch/alpha arch/alphaALPHA_FS/arch/alpha arch/alphaGenerating ALPHA_FS/arch/alpha/decoder.hhGenerating ALPHA_FS/arch/alpha/decoder.hhGenerating ALPHA_FS/arch/alpha/decoder.ccGenerating ALPHA_FS/arch/alpha/decoder.ccGenerating ALPHA_FS/arch/alpha/simple_cpu_exec.ccGenerating ALPHA_FS/arch/alpha/simple_cpu_exec.ccGenerating ALPHA_FS/arch/alpha/fast_cpu_exec.ccGenerating ALPHA_FS/arch/alpha/fast_cpu_exec.ccGenerating ALPHA_FS/arch/alpha/full_cpu_exec.ccGenerating ALPHA_FS/arch/alpha/full_cpu_exec.ccGenerating ALPHA_FS/arch/alpha/alpha_o3_exec.ccGenerating ALPHA_FS/arch/alpha/alpha_o3_exec.ccDefining SS_COMPATIBLE_FP as 0 in ALPHA_FS/config/ss_compatible_fp.hh.Defining SS_COMPATIBLE_FP as 0 in ALPHA_FS/config/ss_compatible_fp.hh.Defining USE_FENV as 1 in ALPHA_FS/config/use_fenv.hh.Defining USE_FENV as 1 in ALPHA_FS/config/use_fenv.hh.echo '#include "arch/alpha/isa_traits.hh"' > ALPHA_FS/targetarch/isa_traits.hhecho '#include "arch/alpha/isa_traits.hh"' > ALPHA_FS/targetarch/isa_traits.hhDefining FULL_SYSTEM as 1 in ALPHA_FS/config/full_system.hh.Defining FULL_SYSTEM as 1 in ALPHA_FS/config/full_system.hh.echo '#include "arch/alpha/alpha_memory.hh"' > echo '#include "arch/alpha/alpha_memory.hh"' >

ALPHA_FS/targetarch/alpha_memory.hhALPHA_FS/targetarch/alpha_memory.hhecho '#include "arch/alpha/byte_swap.hh"' > ALPHA_FS/targetarch/byte_swap.hhecho '#include "arch/alpha/byte_swap.hh"' > ALPHA_FS/targetarch/byte_swap.hhDefining NO_FAST_ALLOC as 0 in ALPHA_FS/config/no_fast_alloc.hh.Defining NO_FAST_ALLOC as 0 in ALPHA_FS/config/no_fast_alloc.hh.Defining STATS_BINNING as 1 in ALPHA_FS/config/stats_binning.hh.Defining STATS_BINNING as 1 in ALPHA_FS/config/stats_binning.hh.python m5/base/traceflags.py ALPHA_FS/base/traceflagspython m5/base/traceflags.py ALPHA_FS/base/traceflags......


Running SimulationsRunning SimulationsUsage:Usage:m5.debug [-d <dir>] [-E <var>[=<val>]] [-I <dir>] [-P <python>]m5.debug [-d <dir>] [-E <var>[=<val>]] [-I <dir>] [-P <python>] [--<var>=<val>] <config file>[--<var>=<val>] <config file>

-d set the output directory to <dir>-d set the output directory to <dir> -E set the environment variable <var> to <val> (or -E set the environment variable <var> to <val> (or

'True')'True') -I add the directory <dir> to python's path-I add the directory <dir> to python's path -P execute <python> directly in the configuration-P execute <python> directly in the configuration --var=val set the python variable <var> to '<val>'--var=val set the python variable <var> to '<val>' <configfile> config file name (ends in .py)<configfile> config file name (ends in .py)

% % ALPHA_FS/m5.debug –d output –ETEST=SPECWEB ALPHA_FS/m5.debug –d output –ETEST=SPECWEB configs/fullsys/run.pyconfigs/fullsys/run.py

% % ALPHA_FS/m5.debug –d output –EDUMPFILE=ethertraceALPHA_FS/m5.debug –d output –EDUMPFILE=ethertrace-ETEST=NETPERF_STREAM configs/fullsys/run.py-ETEST=NETPERF_STREAM configs/fullsys/run.py--Trace.flags=“EthernetAll”--Trace.flags=“EthernetAll”

% % ALPHA_SE/m5.opt –d output m5-test/test1/run.pyALPHA_SE/m5.opt –d output m5-test/test1/run.py


% ~/m5/build/ALPHA_FS/m5.debug –d output ~/m5/configs/fullsys/run.py% ~/m5/build/ALPHA_FS/m5.debug –d output ~/m5/configs/fullsys/run.pyM5 Simulator SystemM5 Simulator SystemCopyright (c) 2001-2005Copyright (c) 2001-2005The Regents of The University of MichiganThe Regents of The University of MichiganAll Rights ReservedAll Rights Reserved

This code is part of the M5 simulator, developed by Nathan Binkert,This code is part of the M5 simulator, developed by Nathan Binkert,Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributionsErik Hallnor, Steve Raasch, and Steve Reinhardt, with contributionsfrom Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,and Andrew Schultz.and Andrew Schultz.

M5 compiled on Oct 2 2005 22:16:33M5 compiled on Oct 2 2005 22:16:33M5 simulation started Sun Oct 2 22:17:40 2005M5 simulation started Sun Oct 2 22:17:40 2005Listening for console connection on port 3456Listening for console connection on port 3456 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1

00:00:00 200600:00:00 2006command line: ./m5.opt -d output ../../configs/fullsys/run.pycommand line: ./m5.opt -d output ../../configs/fullsys/run.py

Listening for remote gdb connection on port 7000Listening for remote gdb connection on port 7000warn: Entering event queue. Starting simulation...warn: Entering event queue. Starting simulation...


m5termm5term

allows user to connect to the simulated allows user to connect to the simulated console interfaceconsole interface

% % cd m5cd m5

% % cd util/termcd util/term

% % makemake

gcc -o m5term term.cgcc -o m5term term.c

% % make installmake install

sudo install -o root -m 555 m5term /usr/local/binsudo install -o root -m 555 m5term /usr/local/bin


% % m5term localhost 3456m5term localhost 3456==== m5 slave console: Console 0 ======== m5 slave console: Console 0 ====M5 consoleM5 consoleGot Configuration 127 Got Configuration 127 memsize 8000000 pages 4000 memsize 8000000 pages 4000 First free page after ROM 0xFFFFFC0000018000First free page after ROM 0xFFFFFC0000018000HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000

l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC00000460000xFFFFFC0000046000

CPU Clock at 2000 MHz IntrClockFrequency=1024 CPU Clock at 2000 MHz IntrClockFrequency=1024 Booting with 1 processor(s) Booting with 1 processor(s) ............VFS: Mounted root (ext2 filesystem) readonly.VFS: Mounted root (ext2 filesystem) readonly.Freeing unused kernel memory: 480k freedFreeing unused kernel memory: 480k freedinit started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binaryinit started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary

PTXdist-0.7.0 (2004-11-18T11:23:40-0500)PTXdist-0.7.0 (2004-11-18T11:23:40-0500)

mounting filesystems...mounting filesystems...EXT2-fs warning: checktime reached, running e2fsck is recommendedEXT2-fs warning: checktime reached, running e2fsck is recommendedloading script...loading script...Script from M5 readfile is empty, starting bash shell...Script from M5 readfile is empty, starting bash shell...# # lslsbenchmarks etc lib mnt sbin usrbenchmarks etc lib mnt sbin usrbin floppy lost+found modules sys varbin floppy lost+found modules sys vardev home man proc tmp zdev home man proc tmp z# #


Configuration FilesConfiguration Files

PythonPythonConfig objs mapped to simulator objsConfig objs mapped to simulator objsNo need for scripts to generate configsNo need for scripts to generate configs

All logic for running many simulations contained in a All logic for running many simulations contained in a single set of configurable config files!single set of configurable config files!

Pass parameters via environment varsPass parameters via environment vars -E<var>[=<val>]-E<var>[=<val>]

Variables with units are enforcedVariables with units are enforced Latency must be ‘2ns’, not simply 2Latency must be ‘2ns’, not simply 2


class DCache(BaseCache):class DCache(BaseCache):latency = 3 * Parent.clock.periodlatency = 3 * Parent.clock.periodsize = '32kB'size = '32kB'mshrs = 32mshrs = 32

class CPU(SimpleCPU):class CPU(SimpleCPU):dcache = DCache(in_bus=NULL, out_bus=Parent.membus)dcache = DCache(in_bus=NULL, out_bus=Parent.membus)icache = ICache(in_bus=NULL, out_bus=Parent.membus)icache = ICache(in_bus=NULL, out_bus=Parent.membus)

class System(LinuxSystem):class System(LinuxSystem):cpu = CPU()cpu = CPU()membus = Bus(width=16, clock='400MHz')membus = Bus(width=16, clock='400MHz')ram = BaseMemory(in_bus=Parent.membus, latency='40ns',ram = BaseMemory(in_bus=Parent.membus, latency='40ns',

addr_range=[ Parent.physmem.range ])addr_range=[ Parent.physmem.range ])physmem = PhysicalMemory(range=AddrRange('128MB'))physmem = PhysicalMemory(range=AddrRange('128MB'))tsunami = Tsunami()tsunami = Tsunami()simple_disk = SimpleDisk(disk=Parent.tsunami.disk0.image)simple_disk = SimpleDisk(disk=Parent.tsunami.disk0.image)sim_console = SimConsole(listener=ConsoleListener(port=3456))sim_console = SimConsole(listener=ConsoleListener(port=3456))kernel = '/dist/m5/system/binaries/vmlinux-latest'kernel = '/dist/m5/system/binaries/vmlinux-latest'pal = '/dist/m5/system/binaries/ts_osfpal'pal = '/dist/m5/system/binaries/ts_osfpal'console = '/dist/m5/system/binaries/console_ts'console = '/dist/m5/system/binaries/console_ts'boot_osflags = 'root=/dev/hda1 console=ttyS0'boot_osflags = 'root=/dev/hda1 console=ttyS0'

root = Root(clock='2GHz')root = Root(clock='2GHz')root.client = System(readfile='/dist/m5/system/boot/netperf-stream-client.rcS')root.client = System(readfile='/dist/m5/system/boot/netperf-stream-client.rcS')root.server = System(readfile='/dist/m5/system/boot/netperf-server.rcS')root.server = System(readfile='/dist/m5/system/boot/netperf-server.rcS')root.etherlink = EtherLink(int1 = Parent.server.tsunami.etherint[0],root.etherlink = EtherLink(int1 = Parent.server.tsunami.etherint[0],

int2 = Parent.client.tsunami.etherint[0])int2 = Parent.client.tsunami.etherint[0])


Output FilesOutput Files

Current Directory or -d <dir>Current Directory or -d <dir> config.py, config.ini, config.outconfig.py, config.ini, config.out console.<system>.sim_consoleconsole.<system>.sim_console outputoutput stats.txtstats.txt cpt.<number>/cpt.<number>/

Database OutputDatabase Output M5 can output to a MYSQL databaseM5 can output to a MYSQL database


Statistics (Statistics (stats.txtstats.txt))

client.cpu.not_idle_fraction 0.011831client.cpu.not_idle_fraction 0.011831

client.cpu.numCycles 1002224512client.cpu.numCycles 1002224512

client.cpu.num_insts 1002224512client.cpu.num_insts 1002224512

client.cpu.num_refs 183157920client.cpu.num_refs 183157920

. . .. . .

client.tsunami.etherdev0.rxBandwidth 775424160client.tsunami.etherdev0.rxBandwidth 775424160

client.tsunami.etherdev0.rxBytes 4846401client.tsunami.etherdev0.rxBytes 4846401

client.tsunami.etherdev0.rxIpChecksums 3520client.tsunami.etherdev0.rxIpChecksums 3520

client.tsunami.etherdev0.rxPPS 70400client.tsunami.etherdev0.rxPPS 70400

client.tsunami.etherdev0.rxPackets 3520client.tsunami.etherdev0.rxPackets 3520

client.tsunami.etherdev0.rxTcpChecksums 3520client.tsunami.etherdev0.rxTcpChecksums 3520

client.tsunami.etherdev0.rxUdpChecksums 0client.tsunami.etherdev0.rxUdpChecksums 0

client.tsunami.etherdev0.totBandwidth 800440160client.tsunami.etherdev0.totBandwidth 800440160

client.tsunami.etherdev0.totBytes 5002751client.tsunami.etherdev0.totBytes 5002751


CheckpointingCheckpointing

--Serialize.cycle=<start cycle>--Serialize.cycle=<start cycle>--Serialize.period=<repeat interval>--Serialize.period=<repeat interval>--Serialize.count=<# of checkpoints>--Serialize.count=<# of checkpoints>

M5 instructionM5 instruction Insert special instruction into code to trigger a Insert special instruction into code to trigger a

checkpoint to be droppedcheckpoint to be dropped Our benchmarks do thisOur benchmarks do this


Starting From a CheckpointStarting From a Checkpoint

Same configuration as normal except you add:Same configuration as normal except you add:

--Root.checkpoint=<path>/cpt.<number>--Root.checkpoint=<path>/cpt.<number>

Checkpoints must be regenerated with some Checkpoints must be regenerated with some config changesconfig changes Most config changes that are architecturally visible Most config changes that are architecturally visible

(because the kernel may have behaved differently)(because the kernel may have behaved differently) Physical memory size, new kernelsPhysical memory size, new kernels


Sampling & Warm-upSampling & Warm-up

M5 canM5 can dump statistics many timesdump statistics many times aggregate statistics based on some eventaggregate statistics based on some event

(keep stats according to kernel mode or user mode)(keep stats according to kernel mode or user mode)

Switch between CPU configurationsSwitch between CPU configurationsFunctional CPU Functional CPU Detailed CPU Detailed CPU Warm-up caches in a functional CPU, do Warm-up caches in a functional CPU, do

measurements in a detailed CPUmeasurements in a detailed CPU




Full System WorkloadsFull System Workloads



Basic OperationBasic OperationDisk imagesDisk images

Raw copies of Linux disk imageRaw copies of Linux disk image Binaries to be run must be present on imageBinaries to be run must be present on image

rcS files (rcS files (m5/configs/boot/*.rcSm5/configs/boot/*.rcS)) Exactly like normal boot scriptsExactly like normal boot scripts Use them to start running a binary on the disk Use them to start running a binary on the disk

image, configure ethernet interfaces, etc.image, configure ethernet interfaces, etc. Can also execute m5 instructionsCan also execute m5 instructions Nice and flexible, since not compiled inNice and flexible, since not compiled in

Specified in configuration by Specified in configuration by readfile=‘path/to/script.rcS’readfile=‘path/to/script.rcS’


See for yourself!See for yourself!Going into / of disk image and typing ls will show:Going into / of disk image and typing ls will show:

benchmarks etc lib mnt sbin usrbenchmarks etc lib mnt sbin usr bin floppy lost+found modules sys varbin floppy lost+found modules sys var dev home man proc tmp zdev home man proc tmp z

Snippet of .rcS file:Snippet of .rcS file:

echo -n "setting up network..."echo -n "setting up network..."/sbin/ifconfig eth0 192.168.0.10 txqueuelen 1000/sbin/ifconfig eth0 192.168.0.10 txqueuelen 1000/sbin/ifconfig lo 127.0.0.1/sbin/ifconfig lo 127.0.0.1echo -n "running surge client..."echo -n "running surge client..."/bin/bash -c "cd /benchmarks/surge && ./Surge 2 100 1 192.168.0.1 5“/bin/bash -c "cd /benchmarks/surge && ./Surge 2 100 1 192.168.0.1 5“echo -n "halting machine"echo -n "halting machine"m5 exitm5 exit


Up and Running BenchmarksUp and Running Benchmarks

All networking focusedAll networking focusedSpecWEB99SpecWEB99NetperfNetperf

stream – a transmit benchmarkstream – a transmit benchmark maerts – a receive benchmarkmaerts – a receive benchmark

In progress:In progress: NFS NFS (server works; client tuning needed)(server works; client tuning needed)

iSCSIiSCSI video streamingvideo streaming


Adding Your Own BenchmarksAdding Your Own BenchmarksHighly encouraged! Highly encouraged!

Please share them with others!Please share them with others!

Since M5 is Alpha targeted, need to Since M5 is Alpha targeted, need to compile Alpha binariescompile Alpha binaries Cross-compiler can be downloaded from Cross-compiler can be downloaded from

www.kegel.com/crosstoolwww.kegel.com/crosstool Or, if you have an Alpha, use thatOr, if you have an Alpha, use that Add the benchmark binaries to disk image Add the benchmark binaries to disk image Create .rcS file that executes the binaryCreate .rcS file that executes the binary

http://www.kegel.com/crosstool


Mounting Disk ImagesMounting Disk Images

If you need to mount a disk image to If you need to mount a disk image to change something (like add a benchmark change something (like add a benchmark binary)binary)

As root:As root:mount –o loop,offset=32256 myimage.img /mnt/pointmount –o loop,offset=32256 myimage.img /mnt/point

You can then manipulate the file system You can then manipulate the file system directly and copy in binariesdirectly and copy in binaries

Don’t forget to unmount!Don’t forget to unmount!




Wrap-UpWrap-Up



Thank You!Thank You!

We hope you found this tutorial usefulWe hope you found this tutorial usefulWe hope you find M5 useful tooWe hope you find M5 useful tooWe’d love to work with you to make M5 We’d love to work with you to make M5

even more useful to the communityeven more useful to the community


Keep In TouchKeep In Touch

Come talk to usCome talk to usLonger tutorial and updates available at Longer tutorial and updates available at

http://m5.eecs.umich.eduhttp://m5.eecs.umich.eduUse, subscribe to our mailing lists:Use, subscribe to our mailing lists:

[email protected]@lists.sourceforge.net [email protected]@lists.sourceforge.net

Documents

10/7/05 IOSCA 2005 Tutorial 1 Using the M5 Simulator Nathan Binkert and Ali Saidi Ron Dreslinski, Lisa Hsu, Thanks also to Ron Dreslinski, Lisa Hsu, Kevin