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IIT-Bombay Lecture 11 M. Shojaei Baghini

Module 12Latch as a Comparator

References- Prof. Boris Murmann’s slides from “VLSI Data Conversion Circuits”, Stanford University, 2013.- Section “Latched Comparators” onwards from chapter “Comparators”, Analog Integrated Circuit Design by T. C. Carusone, D. A. Johns and K. Martin, J. Wiley & Sons, 2012.- “Clocked Comparator” from chapter “Submicron CMOS Circuit Design”, CMOS Mixed-signal Circuit Design by R. Jacob Baker, Wiley India, IEEE press, reprint 2009.- “Comparator” from chapter “Nonlinear Analog Circuits”, CMOS Circuit Design, Layout and Simulation by R. Jacob Baker, Wiley India, IEEE press, 2008.- “The StrongArm Latch”, B. Razavi, IEEE Solid-State Circuits Magazine, Spring 2015.

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Replacing Cascade of N Integrators with a Closed Loop of Integrators

• Each inverter is a Gm module driving a capacitive load and hence behaves as an integrator.

• A closed loop of two inverters is mimicking cascade of infinite number of integrators.

VDD

VSS

VIP VIN

!1 !1

!2

!2CL CL

Latch (regenerative sense amplifier)

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Latch as a Comparator

B. Murmann’s course, Stanford Univ., 2013Latch gain

!!

!="#$%

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Latch as a Comparator - Example

B. Murmann’s course, Stanford Univ., 2013

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Linear Behavior of log(Vdiff(t)) versus t and Initial Condition

B. Murmann’s course, Stanford Univ., 2013

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Analysis of Latch Delay

• K. Martin’s book, 2012 • B. Murmann’s course, Stanford

Univ., 2013

Td,latch = !latchln "#$,&#'()"#$,*C ≈ a × WLCox , 1<a<2

gm ≈ b × +Cox W/L × VGST, 0.5<b<1(either NMOS or PMOS transistor) ⇒ !latch ≈ d × L2/(+n × VGST) where 1<d<4

Velocity saturation:!latch ≈ a × L/vsat

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IIT-Bombay Lecture 11 M. Shojaei Baghini

End of Lecture 11

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Mixed-Signal VLSI DesignCourse Code: EE719

Department: Electrical EngineeringLecture 13: February 10, 2020

Instructor Name: M. Shojaei BaghiniE-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Module 13Effect of Offset in Latched Comparator

Reference• An Analysis of Latch Comparator Offset Due to Load

Capacitor Mismatch, A. Nikoozadeh and B. Murmann, IEEE TCAS-II, Dec. 2006

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Shortcomings Associated with the Stand-alone Latch as a Comparator

• Static and dynamic offset of latch• Charge injection from switches• Kickback noise• Low CMRR

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Latch Offset

!"#0 = 1 + ∆)) − 1 !"+0 − !#,+ + ΔVsw

VON0: Initial voltage , CLP=C , CLN=C+ΔCExample: 5% mismatch, VON0 = 300mV, VSWN = 0.9V , ΔVsw = 20mV ⇒ Initial offset voltage VOS0 = 35mV!

Inspired from: An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch, A. Nikoozadeh and B. Murmann, IEEE TCAS-II, Dec. 2006

!"#0 = 1 + ∆)) 1 + ∆./

./− 1 !"+0 − !#,+ + ΔVsw

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Pre-amplifier Followed by Latch

!"#0 = 1 + ∆)) − 1 !"+0 − !#,+ + ΔVsw

VON0: Initial voltage , CLP=C , CLN=C+ΔCExample: 5% mismatch, VON0 = 300mV, VSWN = 0.9V , ΔVsw = 20mV ⇒ Initial offset voltage VOS0 = 35mV!

Assume pre-amp gain = 8 ⇒ Equivalent offset a the input of pre-amp = 35/8 ≈ 4.4 mV.

Even considering offset of 2mV for the pre-amp the total equivalent input offset voltage ≈ 4.8 mV