11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters Data Sheet … · 2019. 10. 13. · 11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters Data Sheet AD9737A/AD9739A Rev. Information

11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters

Data Sheet AD9737A/AD9739A

Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.

FEATURES Direct RF synthesis at 2.5 GSPS update rate

DC to 1.25 GHz in baseband mode 1.25 GHz to 3.0 GHz in mix-mode

Industry leading single/multicarrier IF or RF synthesis Dual-port LVDS data interface

Up to 1.25 GSPS operation Source synchronous DDR clocking

Pin compatible with the AD9739 Programmable output current: 8.7 mA to 31.7 mA Low power: 1.1 W at 2.5 GSPS

APPLICATIONS Broadband communications systems

DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics

FUNCTIONAL BLOCK DIAGRAM

LVD

S D

DR

REC

EIVE

R

DCI

SDOSDIO

SCLKCS

DACCLK

DCOD

B0[

13:0

]D

B1[

13:0

]CLK DISTRIBUTION�

(DIV-BY-4)

DA

TAC

ON

TRO

LLER

4-TO

-1D

ATA

ASS

EMB

LER

SPI

RESET

DLL(MU CONTROLLER)

LVD

S D

DR

REC

EIVE

R

DA

TALA

TCH IOUTN

IOUTP

VREFI120

IRQ

1.2V

DAC BIAS

AD9737A/AD9739A

TxDACCORE

0961

6-00

1

Figure 1.

GENERAL DESCRIPTION The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS.

By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A.

The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.

The AD9737A/AD9739A are manufactured on a 0.18 µm CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics.

PRODUCT HIGHLIGHTS 1. Ability to synthesize high quality wideband signals with

bandwidths of up to 1.25 GHz in the first or second Nyquist zone.

2. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mix-mode operation.

3. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS.

4. On-chip controllers manage external and internal clock domain skews.

5. Programmable differential current output with an 8.66 mA to 31.66 mA range.

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AD9737A/AD9739A Data Sheet

Rev. | Page 2 of 64

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4

DC Specifications ......................................................................... 4 LVDS Digital Specifications ........................................................ 5 Serial Port Specifications ............................................................. 6 AC Specifications .......................................................................... 7

Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics—AD9737A ..................... 14

Static Linearity ............................................................................ 14 AC (Normal Mode) .................................................................... 15 AC (Mix-Mode) .......................................................................... 17 One-Carrier DOCSIS Performance (Normal Mode) ............ 20 Four-Carrier DOCSIS Performance (Normal Mode) ........... 21 Eight-Carrier DOCSIS Performance (Normal Mode) .......... 22 16-Carrier DOCSIS Performance (Normal Mode) ............... 23 32-Carrier DOCSIS Performance (Normal Mode) ............... 24 64- and 128-Carrier DOCSIS Performance (Normal Mode)25

Typical Performance Characteristics—AD9739A ..................... 26 Static Linearity ............................................................................ 26 AC (Normal Mode) .................................................................... 28 AC (Mix-Mode) .......................................................................... 31 One-Carrier DOCSIS Performance (Normal Mode) ............ 33 Four-Carrier DOCSIS Performance (Normal Mode) ........... 34 Eight-Carrier DOCSIS Performance (Normal Mode) .......... 35 16-Carrier DOCSIS Performance (Normal Mode) ............... 36 32-Carrier DOCSIS Performance (Normal Mode) ............... 37 64- and 128-Carrier DOCSIS Performance (Normal Mode)38

Terminology .................................................................................... 39 Serial Port Interface (SPI) Register ............................................... 40

SPI Register Map Description .................................................. 40 SPI Operation ............................................................................. 40

SPI Register Map ............................................................................ 42 SPI Port Configuration and Software Reset ........................... 43 Power-Down LVDS Interface and TxDAC® ........................... 43 Controller Clock Disable ........................................................... 43 Interrupt Request (IRQ) Enable/Status ................................... 44 TxDAC Full-Scale Current Setting (IOUTFS) and Sleep ........... 44 TxDAC Quad-Switch Mode of Operation .............................. 44 DCI Phase Alignment Status .................................................... 44 Data Receiver Controller Configuration ................................. 44 Data Receiver Controller_Data Sample Delay Value ............ 45 Data Receiver Controller_DCI Delay Value/Window and Phase Rotation ............................................................................ 45 Data Receiver Controller_Delay Line Status .......................... 45 Data Receiver Controller Lock/Tracking Status ..................... 45 CLK Input Common Mode ...................................................... 46 Mu Controller Configuration and Status ................................ 46 Part ID ......................................................................................... 47

Theory of Operation ...................................................................... 48 LVDS Data Port Interface .......................................................... 49 Mu Controller ............................................................................. 52 Interrupt Requests ...................................................................... 54

Analog Interface Considerations .................................................. 55 Analog Modes of Operation ..................................................... 55 Clock Input Considerations ...................................................... 56 Voltage Reference ....................................................................... 57 Analog Outputs .......................................................................... 57 Output Stage Configuration ..................................................... 59 Nonideal Spectral Artifacts ....................................................... 60 Lab Evaluation of the AD9737A/AD9739A ........................... 61 Recommended Start-Up Sequence .......................................... 61

Outline Dimensions ....................................................................... 63 Ordering Guide .......................................................................... 63

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Rev. C | Page 3 of 64

REVISION HISTORY

2/12—Rev. B to Rev. C

Changes to Figure 5 ........................................................................... 9 Changes to Table 7 .......................................................................... 11 Changes to Ordering Guide ........................................................... 63

2/12—Rev. A to Rev. B

Added AD9737A ................................................................ Universal Reorganized Layout ........................................................... Universal Moved Revision History Section ..................................................... 3 Deleted ±6% from Table Summary Statement; Changes to Table 1 ............................................................................................ 4 Deleted ±6% from Table Summary Statement, Table 2 ................ 5 Deleted ±6% from Table Summary Statement, Table 3 ................ 6 Changes to AC Specifications Section and Table 4 ....................... 7 Added Figure 5, Renumbered Sequentially ................................... 9 Added Figure 7 and Table 7, Renumbered Sequentially ............ 10 Deleted Figure 24 ............................................................................ 13 Added Typical Performance Characteristics—AD9737A Section and Figure 9 to Figure 77 ................................................. 14 Deleted Table 9 ................................................................................ 25 Added Static Linearity Section and Figure 78 to Figure 88 ............ 26 Added Figure 106 ............................................................................ 30 Changes to Figure 116, Figure 117, Figure 118, Figure 119, Figure 120, and Figure 121 ............................................................. 33 Changes to Figure 122, Figure 123, Figure 124, Figure 125, Figure 126, and Figure 127 ............................................................. 34 Changes to Figure 128, Figure 129, Figure 130, Figure 131, Figure 132, and Figure 133 ............................................................. 35 Changes to Figure 134, Figure 135, Figure 136, Figure 137, Figure 138, and Figure 139 ............................................................. 36 Changes to Figure 140, Figure 141, Figure 142, Figure 143, Figure 144, and Figure 145 ............................................................. 37 Changes to Figure 146, Figure 147, Figure 148, Figure 149, and Figure 150; Added Figure 151 ................................................ 38 Added Table 10 ................................................................................ 42

Added SPI Port Configuration and Software Reset Section, Power-Down LVDS Interface and TxDAC Section, Controller Clock Disable Section, and Table 11 to Table 13 ........................ 43 Added Interrupt Request (IRQ) Enable/Status Section, TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Section, TxDAC Quad-Switch Mode of Operation Section, DCI Phase Alignment Status Section, Data Receiver Controller Configuration Section, and Table 14 to Table 18 ........................ 44 Added Data Receiver Controller_Data Sample Delay Value Section, Data Receiver Controller_DCI Delay Value/Window and Phase Rotation Section, Data Receiver Controller_Delay Line Status Section, Data Receiver Controller Lock/Tracking Status Section, and Table 19 to Table 22 ...................................... 45 Added CLK Input Common Mode Section, and Mu Controller Configuration and Status Section, and Table 23 and Table 24 ..................................................................................... 46 Added Part ID Section, and Table 25 ........................................... 47 Changes to LVDS Data Port Interface Section ............................ 49 Changes to Data Receiver Controller Initialization Description Section ........................................................................ 51 Changes to Mu Controller Section ............................................... 52 Added Figure 167 and Table 27, Changes to Mu Controller Initialization Description Section ................................................. 53 Changes to Analog Modes of Operation Section, Figure 171, and Figure 172 ................................................................................. 55 Updated Outline Dimensions ........................................................ 63 Changes to Ordering Guide ........................................................... 63

7/11—Rev. 0 to Rev. A

Changed Maximum Update Rate (DACCLK Input) Parameter to DAC Clock Rate Parameter in Table 4 ....................................... 6 Added Adjusted DAC Update Rate Parameter and Endnote 1 in Table 4 ................................................................................................. 6 Updated Outline Dimensions ........................................................ 43

1/11—Revision 0: Initial Version


Rev. | Page 4 of 64

SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA.

Table 1. AD9737A AD9739A Parameter Min Typ Max Min Typ Max Unit RESOLUTION 11 14 Bits ACCURACY

Integral Nonlinearity (INL) ±0.5 ±2.5 LSB Differential Nonlinearity (DNL) ±0.5 ±2.0 LSB

ANALOG OUTPUTS Gain Error (with Internal Reference) 5.5 5.5 % Full-Scale Output Current 8.66 20.2 31.66 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 −1.0 +1.0 V Common-Mode Output Resistance 10 10 MΩ Differential Output Resistance 70 70 Ω Output Capacitance 1 1 pF

DAC CLOCK INPUT (DACCLK_P, DACCLK_N) Differential Peak-to-Peak Voltage 1.2 1.6 2.0 1.2 1.6 2.0 V Common-Mode Voltage 900 900 mV Clock Rate 1.6 2.5 1.6 2.5 GHz

TEMPERATURE DRIFT Gain 60 60 ppm/°C Reference Voltage 20 20 ppm/°C

REFERENCE Internal Reference Voltage 1.15 1.2 1.25 1.15 1.2 1.25 V Output Resistance 5 5 kΩ

ANALOG SUPPLY VOLTAGES VDDA 3.1 3.3 3.5 3.1 3.3 3.5 V VDDC 1.70 1.8 1.90 1.70 1.8 1.90 V

DIGITAL SUPPLY VOLTAGES VDD33 3.10 3.3 3.5 3.10 3.3 3.5 V VDD 1.70 1.8 1.90 1.70 1.8 1.90 V

SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS IVDDA 37 38 37 38 mA IVDDC 158 167 158 167 mA IVDD33 14.5 16 14.5 16 mA IVDD 173 183 173 183 mA Power Dissipation 0.770 0.770 W Sleep Mode, IVDDA 2.5 2.75 2.5 2.75 mA Power-Down Mode (All Power-Down Bits Set in Register 0x01 and

Register 0x02)

IVDDA 0.02 0.02 mA IVDDC 6 6 mA IVDD33 0.6 0.6 mA IVDD 0.1 0.1 mA

SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS IVDDC 223 223 mA IVDD33 14.5 14.5 mA IVDD 215 215 mA Power Dissipation 0.960 0.960 mW

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Rev. | Page 5 of 64

LVDS DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-1996 reduced range link, unless otherwise noted.

Table 2. Parameter Min Typ Max Unit LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1

Input Common-Mode Voltage Range, VCOM 825 1575 mV Logic High Differential Input Threshold, VIH_DTH 175 400 mV Logic Low Differential Input Threshold, VIL_DTH −175 −400 mV Receiver Differential Input Impedance, RIN 80 120 Ω Input Capacitance 1.2 pF LVDS Input Rate 1250 MSPS LVDS Minimum Data Valid Period (tMDE) (See Figure 159) 344 ps

LVDS CLOCK INPUT (DCI)2 Input Common-Mode Voltage Range, VCOM 825 1575 mV Logic High Differential Input Threshold, VIH_DTH 175 400 mV Logic Low Differential Input Threshold, VIL_DTH −175 −400 mV Receiver Differential Input Impedance, RIN 80 120 Ω Input Capacitance 1.2 pF Maximum Clock Rate 625 MHz

LVDS CLOCK OUTPUT (DCO)3 Output Voltage High (DCO_P or DCO_N) 1375 mV Output Voltage Low (DCO_P or DCO_N) 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, RO 80 100 120 Ω RO Single-Ended Mismatch 10 % Maximum Clock Rate 625 MHz

1 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins. 2 DCI_P and DCI_N pins. 3 DCO_P and DCO_N pins with 100 Ω differential termination.

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Rev. | Page 6 of 64

SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.

Table 3. Parameter Min Typ Max Unit WRITE OPERATION (See Figure 154)

SCLK Clock Rate, fSCLK, 1/tSCLK 20 MHz SCLK Clock High, tHIGH 18 ns SCLK Clock Low, tLOW 18 ns SDIO to SCLK Setup Time, tDS 2 ns SCLK to SDIO Hold Time, tDH 1 ns CS to SCLK Setup Time, tS 3 ns

SCLK to CS Hold Time, tH 2 ns

READ OPERATION (See Figure 155 and Figure 156) SCLK Clock Rate, fSCLK, 1/tSCLK 20 MHz SCLK Clock High, tHIGH 18 ns SCLK Clock Low, tLOW 18 ns SDIO to SCLK Setup Time, tDS 2 ns SCLK to SDIO Hold Time, tDH 1 ns CS to SCLK Setup Time, tS 3 ns

SCLK to SDIO (or SDO) Data Valid Time, tDV 15 ns CS to SDIO (or SDO) Output Valid to High-Z, tEZ 2 ns

INPUTS (SDI, SDIO, SCLK, CS)

Voltage in High, VIH 2.0 3.3 V Voltage in Low, VIL 0 0.8 V Current in High, IIH −10 +10 µA Current in Low, IIL −10 +10 µA

OUTPUT (SDIO) Voltage Out High, VOH 2.4 3.5 V Voltage Out Low, VOL 0 0.4 V Current Out High, IOH 4 mA Current Out Low, IOL 4 mA

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Rev. | Page 7 of 64

AC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS, unless otherwise noted.

Table 4. AD9737A AD9739A Parameter Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE

DAC Clock Rate 1600 2500 1600 2500 MSPS Adjusted DAC Update Rate1 1600 2500 1600 2500 MSPS Output Settling Time to 0.1% 13 13 ns

SPURIOUS-FREE DYNAMIC RANGE (SFDR) fOUT = 100 MHz 70 70 dBc fOUT = 350 MHz 65 65 dBc fOUT = 550 MHz 58 58 dBc fOUT = 950 MHz 55 55 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD), fOUT2 = fOUT1 + 1.25 MHz

fOUT = 100 MHz 94 94 dBc fOUT = 350 MHz 78 78 dBc fOUT = 550 MHz 72 72 dBc fOUT = 950 MHz 68 68 dBc

NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE fOUT = 100 MHz −162 −167 dBm/Hz fOUT = 350 MHz −162 −166 dBm/Hz fOUT = 550 MHz −161 −164 dBm/Hz fOUT = 850 MHz −161 −163 dBm/Hz

WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL

fDAC = 2457.6 MSPS, fOUT = 350 MHz 80/81 80/80 dBc fDAC = 2457.6 MSPS, fOUT = 950 MHz 75/75 78/79 dBc fDAC = 2457.6 MSPS, fOUT = 1700 MHz (Mix-Mode) 69/71 74/74 dBc fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix-Mode) 66/67 69/72 dBc

1 Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor

is 1. Thus, with fDAC = 2500 MSPS, fDAC, adjusted, = 2500 MSPS.

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Rev. | Page 8 of 64

ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating VDDA to VSSA −0.3 V to +3.6 V VDD33 to VSS −0.3 V to +3.6 V VDD to VSS −0.3 V to +1.98 V VDDC to VSSC −0.3 V to +1.98 V VSSA to VSS −0.3 V to +0.3 V VSSA to VSSC −0.3 V to +0.3 V VSS to VSSC −0.3 V to +0.3 V DACCLK_P, DACCLK_N to VSSC −0.3 V to VDDC + 0.18 V DCI, DCO to VSS −0.3 V to VDD33 + 0.3 V LVDS Data Inputs to VSS −0.3 V to VDD33 + 0.3 V IOUTP, IOUTN to VSSA −1.0 V to VDDA + 0.3 V I120, VREF to VSSA −0.3 V to VDDA + 0.3 V IRQ, CS, SCLK, SDO, SDIO, RESET to VSS −0.3 V to VDD33 + 0.3 V

Junction Temperature 150°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance Package Type θJA θJC Unit 160-Ball CSP_BGA 31.2 7.0 °C/W1

1 With no airflow movement.

ESD CAUTION

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

0961

6-00

2

AD9737A/AD9739A

1413121110876321 954

A

B

C

D

E

F

G

H

J

K

L

M

N

P

VSSA, ANALOG SUPPLY GROUNDVSSA SHIELD, ANALOG SUPPLY GROUND SHIELD

VDDA, 3.3V, ANALOG SUPPLY

Figure 2. Analog Supply Pins (Top View)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

1413121110876321 954

VSS DIGITAL SUPPLY GROUNDVDD33, 3.3V DIGITAL SUPPLY

VDD, 1.8V, DIGITAL SUPPLY

0961

6-00

3

AD9737A/AD9739A

Figure 3. Digital Supply Pins (Top View)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

1413121110876321 954

VSSC, CLOCK SUPPLY GROUNDVDDC, 1.8V, CLOCK SUPPLY

0961

6-00

4

AD9737A/AD9739A

Figure 4. Digital LVDS Clock Supply Pins (Top View)

AB

EFGHJKLDB1[0:10]PMDB1[0:10]N

CDACCLK_NDDACCLK_P

DB0[0:10]P NDB0[0:10]N P

1413121110876321 954

DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)

DCI_P/_NDCO_P/_N

0961

6-03

6

AD9737A

Figure 5. AD9737A Digital LVDS Input, Clock I/O (Top View)

ABCDEFGHJKLM

DB1[0:13]PDB1[0:13]NDB0[0:13]PDB0[0:13]N

DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)

DACCLK_NDACCLK_P

NP

1413121110876321 954

DCI_P/_NDCO_P/_N

0961

6-00

5

AD9739A

Figure 6. AD9739A Digital LVDS Input, Clock I/O (Top View)



Rev. | Page 10 of 64

A

B

C

D

E

F

G

H

J

K

L

M

N

P

14131211106321 954

IRQCS

SCLK

RESETSDIOSDO

7

IOU

TN

8

IOU

TP

I120

VREF

0961

6-00

6

AD9737A

Figure 7. AD9737A Analog I/O and SPI Control Pins (Top View)

Table 7. AD9737A Pin Function Descriptions Pin No. Mnemonic Description C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5

VSSC Clock Supply Ground.

A10, A11, B10, B11, C10, C11, D10, D11 VDDA 3.3 V Analog Supply Input. A12, A13, B12, B13, C12, C13, D12, D13, VSSA Analog Supply Ground. A6, A9, B6, B9, C6, C9, D6, D9, E11, E12, E13, E14, F1, F2, F3, F4, F11, F12

VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC.

A14 NC Do not connect to this pin. A7, B7, C7, D7 IOUTN DAC Negative Current Output Source. A8, B8, C8, D8 IOUTP DAC Positive Current Output Source. B14 I120 Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ

resistor to generate a 120 µA reference current. C14 VREF Voltage Reference Input/Output. Decouple to VSSA with a 1 nF

capacitor. D14 NC Factory Test Pin. Do not connect to this pin. C3, D3 DACCLK_N/DACCLK_P Negative/Positive DAC Clock Input (DACCLK). F13 IRQ Interrupt Request Open Drain Output. Active high. Pull up to

VDD33 with a 10 kΩ resistor. F14 RESET Reset Input. Active high. Tie to VSS if unused. G13 CS Serial Port Enable Input.

G14 SDIO Serial Port Data Input/Output. H13 SCLK Serial Port Clock Input. H14 SDO Serial Port Data Output. J3, J4, J11, J12 VDD33 3.3 V Digital Supply Input. G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply Input. H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Ground. J1, J2 NC Differential resistor of 200 Ω exists between J1 and J2. Do not

connect to this pin. K1, K2 NC Differential resistor of 100 Ω exists between K1 and K2. Do not

connect to this pin. J13, J14 DCO_P/DCO_N Positive/Negative Data Clock Output (DCO). K13, K14 DCI_P/DCI_N Positive/Negative Data Clock Input (DCI).

C




Pin No. Mnemonic Description L1, M1 NC, NC Do not connect to this pin. L2, M2 NC, NC Do not connect to this pin. L3, M3 NC, NC Do not connect to this pin. L4, M4 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0. L5, M5 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1. L6, M6 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2. L7, M7 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3. L8, M8 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4. L9, M9 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5. L10, M10 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6. L11, M11 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7. L12, M12 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8. L13, M13 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9. L14, M14 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10. N1, P1 NC, NC Do not connect to this pin. N2, P2 NC, NC Do not connect to this pin. N3, P3 NC, NC Do not connect to this pin. N4, P4 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0. N5, P5 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1. N6, P6 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2. N7, P7 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3. N8, P8 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4. N9, P9 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5. N10, P10 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. N11, P11 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. N12, P12 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. N13, P13 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. N14, P14 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10.



A

B

C

D

E

F

G

H

J

K

L

M

N

P

14131211106321 954

IRQCS

SCLK

RESETSDIOSDO

7

IOU

TN

8

IOU

TP

I120

VREF

0961

6-03

7

AD9739A

Figure 8. AD9739A Analog I/O and SPI Control Pins (Top View)

Table 8. AD9739A Pin Function Descriptions Pin No. Mnemonic Description C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5

VSSC Clock Supply Ground.

A10, A11, B10, B11, C10, C11, D10, D11 VDDA 3.3 V Analog Supply Input. A12, A13, B12, B13, C12, C13, D12, D13, VSSA Analog Supply Ground. A6, A9, B6, B9, C6, C9, D6, D9, E11, E12, E13, E14, F1, F2, F3, F4, F11, F12

VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC.

A14 NC Do not connect to this pin. A7, B7, C7, D7 IOUTN DAC Negative Current Output Source. A8, B8, C8, D8 IOUTP DAC Positive Current Output Source. B14 I120 Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ

resistor to generate a 120 μA reference current. C14 VREF Voltage Reference Input/Output. Decouple to VSSA with a 1 nF

capacitor. D14 NC Factory Test Pin. Do not connect to this pin. C3, D3 DACCLK_N/DACCLK_P Negative/Positive DAC Clock Input (DACCLK). F13 IRQ Interrupt Request Open Drain Output. Active high. Pull up to

VDD33 with a 10 kΩ resistor. F14 RESET Reset Input. Active high. Tie to VSS if unused. G13 CS Serial Port Enable Input.

G14 SDIO Serial Port Data Input/Output. H13 SCLK Serial Port Clock Input. H14 SDO Serial Port Data Output. J3, J4, J11, J12 VDD33 3.3 V Digital Supply Input. G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply Input. H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Ground. J1, J2 NC Differential resistor of 200 Ω exists between J1 and J2. Do not

connect to this pin. K1, K2 NC Differential resistor of 100 Ω exists between K1 and K2. Do not

connect to this pin. J13, J14 DCO_P/DCO_N Positive/Negative Data Clock Output (DCO). K13, K14 DCI_P/DCI_N Positive/Negative Data Clock Input (DCI).




Pin No. Mnemonic Description L1, M1 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0. L2, M2 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1. L3, M3 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2. L4, M4 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3. L5, M5 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4. L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5. L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6. L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7. L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8. L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9. L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10. L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11. L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12. L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13. N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0. N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1. N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2. N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3. N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4. N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5. N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11. N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12. N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13.



TYPICAL PERFORMANCE CHARACTERISTICS—AD9737A STATIC LINEARITY IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.

0.3

–0.40 2048

ER

RO

R (L

SB

)

CODE

–0.3

–0.2

–0.1

0

0.1

0.2

256 512 768 1024 1280 1536 1792

0961

6-10

9

Figure 9. Typical INL, 20 mA at 25°C

0.4

–0.30 2048

ER

RO

R (L

SB

)

CODE

–0.2

–0.1

0

0.1

0.2

0.3

256 512 768 1024 1280 1536 1792

0961

6-11

0

Figure 10. Typical DNL, 20 mA at 25°C

0.25

–0.250 2048

ERR

OR

(LSB

)

CODE

–0.20

–0.10

–0.15

–0.05

0

0.10

0.05

0.15

0.20

256 512 768 1024 1280 1536 1792

0961

6-11

1


0.25

–0.250 2048

ERR

OR

(LSB

)

CODE

–0.20

–0.10

–0.15

–0.05

0

0.10

0.05

0.15

0.20

256 512 768 1024 1280 1536 1792

0961

6-11

2


0.6

–0.6

–0.5

–0.4

–0.3

0 2048

ERR

OR

(LSB

)

CODE

–0.2

–0.1

0

0.1

0.2

0.3

0.5

0.4

256 512 768 1024 1280 1536 1792

0961

6-11

3


0.2

–0.8

–0.7

–0.6

–0.5

–0.4

–0.3

0 2048

ERR

OR

(LSB

)

CODE

–0.2

–0.1

0

0.1

256 512 768 1024 1280 1536 1792

0961

6-11

4


C

http://www.analog.com/AD9737A



AC (NORMAL MODE) IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.

10dB

/DIV

STOP 2.4GHzSTART 20MHzVBW 20kHz 09

616-

115

Figure 15. Single Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS

10dB

/DIV

VBW 20kHz

STOP 2.4GHzSTART 20MHz

0961

6-11

6

Figure 16. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS

90

80

0

10

20

30

40

50

60

70

0 12001000800600400200

SFD

R (d

Bc)

fOUT (MHz)

1.6GSPS

2.4GSPS1.2GSPS

2.0GSPS

0961

6-11

7

Figure 17. SFDR vs. fOUT over fDAC

120

100

80

60

40

20

00 200 400 600 800 1000 1200 1400

IIMD

(dB

c)

fOUT (MHz)

2.0GSPS

1.6GSPS

1.2GSPS

2.4GSPS

0961

6-11

8

Figure 18. IMD vs. fOUT over fDAC

–150

–1700 200 400 600 800 1000 1200

NSD

(dB

m/H

z)

fOUT (MHz)

1.2GSPS

2.4GSPS

–168

–166

–164

–162

–160

–158

–156

–154

–152

0961

6-11

9

Figure 19. Single-Tone NSD over fOUT

–150

–1700 200 400 600 800 1000 1200

NSD

(dB

m/H

z)

fOUT (MHz)

1.2GSPS

2.4GSPS

–168

–166

–164

–162

–160

–158

–156

–154

–152

0961

6-12

0

Figure 20. Eight-Tone NSD over fOUT

C



fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.

90

300 200 300100 400 600 700500 900800 1000

SFD

R (d

Bc)

fOUT (MHz)

35

40

45

50

55

60

65

70

75

80

85

–3dBFS

0dBFS

–6dBFS

0961

6-12

1

Figure 21. SFDR vs. fOUT over Digital Full Scale

90

300 200 400 600 800 1000

SFD

R (d

Bc)

fOUT (MHz)

40

50

60

70

80

–3dBFS

0dBFS

–6dBFS

0961

6-12

2

Figure 22. SFDR for Second Harmonic vs. fOUT over Digital Full Scale

90

300 200 400 600 800 1000

SFD

R (d

Bc)

fOUT (MHz)

40

50

60

70

80

0dBFS

–6dBFS

–3dBFS

0961

6-12

3

Figure 23. SFDR for Third Harmonic vs. fOUT over Digital Full Scale

100

400 1000

IMD

(dB

c)

fOUT (MHz)

0dBFS

45

50

55

60

65

70

75

80

85

90

95

100 200 300 400 500 600 700 800 900

–3dBFS

–6dBFS

0961

6-12

4

Figure 24. IMD vs. fOUT over Digital Full Scale

30

40

35

0 1000

SFD

R (d

Bc)

fOUT (MHz)

45

50

55

60

65

70

75

80

85

90

100 200 300 400 500 600 700 800 900

30mA FS

10mA FS

20mA FS

0961

6-12

5

Figure 25. SFDR vs. fOUT over DAC IOUTFS

400 1000

IMD

(dB

c)

fOUT (MHz)

45

50

55

60

65

70

75

80

85

90

95

100

100 200 300 400 500 600 700 800 900

20mA FS

30mA FS

10mA FS09

616-

126

Figure 26. IMD vs. fOUT over DAC IOUTFS

C



AC (MIX-MODE) fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.

0961

6-12

7

30

40

35

0 1000

SFD

R (d

Bc)

fOUT (MHz)

45

50

55

60

65

70

75

80

85

90

100 200 300 400 500 600 700 800 900

+85°C

–40°C

+25°C

Figure 27. SFDR vs. fOUT over Temperature 09

616-

128

400 1000

IMD

(dB

c)

fOUT (MHz)

45

50

55

60

65

70

75

80

85

90

95

100

100 200 300 400 500 600 700 800 900

–40°C

+25°C

+85°C

Figure 28. IMD vs. fOUT over Temperature

0961

6-12

9

–170

–168

–166

–164

–162

–160

–158

–156

–154

–152

–150

0 200 400 600 800 1000100 300 500 700 900

fOUT (MHz)

NSD

(dB

m/H

z)

+25°C

+85°C

Figure 29. Single-Tone NSD vs. fOUT over Temperature

0961

6-13

0

–170

–168

–166

–164

–162

–160

–158

–156

–154

–152

–150

0 200 400 600 800 1000100 300 500 700 900

fOUT (MHz)

NSD

(dBm

/Hz)

+25°C

+85°C

Figure 30. Eight-Tone NSD vs. fOUT over Temperature

SPAN 54.68MHzSWEEP 1.509s

CENTER 350MHz#RES BW 30kHz

UPPERFILTERONONONONON

dBc–79.73–80.21–80.85–81.41–81.46

dBc–80.51–81.11–81.67–81.61–82.19

dBm–92.90–93.38–94.01–94.58–94.63

LOWERdBm

–93.67–94.27–94.84–94.77–95.35

INTEG BW3.840MHz3.840MHz3.840MHz3.840MHz3.840MHz

OFFSET FREQ5.000MHz10.00MHz15.00MHz20.00MHz25.00MHz

CARRIER POWER –13.167dBm/3.84MHz ACP-IBW

10dB

/DIV

–35

–45

–55

–65

–75

–85

–95

–105

–115

0961

6-13

1

VBW 3kHz

–81.4dBc–81.1dBc –80.5dBc –13.2dBm –80.8dBc–80.2dBc–79.7dBc –81.5dBc–81.6dBc–82.2dBc –81.7dBc

Figure 31. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS

–50

–55

–60

–65

–70

–75

–80

–85

–900 200 400 600 800 140012001000

AC

LR (d

Bc)

fOUT (MHz) 0961

6-22

6

FIRST ADJ CH

FIFTH ADJ CH

SECOND ADJ CH

Figure 32. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS

C



fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.

0961

6-13

2

10dB

/DIV

STOP 2.4GHzSWEEP 7.174s (601pts)

START 20MHz#RES BW 20kHz

VBW 20kHz Figure 33. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS

0961

6-13

3

10dB

/DIV



VBW 20kHz

Figure 34. Single-Tone Spectrum at fOUT = 1.31 GHz, fDAC = 2.4 GSPS

0961

6-13

4

101520253035404550556065707580

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

fOUT (MHz)

SFD

R (d

Bc)

Figure 35. SFDR in Mix-mode vs. fOUT at 2.4 GSPS

0961

6-13

530

40

50

60

70

90

80

100

1000 130012001100 1400 1500 1600 1700 1800 1900 2000

IMD

(dB

c)

fOUT (MHz) Figure 36. IMD in Mix-Mode vs. fOUT at 2.4 GSPS

0961

6-13

6


CENTER 2.108MHz#RES BW 30kHz


dBc–69.84–71.15–71.75–72.19–72.70

dBc–69.82–69.93–71.77–72.26–71.90

dBm–89.36–90.67–91.28–91.71–92.22

LOWERdBm

–88.34–89.46–91.29–91.79–91.42




10dB

/DIV

–35

–45

–55

–65

–75

–85

–95

–105

–115

VBW 3kHz

–72.7dBc–71.8dBc –69.9dBc –68.8dBc –19.5dBm–72.3dBc–71.9dBc –69.8dBc –71.1dBc –71.8dBc –72.2dBc

Figure 37. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,

fDAC = 2457.6 MSPS (Second Nyquist Zone)

–90

–85

–80

–75

–70

–65

–60

–55

–50

1307

.6

3557

.6

1557

.6

1807

.6

2057

.6

2307

.6

2557

.6

2807

.6

3057

.6

3307

.6

SECOND NYQUIST ZONE THIRD NYQUIST ZONE

FIRST ADJ CH

THIRD ADJ CHACL

R(d

Bc)

0961

6-13

7

fOUT (MHz)

SECOND ADJ CH

Figure 38. Single-Carrier WCDMA ACLR vs. fOUT, fDAC = 2457.6 MSPS

C




0961

6-13

8




dBc–65.56–65.82–65.98–66.06–66.14

dBc–65.65–65.70–65.81–65.84–65.84

dBm–94.72–94.98–95.14–95.22–95.31

LOWERdBm

–94.81–94.86–94.97–95.00–95.00




10dB

/DIV

–45

–55

–65

–75

–85

–95

–115

–105

–125

VBW 3kHz

–66.1dBc –66.1dBc–65.8dBc –65.7dBc –65.6dBc –29.2dBm–65.8dBc –65.8dBc –65.6dBc –65.8dBc –66.0dBc

Figure 39. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone)

0961

6-13

9




dBc–64.93–64.26–65.21–65.74–66.13

dBc–65.42–64.93–65.12–65.24–65.61

dBm–92.23–91.56–92.50–93.04–93.42

LOWERdBm

–92.72–92.23–92.42–92.53–92.91




10dB

/DIV

–50

–60

–70

–80

–90

–100

–120

–110

–130

VBW 3kHz

–65.2dBc–65.4dBc

–27.6dBm–27.6dBm

–27.3dBm–27.4dBm

–64.9dBc–64.9dBc–64.3dBc –65.7dBc

–66.1dBc–65.1dBc

–65.2dBc–65.6dBc

Figure 40. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz,

fDAC = 2457.6 MSPS (Second Nyquist Zone) 09

616-

140




dBc–58.20–58.15–58.26–58.33–58.21

dBc–58.05–57.95–57.95–57.97–58.05

dBm–95.26–95.21–95.32–95.39–95.27

LOWERdBm

–95.11–95.02–95.01–95.04–95.11




10dB

/DIV

–60

–70

–80

–90

–100

–110

–130

–120

–140

VBW 3kHz

–58.3dBc–58.0dBc

–37.4dBm–37.1dBm

–37.1dBm–36.9dBm

–58.2dBc–58.0dBc–58.1dBc –58.3dBc

–58.2dBc–57.9dBc

–58.0dBc–58.0dBc

Figure 41. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz,

fDAC = 2457.6 MSPS (Third Nyquist Zone)

C



ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.

0961

6-14

1

10dB

/DIV

VBW 2kHz STOP 1GHzSWEEP 24.1s (1001pts)


FUNCTIONVALUE

FUNCTIONWIDTHFUNCTION

–10.238dBm–74.467dB–77.224dB–78.437dB–67.413dB

6MHz6MHz6MHz6MHz6MHz

BAND POWERBAND POWERBAND POWERBAND POWERBAND POWER

(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

Y–10.238dBm–74.467dB–77.224dB–78.437dB–67.413dB

fffff

11111

12345

XNΔ1Δ1Δ1Δ1

MODEMKR SCLTRC200.10MHz199.50MHz399.95MHz599.45MHz413.25MHz

–30

–40

–50

–60

–70

–80

–90

–100

–110 4Δ1

1

2Δ1 3Δ1

5Δ1

Figure 42. Low Band Wideband ACLR

0961

6-14

2

10dB

/DIV



FUNCTIONVALUE


–11.538dBm–74.399dB–74.344dB–68.472dB–66.197dB



(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

Y–11.538dBm–74.421dB–76.294dB–68.472dB–66.156dB

fffff

11111

12345

XNΔ1Δ1Δ1Δ1

MODEMKR SCLTRC550.65MHz–487.35MHz125.40MHz253.65MHz62.70MHz

–30

–40

–50

–60

–70

–80

–90

–100

–1103Δ1

2Δ1

1

4Δ15Δ1

Figure 43. Mid Band Wideband ACLR

0961

6-14

3

10dB

/DIV



FUNCTIONVALUE


–14.446dBm–60.856dB–66.013dB–68.697dB–63.533dB–68.162dB

6MHz6MHz6MHz6MHz6MHz6MHz

BAND POWERBAND POWERBAND POWERBAND POWERBAND POWERBAND POWER

(Δ)(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)(Δ)

Y–14.418dBm–60.856dB–66.000dB–68.751dB–63.533dB–66.162dB

ffffff

111111

123456

XNΔ1Δ1Δ1Δ1Δ1

MODEMKR SCLTRC 948.70MHz–393.30MHz–553.85MHz–612.75MHz–335.35MHz–57.95MHz

–30

–40

–50

–60

–70

–80

–90

–100

–110

3Δ1 5Δ14Δ1

2Δ1

6Δ1

1

Figure 44. High Band Wideband ACLR

0961

6-14

4

SPAN 54MHzSWEEP 1.49s

VBW 3kHzCENTER 200MHz#RES BW 30kHz

UPPERFILTEROFFOFFOFFOFFOFF

dBc–57.47–79.87–78.96–78.69–78.68

dBc–58.34–79.27–78.44–78.59–78.41

dBm–67.70–90.10–89.19–88.92–88.90

LOWERdBm

–68.57–89.50–88.66–88.82–88.63

INTEG BW750.0kHz5.250MHz6.000MHz6.000MHz6.000MHz


CARRIER POWER –10.226dBm/6MHz ACP-IBW

10dB

/DIV

–30

–40

–50

–60

–70

–80

–90

–100

–110

–78.4dBc –78.6dBc –78.4dBc –79.3dBc –10.2dBm –79.9dBc –79.0dBc –78.7dBc–78.7dBc

Figure 45. Low Band Narrow-Band ACLR

0961

6-14

5




dBc–60.92–74.14–74.68–74.91–75.34

dBc–59.37–74.02–74.53–75.00–75.97

dBm–73.03–86.25–86.79–87.01–87.44

LOWERdBm

–71.48–86.12–86.63–87.11–88.08




10dB

/DIV

–30

–40

–50

–60

–70

–80

–90

–100

–110


Figure 46. Mid Band Narrow-Band ACLR

0961

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6




dBc–61.30–69.39–70.50–71.02–71.75

dBc–57.84–69.02–70.01–70.89–71.94

dBm–74.89–82.98–84.09–84.61–85.34

LOWERdBm

–71.43–82.61–83.60–84.48–85.53




10dB

/DIV

–30

–40

–50

–60

–70

–80

–90

–100

–110


Figure 47. High Band Narrow-Band ACLR

C



FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.

STOP 1GHzSWEEP 24.1s (1001pts)


10dB

/DIV

–30

–40

–50

–60

–70

–80

–90

–100

–110

0961

6-14

7

VBW 2kHz

1

2Δ1

5Δ1

3Δ1 4Δ1

FUNCTIONVALUE


–18.419dBm–69.277dB–71.485dB–72.343dB–59.518dB



(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

Y–18.419dBm–69.252dB–71.282dB–72.100dB–59.520dB

fffff

11111

12345

XNΔ1Δ1Δ1Δ1

MODEMKR SCLTRC200.10MHz221.35MHz431.30MHz651.70MHz413.25MHz




10dB

/DIV

–30

–40

–50

–60

–70

–80

–90

–100

–110

0961

6-14

8

VBW 2kHz

1

2Δ1

5Δ1

3Δ14Δ1

FUNCTIONVALUE


–19.885dBm–70.252dB–69.581dB–67.793dB–58.085dB



(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

Y–19.885dBm–70.252dB–69.535dB–67.793dB–58.085dB

fffff

11111

12345

XNΔ1Δ1Δ1Δ1

MODEMKR SCLTRC549.70MHz–486.40MHz126.35MHz228.00MHz63.65MHz




10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

0961

6-14

9

VBW 2kHz

1

2Δ1

5Δ1

6Δ13Δ14Δ1

FUNCTIONVALUE


–21.676dBm–62.206dB–65.730dB–67.064dB–56.405dB–65.729dB

6MHz6MHz6MHz6MHz6MHz6MHz

BAND POWERBAND POWERBAND POWERBAND POWERBAND POWERBAND POWER

(Δ)(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)(Δ)

Y–21.631dBm–62.206dB–65.730dB–67.064dB–56.405dB–65.729dB

ffffff

111111

123456

XNΔ1Δ1Δ1Δ1Δ1

MODEMKR SCLTRC950.60MHz–415.15MHz–529.15MHz–610.85MHz–337.25MHz–59.85MHz





dBc–58.82–73.28–72.92–73.50–73.74

dBc–10.82–0.566–0.123–0.028–53.18

dBm–76.71–91.17–90.81–91.39–91.63

LOWERdBm

–28.71–18.46–17.77–17.86–71.07

INTEG BW750kHz5.25kHz6MHz6MHz6MHz



10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

0961

6-15

0

VBW 3kHz

–53.2dBc 0dBc –73.5dBc–72.9dBc –73.7dBc0.1dBc –0.6dBc

–17.9dBc

–73.3dBc

Figure 51. Low Band Narrow-Band ACLR (Worse Side)




dBc–10.49–0.526–0.160–0.024–54.18

dBc–58.29–68.28–68.47–69.72–70.64

dBm–30.02–20.06–19.69–19.56–73.72

LOWERdBm

–77.82–87.81–88.00–89.25–90.17




10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

0961

6-15

1

VBW 3kHz

–70.6dBc –69.7dBc 0dBc–0.2dBc –54.2dBc–68.5dBc –68.3dBc

–19.5dBc

–0.5dBc

Figure 52. Mid Band Narrow-Band ACLR (Worse Side)




dBc–11.04–0.437–0.172–0.098–53.11

dBc–59.52–63.90–64.29–65.41–66.57

dBm–32.55–21.95–21.68–21.41–74.62

LOWERdBm

–81.03–85.41–85.80–86.92–88.08




10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

0961

6-15

2

VBW 3kHz

–66.6dBc –65.4dBc 0.1dBc–0.2dBc –53.1dBc–64.3dBc –63.9dBc

–21.5dBm

–0.4dBc

Figure 53. High Band Narrow-Band ACLR (Worse Side) C



EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.



10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–120

–110

0961

6-15

3VBW 2kHz

1

2Δ1

3Δ1

FUNCTIONVALUE


–22.253dBm–66.457dB–55.791dB

6MHz6MHz6MHz

BAND POWERBAND POWERBAND POWER

(Δ)(Δ)

(Δ)(Δ)

(Δ)(Δ)

Y–22.253dBm–66.457dB–55.791dB

fff

111

123

XNΔ1Δ1

MODEMKR SCLTRC200.10MHz235.60MHz431.25MHz




10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

0961

6-15

4

VBW 2kHz

1

2Δ1

3Δ1

FUNCTIONVALUE


–23.585dBm–54.206dB–66.628dB

6MHz6MHz6MHz


(Δ)(Δ)

(Δ)(Δ)

(Δ)(Δ)

Y–23.586dBm–54.209dB–66.696dB

fff

111

123

XNΔ1Δ1





10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

0961

6-15

5

VBW 2kHz

1

2Δ1

5Δ1

4Δ13Δ1

FUNCTIONVALUE


–26.330dBm–61.574dB–63.268dB–62.616dB–51.728dB



(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

Y–26.330dBm–61.549dB–63.183dB–62.616dB–51.728dB

fffff

11111

12345

XNΔ1Δ1Δ1Δ1

MODEMKR SCLTRC950.60MHz–448.40MHz–582.35MHz–80.75MHz–338.20MHz


0961

6-15

6



UPPERFILTEROFFOFFOFFOFF

dBc–10.96–0.572–0.250–0.186

dBc–55.24–70.28–69.23–69.11

dBm–34.25–23.86–23.54–23.47

LOWERdBm

–78.53–93.56–92.52–92.40

INTEG BW750kHz5.25MHz6MHz6MHz

OFFSET FREQ3.375MHz6.375MHz12.00MHz18.00MHz


10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

VBW 3kHz

–69.1dBc –69.2dBc –70.3dBc –23.3dBc –0.6dBc –0.2dBc–0.3dBc

Figure 57. Low Band Narrow-Band ACLR (Worse Side)

0961

6-15

7



UPPERFILTEROFFOFFOFFOFF

dBc–56.23–66.75–66.45–66.78

dBc–10.79–0.089–0.289–0.145

dBm–79.91–90.43–90.12–90.46

LOWERdBm

–34.47–23.76–23.39–23.53

INTEG BW750kHz5.25kHz6MHz6MHz

OFFSET FREQ3.375MHz6.375MHz12.00MHz18.00MHz


10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

VBW 3kHz

0.1dBc 0.3dBc–66.8dBc–66.4dBc

–0.1dBc

–23.7dBc

–66.8dBc


0961

6-15

8




dBc–10.99–0.366–0.073–0.053–0.225

dBc–60.71–62.67–62.21–62.68–63.49

dBm–37.38–26.75–26.31–26.33–26.16

LOWERdBm

–87.10–89.06–88.60–89.07–89.88




10dB

/DIV

–40

–50

–60

–70

–80

–90

–100

–110

–120

VBW 3kHz

–63.5dBc –62.7dBc0.1dBc0.1dBc 0.2dBc

–62.2dBc –62.7dBc

–26.4dBm

–0.4dBc


C



16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.

0961

6-15

9

10dB

/DIV



FUNCTIONVALUE


–26.391dBm–64.927dB–65.369dB–51.688dB

6MHz6MHz6MHz6MHz

BAND POWERBAND POWERBAND POWERBAND POWER

(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

Y–26.390dBm–64.811dB–65.150dB–51.688dB

ffff

1111

1234

XNΔ1Δ1Δ1

MODEMKR SCLTRC160.20MHz80.75MHz232.75MHz452.20MHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

1

2Δ13Δ1

4Δ1


0961

6-16

0

10dB

/DIV



FUNCTIONVALUE


–27.503dBm–63.639dB–62.631dB–63.408dB

6MHz6MHz6MHz6MHz


(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

Y–27.503dBm–63.639dB–62.748dB–63.408dB

ffff

1111

1234

XNΔ1Δ1Δ1

MODEMKR SCLTRC549.70MHz–486.40MHz126.35MHz254.60MHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

2Δ1

1

3Δ1 4Δ1


0961

6-16

1

10dB

/DIV



FUNCTIONVALUE


–28.493dBm–60.066dB–61.070dB–61.014dB–49.417dB



(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)(Δ)

Y–28.493dBm–60.066dB–61.070dB–61.014dB–49.417dB

fffff

11111

12345

XNΔ1Δ1Δ1Δ1

MODEMKR SCLTRC899.30MHz–343.90MHz–504.45MHz–563.35MHz–285.95MHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

4Δ1 3Δ1

5Δ1

2Δ1

1


0961

6-16

2




dBc–61.30–65.24–63.93–64.07–64.08

dBm–87.55–91.49–90.18–90.32–90.33

LOWERdBc

–10.95–0.314–0.166–0.125–0.034

dBm–37.20–26.56–26.42–26.38–26.28




10dB

/DIV

0.0dBc –0.1dBc –0.2dBc –0.3dBc –26.3dBm –65.2dBc –63.9dBc –64.1dBc–64.1dBc

–50

–60

–70

–80

–90

–100

–110

–120

–130


0961

6-16

3




dBc–60.24–63.87–62.76–63.08–63.33

dBm–87.62–91.26–90.15–90.46–90.72

LOWERdBc

–11.65–0.239–0.199–0.282–0.288

dBm–39.04–27.63–27.19–27.10–27.10




10dB

/DIV

0.3dBc 0.3dBc 0.2dBc –0.2dBc –27.4dBm –63.9dBc –62.8dBc –63.3dBc–63.1dBc

–45

–55

–65

–75

–85

–95

–105

–115

–125


0961

6-16

4




dBc–11.14–0.446–0.271–0.318–0.147

dBm–39.25–28.56–28.38–28.43–28.26

LOWERdBc

–58.27–61.84–61.30–62.11–62.66

dBm–86.38–89.95–89.42–90.22–90.77




10dB

/DIV

–62.7dBc –62.1dBc –61.3dBc 61.8dBc –28.1dBm ––0.4dBc –0.3dBc –0.1dBc–0.3dBc

–45

–55

–65

–75

–85

–95

–105

–115

–125


C



32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.

0961

6-16

5

10dB

/DIV



FUNCTIONVALUE


–29.853dBm–61.410dB–61.639dB–48.122dB

6MHz6MHz6MHz6MHz


(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

Y–29.852dBm–61.581dB–61.313dB–48.122dB

ffff

1111

1234

XNΔ1Δ1Δ1

MODEMKR SCLTRC256.15MHz94.05MHz243.20MHz356.25MHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

1

3Δ12Δ1

4Δ1


0961

6-16

6

10dB

/DIV



FUNCTIONVALUE


–29.461dBm–61.621dB–61.831dB

6MHz6MHz6MHz


(Δ)(Δ)

(Δ)(Δ)

(Δ)(Δ)

Y–29.461dbm–61.621dB–61.831dB

fff

111

123

XNΔ1Δ1

MODEMKR SCLTRC550MHz–462.65MHz314.45MHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

2Δ1

1

3Δ1


0961

6-16

7

10dB

/DIV



FUNCTIONVALUE


–32.396dBm–57.463dB–58.079dB–45.705dB

6MHz6MHz6MHz6MHz


(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

(Δ)(Δ)(Δ)

Y–32.396dBm–57.463dB–58.079dB–45.705dB

ffff

1111

1234

XNΔ1Δ1Δ1

MODEMKR SCLTRC799.55MHz–138.70MHz–601.35MHz–187.15MHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

2Δ1

1

4Δ1

3Δ1


0961

6-16

8




dBc–60.27–65.64–64.12–64.24–64.12

dBm–88.50–93.87–92.35–92.47–92.35

LOWERdBc

–10.80–0.336

0.0600.0810.080

dBm–39.03–28.56–28.17–28.15–28.15




10dB

/DIV


–50

–60

–70

–80

–90

–100

–110

–120

–130


0961

6-16

9




dBc–10.88–0.576–0.222–0.423–0.133

dBm–40.39–30.09–29.73–29.93–29.63

LOWERdBc

–58.70–62.34–61.36–61.70–61.84

dBm–88.21–91.85–90.87–91.21–91.36




10dB

/DIV

–61.8dBc –61.7dBc –61.4dBc –62.3dBc –29.5dBm ––0.6dBc –0.2dBc –0.1dBc–0.4dBc

–50

–60

–70

–80

–90

–100

–110

–120

–130


0961

6-17

0




dBc–10.73–0.201

0.3000.2960.230

dBm–42.89–32.35–31.85–31.86–31.92

LOWERdBc

–59.39–61.40–59.86–59.61–60.04

dBm–91.54–93.55–92.01–91.77–92.20




10dB

/DIV

–60.0dBc –59.6dBc –59.9dBc –61.4dBc –32.2dBm ––0.2dBc 0.3dBc 0.2dBc0.3dBc

–50

–60

–70

–80

–90

–100

–110

–120

–130


C



64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.

0961

6-17

1

10dB

/DIV



FUNCTIONVALUE


–33.680dBm–46.450dB–56.577dB

6MHz6MHz6MHz


(Δ)(Δ)

(Δ)(Δ)

(Δ)(Δ)

Y–33.679dBm–46.452dB–56.577dB

fff

111

123

XNΔ1Δ1


–50

–60

–70

–80

–90

–100

–110

–120

–130

2Δ1

3Δ1

1


0961

6-17

2

10dB

/DIV



FUNCTIONVALUE


–34.413dBm–56.033dB

–36.289dBm

6MHz6MHz6MHz


(Δ)(Δ)(Δ)

Y–34.413dBm–56.033dB–36.289dBm

fff

111

123

XNΔ1N

MODEMKR SCLTRC599.10MHz–292.60MHz978.15MHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

1

2Δ1

3


0961

6-17

3

10dB

/DIV



FUNCTIONVALUE


–35.909dBm–53.920dB

–38.646dBm

6MHz6MHz6MHz


(Δ)(Δ)(Δ)

Y–34.909dBm–53.920dB–38.646dBm

fff

111

123

XNΔ1N


–50

–60

–70

–80

–90

–100

–110

–120

–130

1

2Δ1

3

Figure 74. 128-Carrier Low Band Wideband ACLR

0961

6-17

4




dBc–59.56–60.04–58.69–59.04–58.86

dBm–92.93–93.41–92.06–92.40–92.23

LOWERdBc

–11.02–0.3370.0500.0640.099

dBm–44.39–33.74–33.32–33.30–33.27




10dB

/DIV


–50

–60

–70

–80

–90

–100

–110

–120

–130

Figure 75. 64-Carrier Low Band Narrow-Band ACLR

0961

6-17

5




dBc–11.06–0.380–0.004–0.0120.043

dBm–44.91–34.23–33.85–33.86–33.81

LOWERdBc

–58.63–59.29–58.37–57.84–58.04

dBm–92.48–93.14–92.22–91.69–91.89




10dB

/DIV

–58.0dBc –57.8dBc –58.4dBc –59.3dBc –33.8dBm ––0.4dBc 0.0dBc 0.0dBc0.0dBc

–50

–60

–70

–80

–90

–100

–110

–120

–130

Figure 76. 64-Carrier High Band Narrow-Band ACLR

0961

6-21

8




dBc–59.28–54.33–53.36–53.35–53.07

dBm–97.73–92.79–91.82–91.81–91.53

LOWERdBc

–11.07–0.210

0.3530.2530.292

dBm–49.53–38.67–38.10–38.20–38.16




10dB

/DIV


–50

–60

–70

–80

–90

–100

–110

–120

–130

Figure 77. 128-Carrier Narrow-Band ACLR

C



TYPICAL PERFORMANCE CHARACTERISTICS—AD9739A STATIC LINEARITY

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

CODE

ER

RO

R (L

SB

)

20480 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-20

7


–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-21

0


0–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-20

8

Figure 80. Typical INL, 20 mA at −40°C

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-21

1

Figure 81. Typical DNL, 20 mA at −40°C

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-20

9


–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-21

2


C

http://www.analog.com/AD9739A



CODE

ERR

OR

(LSB

)

20480 4096 6144 8192 10,240 12,288 14,336 16,384–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

0961

6-21

3


–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-21

6


0–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-21

4


–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

0

CODE

ERR

OR

(LSB

)

2048 4096 6144 8192 10,240 12,288 14,336 16,384

0961

6-21

7


0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0 250 500 750 1000 1250 1500 1750 2000 2250 2500

TOTAL

DVDD18

CLKVDD

AVDDDVDD33

fDAC (MHz)

POW

ER (W

)

0961

6-21

5

Figure 88. Power Consumption vs. fDAC at 25°C

C



AC (NORMAL MODE) IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.

VBW 10kHz

10dB

/DIV


0961

6-00

7


fOUT (MHz)

SFD

R (d

Bc)

30

35

40

45

50

55

60

65

70

75

80

0 100 200 300 400 500 600 700 800 900 1000 1100 1200

1.6GSPS1.2GSPS

2.4GSPS2.0GSPS

0961

6-00

8

Figure 90. SFDR vs. fOUT over fDAC

NSD

(dB

m/H

z)

–170

–168

–166

–164

–162

–160

–158

–156

–154

–152

–150

1.2GSPS

2.4GSPS

fOUT (MHz)0 100 200 300 400 500 600 700 800 900 1000 1100 1200

0961

6-00

9

Figure 91. Single-Tone NSD vs. fOUT

VBW 10kHz

10dB

/DIV


0961

6-01

0


fOUT (MHz)

IMD

(dB

c)

300 100 200 300 400 500 600 700 800 900 1000

35404550556065707580859095

100

1100 1200

1.2GSPS

1.6GSPS

2.0GSPS

2.4GSPS

0961

6-01

1

Figure 93. IMD vs. fOUT over fDAC

fOUT (MHz)

NSD

(dB

m/H

z)

0 100 200 300 400 500 600 700 800 900 1000 1100 1200–170

–169

–168

–167

–166

–165

–164

–163

–162

–161

–160

2.4GSPS

1.2GSPS

0961

6-01

2

Figure 94. Eight-Tone NSD vs. fOUT

C




–3dBFS

0dBFS

fOUT (MHz)

SFD

R (d

Bc)

30

40

50

60

70

80

90

0 100 200 300 400 500 600 700 800 900 1000

–6dBFS

0961

6-01

3

Figure 95. SFDR vs. fOUT over Digital Full Scale

fOUT (MHz)

SFD

R (d

B)

300 100 200 300 400 500 600 700 800 900 1000

40

50

60

70

80

90

0dBFS–3dBFS

–6dBFS

0961

6-01

4

Figure 96. SFDR for Second Harmonic over fOUT vs. Digital Full Scale

fOUT (MHz)

SFD

R (d

Bc)

30

40

50

60

70

80

90

0 100 200 300 400 500 600 700 800 900 1000

10mA FS

20mA FS

30mA FS

0961

6-01

5

Figure 97. SFDR vs. fOUT over DAC IOUTFS

fOUT (MHz)

IMD

(dB

c)

30

40

50

60

70

80

90

100

110

0 100 200 300 400 500 600 700 800 900 1000

0dBFS

–6dBFS

–3dBFS

0961

6-01

6

Figure 98. IMD vs. fOUT over Digital Full Scale

fOUT (MHz)

SFD

R (d

B)

300 100 200 300 400 500 600 700 800 900 1000

40

50

60

70

80

90

–6dBFS

–3dBFS

0dBFS

0961

6-01

7

Figure 99. SFDR for Third Harmonic over fOUT vs. Digital Full Scale

fOUT (MHz)

IMD

(dB

c)

30

40

50

60

70

80

90

100

110

0 100 200 300 400 500 600 700 800 900 1000

10mA FS

20mA FS

30mA FS

0961

6-01

8

Figure 100. IMD vs. fOUT over DAC IOUTFS

C




fOUT (MHz)

SFD

R (d

Bc)

30

40

50

60

70

80

90

0 100 200 300 400 500 600 700 800 900 1000

+25°C

+85°C–40°C

0961

6-01

9

Figure 101. SFDR vs. fOUT over Temperature

–170

–168

–166

–164

–162

–160

–158

–156

–154

–152

–150

0 200 400 600 800 1000100 300 500 700 900

fOUT (MHz)

NSD

(dB

m/H

z)

+25°C

–40°C

+85°C

0961

6-02

0

Figure 102. Single-Tone NSD vs. fOUT over Temperature

VBW 300kHz

10dB

/DIV

SPAN 53.84MHzSWEEP 174.6ms (601pts)


RMS RESULTSCARRIER POWER–14.54dBm/3.84MHz

FREQOFFSET(MHz)510152025

REFBW

(MHz)3.843.843.843.843.84

(dBc)–79.90–80.60–80.90–80.62–80.76

(dBm)–94.44–95.14–95.45–95.16–95.30

LOWER(dBc)

–79.03–79.36–80.73–80.97–80.95

(dBm)–93.57–94.40–95.27–95.51–95.49

UPPER

0961

6-02

1

Figure 103. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS

fOUT (MHz)

IMD

(dB

c)

30

40

50

60

70

80

90

100

110

0 100 200 300 400 500 600 700 800 900 1000

+25°C–40°C

+85°C

0961

6-02

2

Figure 104. IMD vs. fOUT over Temperature

–170

–168

–166

–164

–162

–160

–158

–156

–154

–152

–150

0 200 400 600 800 1000100 300 500 700 900

fOUT (MHz)

NSD

(dB

m/H

z)

+25°C

–40°C

+85°C

0961

6-02

3

Figure 105. Eight-Tone NSD vs. fOUT over Temperature

–50

–55

–60

–65

–70

–75

–80

–85

–900 200 400 600 800 140012001000

AC

LR (d

Bc)

fOUT (MHz) 0961

6-22

5

FIRST ADJ CH

FIFTH ADJ CH

SECOND ADJ CH


C



AC (MIX-MODE) fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.

VBW 10kHz

10dB

/DIV



0961

6-02

6

Figure 107. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS

101520253035404550556065707580

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

fOUT (MHz)

SFD

R (d

Bc)

0961

6-02

7

Figure 108. SFDR in Mix-Mode vs. fOUT at 2.4 GSPS

VBW 300kHz

10dB

/DIV


CENTER 2.10706MHz#RES VW 30kHz



REFBW

(MHz)3.843.843.843.843.84

(dBc)–68.99–72.09–72.86–74.34–74.77

(dBm)–90.43–93.52–94.30–95.77–96.20

LOWER(dBc)

–63.94–71.07–71.34–72.60–73.26

(dBm)–90.37–92.50–92.77–94.03–94.70

UPPER

0961

6-03

2

Figure 109. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,

fDAC = 2457.6 MSPS (Second Nyquist Zone)

VBW 10kHz

10dB

/DIV

STOP 2.4GHzSTART 20MHz STOP 2.4GHzSWEEP 28.7s (601pts)


0961

6-03

0

Figure 110. Single-Tone Spectrum in Mix-Mode at fOUT = 1.31 GHz,

fDAC = 2.4 GSPS

30

35

40

45

50

55

60

65

70

75

80

85

90

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

fOUT (MHz)

IMD

(dB

c)

0961

6-03

1

Figure 111. IMD in Mix-Mode vs. fOUT at 2.4 GSPS

–90

–85

–80

–75

–70

–65

–60

–55

–50

–45

–40

1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686

SECOND NYQUIST ZONE THIRD NYQUIST ZONE

FIRST ADJ CH

SECOND ADJ CH

FIFTH ADJ CH

fOUT (MHz)

ACL

R(d

Bc)

0961

6-02

5


C




VBW 300kHz

10dB

/DIV


CENTER 2.807GHz#RES BW 30kHz



REFBW

(MHz)3.843.843.843.843.84

(dBc)–64.90–66.27–68.44–70.20–70.85

(dBm)–89.30–90.67–92.84–94.60–95.25

LOWER(dBc)

–63.82–65.70–66.55–68.95–70.45

(dBm)–88.22–90.10–90.95–93.35–94.85

UPPER

0961

6-03

3

Figure 113. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone)

VBW 300kHz

10dB

/DIV

SPAN 63.84MHzSWEEP 207ms (601pts)

CENTER 2.09758GHz#RES BW 30kHz



REFBW

(MHz)3.843.843.843.843.843.84

(dBc)0.22

–66.68–68.01–68.61–68.87–69.21

(dBm)–25.31–92.21–93.53–94.14–94.40–94.74

LOWER(dBc)

0.240.14

–66.82–67.83–67.64–68.50

(dBm)–25.29–25.38–92.35–93.36–93.17–9

Documents

11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters Data Sheet … · 2019. 10. 13. · 11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters Data Sheet AD9737A/AD9739A Rev. Information