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1111111111111111111111111111111111I IIlllIllllllff 111111 I1I11111I 3 1.176 00159 6304
NASA CONTRACTOR REPORT 166323
Final Report - Multiplexed Extrinsic Silicon Detector Array
James F. Yee
Aeroject Electosystems Company
CONTRACT NAS2-10643 March 1982
!yf)S/l (Jf- /~~/323
NASA-CR-166323 19820014409
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110T TO B: 'l'Al~r::. IHC.M 'thiS neot"
L~DRARY COpy /, DR? ? 1982
LANGLEY RES::i\RCH CENTER Llf3R~.R'(, NAS/\
HAMPTON, VIRGINIA
NI\SI\ i 1111111111111 ~~~I~!~!111111111111I1
https://ntrs.nasa.gov/search.jsp?R=19820014409 2018-06-28T20:38:45+00:00Z
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NASA CONTRACTOR REPORT 166323
Final Report - Multiplexed Extrinsic Silicon Detector Array
James F. Yee Aeroject Electrosystems Company Azusa, California .
Prepared for Ames Research Center under Contract NAS2-l0643
NI\SI\ National Aeronautics and Spar.o Administration
Ames Research Center Mollett Field. California 94035
tlgZ-222P3 #-
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Section
1
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
3
3.1
3.2
3.2.1
3.2.2
3.2.3
4
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.4
Report 6184
TABLE OF CONTENTS
INTR.ODUCTION •••••••••••••••••••••••••••••••••••••••••••••
DESIGN ................................................... DE'l'ECTOR AR.RA. Y •••••••••••••••••••••••••••••••••••••••••••
CRYOGENIC ELECTRONICS .................................... Pre ampli fie r •.•••••••.••••.••.••.••••.••••••.•••••.•••.••
Scanning Electronics •••••••••••••••••••••••••••••••••••••
Heater and Temperature Sensor ••••••••••••••••••••••••••••
AMBIENT-TEMPERATURE ELECTRONICS
Signal-Conditioning Amplifier ••••••••••••••••••••••••••••
Electronics Control Unit •••••••••••••••••••••••••••••••••
TESTING AND PERFORMANCE ••••••••••••••••••••••••••••••••••
NOISE IN AMBIENT ELECTRONICS ............................. DETECTOR AR.RA. Y •••••••••••••••••••••••••••••••••••••••••••
Responsivity •••••••••••••••••••••••••••••••••••••••••••••
Noise .•...•••..•....•..........•...•..••.•.....••.....•..
Relative Spectral Response •••••••••••••••••••••••••••••••
ECU DESCRIPTION AND MESDA OPERATION ••••••••••••••••••••••
ELECTRONICS CONTROL UNIT ................................. INITIAL CHECKOUT •••••••••••••••••••••••••••••••••••••••••
On-Focal-Plane Electronics (Cryogenic)
Ambient-Temperature Electronics
OPERATION
...................
General Procedures •••••••••••••••••••••••••••••••••••••••
Precautions ..•..••.•••.•...•.................•........•..
TEMPERATURE-SENSOR CALIBRATION ........ .. ' ................ .
iii
Page
1
2
2
3
3
3
4
4
4
5
7
7
7
7
8
9
10
10
10
10
10
16
16
17
18
Figure No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Report 6184
FIGURES
MESDA AHelD SYSTEM •••.••••••••••••••••••••••••••••••••••.
CROSS SECTION OF SINGLE CID CELL •••••••••••••••••••••••••
ARTWORK FOR FRONT-SURFACE METALlZATION •••••••••••••••••••
ORIGINAL ARTWORK FOR BACK-SURFACE METALlZATION •••••••••••
REVISED ARTOORK FOR BACK-SURFACE METALlZATION ••••••••••••
ARRAY IN MICROELECTRONICS CASE, SN 8101, 8106, AND 8107 ••
ARRAY IN MICROELECTRONICS CASE, SN 8108 .................. ARRAY IN MICROELECTRONICS CASE, SN 8115 ••••••••••••••••••
ON-FOCAL-PLANE SCANNING ELECTRONICS ••••••••••••••••••••••
TIMING DIAGRAM FOR ONE READ FRAME ••••••••••••••••••••••••
SIGNAL-CONDITIONING AMPLIFIER, SCHEMATIC •••••••••••••••••
COMPONENT LAYOUT FOR SIGNAL-CONDITIONING AMPLIFmR •••••••
COMPONENT LAYOUT FOR AMBIENT-TEMPERATURE ELECTRONICS •••••
SCHEMATIC FOR TIMING AND DRIVE CIRCUIT BOARD 1 ........... SCHEMATIC FOR TIMING AND DRIVE CIRCUIT BOARD 2 •••••••••••
TYPICAL TIMING DIAGRAM FOR MESDA S/H CIRCUIT •••••••••••••
S/H CIRCUIT, SCHEMATIC •••••••••••••••••••••••••••••••••••
COMPONENT LAYOUT FOR S/H BOARD •••••••••••••••••••••••••••
SIGNAL AND NOISE SPECTRA FOR FIRST AHCID-ARRAY/
SCAlE CU SET ••••••••••••••••••••••••••••••••••••••••••••
NOISE SPECTRA FOR AHCID SN 8101 ••••••••••••••••••••••••••
RESPONSE OF AMC ID SN 8101 •••••••••••••••• 0 ••••••••••••••••
RESPONSE OF AMCID SN 8106 TO DIFFERENT LED CURRENTS ••••••
RESPONSE OF AMCID SN 8107 AT DIFFERENT SAMPLING RATES
RESPONSE OF AMCID SN 8108 AT DIFFERENT SAMPLING RATES ••••
RESPONSE OF AMCID SN 8115 ................................ TYPICAL SPECTRAL RESPONSE FOR Si:Bi DETECTOR .............
iv
Page
19
20
21
21
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
\#
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Table No.
1
2
3
4
5
6
Report 6184
TABLES
SIGNAL AND NOISE FOR FIRST AMCID-ARRAY/SCA/ECU SET ••••••••
AVERAGE RESPONSIVITY AND OPERABILITY OF MESDA AMCID
PIXELS ••••••••••••••••••••••••••••••••••••••••••••••••••
FRONT PANEL OF E ctJ ••••••••••••••••••••••••••••••••••••••••
REAR pANEL OF ECU •••••••••••••••••••••••••••••••••••••••••
E CtJ IN"l'ERIOR ••••••••••••••••••••••••••••••••••••••••••••••
CALIBRATION OF TEMPERATURE SENSORS FOR MESDA !MelDs •••••••
v
Page
8
9
11
13
13
18
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Report 6184
Section 1
INTRODUCTION
This program was undertaken to design, develop, and test multi
plexed extrinsic silicon detector arrays (MESDAs) with their associated cryo
genic and ambient-temperature electronics for delivery to Ames Research Center
of the National Aeronautics and Space Administration and to Kitt Peak National
Observatory for evaluation in astronomical applications.
Each array consists of two parallel rows of accumulation-mode
charge-injection devices (AMCIDs) configured in a single bismuth-doped sili
con chip. The cryogenic electronics consist of (a) timing and mUltiplexing
circuitry for use in array addressing, and (b) impedance-matching circuitry
for use in preamplifying the signals detected by each detector element. The
ambient-temperature electronics encompass the components used to drive the
timing circuitry, to amplify and demultiplex the signals, and to control the
-system.
Five arrays with their cryogenic electronics, and three ambient
temperature electronics control units, were delivered under this program.
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Report 6184
Section 2
DESIGN
The MESDA system, shown diagramatically in Figure 1*, is composed
of the detector array, some focal-plane cryogenic electronics, and ambient
temperature electronics for timing and drive use and for processing the sig
nals of both linear arrays.
2.1 DETECTOR ARRAY
Each array consists of two parallel rows of AMeIDs fabricated
in a Si:Bi wafer. For each row, a transparent electrode forms a common read-
out-bus line on the front (incident) surface. Sixty-four gates over a native
oxide thickness of about 0.2 micrometer form the storage and injection gates
on the back of the wafer. Figure 2 presents a cross-sectional view at one
of the gates.
During accumulation, a positive bias is applied to the gate to
store the photogenerated charge carriers (electrons). During readout, the
gates are biased negatively to inject the electrons back into the substrate
to the readout-bus line. The bus line is connected to the gate of a p-chan
nel enhancement-mode cryogenic MOSFET operated in the source-follower mode.
The stored charge is seen as a voltage change on the source of the MOSFET
after readout.
The artwork for the front-surface metalization is shown in Fig
ure 3. It includes a mask, electrically isolated from the readout-bus line,
that defines the pixel area in one dimension. This mask, called the "top
guard", is grounded to prevent crosstalk between the two rows. The metaliza
tion between the two rows is 0.25 mm wide.
*AII figures are presented at the end of the report text.
2
Report 61B4
The artwork for the back-surface metalization incorporates gates
and a guard electrode, called the "bottom guard", to define the pixel area
in the orthogonal dimension. Each gate is about O.lB mm square. The origi
nal artwork (Figure 4) was revised because charge accumulated under the gate
of one array could spill over to the corresponding gate of the other array,
causing crosstalk. This artwork was used on only one of the delivered arrays
[designated as Serial No. (SN) BI01J. The other four delivered arrays, made
with the revised artwork (Figure 5), have guard electrodes that completely
enclose each gate electrode, thereby preventing crosstalk between the two
rows.
The front side of each array is indiu~soldered to the inside
surface of a 32-~square 24-pin nickel-plated Kovar butterfly case as shown
in Figures 6, 7, and B. The case is slotted to provide access to the front
side of the chip. Each case has three holes for feedthroughs used to connect
the two readout-bus lines to the gates of the two cryogenic MOSFETs and to
connect the top guard to one of the feedthrough pins of the case. The Kitt
Peak cases (Figures 7 and B) have an additional hole for spectral-analysis
purposes.
2.2 CRYOGENIC ELECTRONICS
2.2.1 Preamplifier
Inside each case a cryogenic preamplifier is provided for each
of the two readout rows. Each preamplifier consists of a low-noise p-channel
enhancement-mode MOSFET operated as a source follower with a load resistor
that has a resistance of about 3.2 x 107 ohms at 10 K. The HOSFET gain is
about O.BO. Both preamplifiers are mounted on a sapphire substrate that has
gold stripes for wirebonding purposes. The preamplifiers are wirebonded to
the feed through pins of the Kovar cases with the pins as identified in Fig
ures 6, 7, and B.
2.2.2 'Scanning Electronics
On the inside of each microelectronics case is a board for the
electronics that mUltiplexes the injection (read) pulses to the 64 pairs o~
3
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Report 6184
gates. As shown in Figure 9, the board consists of a 4-bit up/down-counter
chip (the MM54C193) and four 4-line to 16-line decoders (MM54C154) that are
powered by external store (positive) and read (negative) voltages. All are
complementary HOS (CMOS) chips, which require minimal power for operation.
External clock pulses load the bits to the counter in the up direction while
an external reset pulse clears the counter. External enable pulses are needed
to trigger the decoders.
A timing diagram for one read frame is shown in Figure 10. The
external clock causes the counter to count in the up direction on all four
decoder chips. There is no output on the decoders, however, until enable
pulses are applied to the enable inputs of each decoder. The enable pulses
are externally clocked sequentially through the four decoder chips--i.e.,
the enable pulses are applied as follows: on the first chip during the first
16 clock pulses, on the second chip during the second 16 clock pulses, etc.
2.2.3 Heater and Temperature Sensor
Also provided in each microelectronics case are a 100-ohm wire
wound resistor that can be used to heat the case, and a 5.6-kilohm carbon-
glass resistor used as a temperature sensor. Calibrations for each tempera
ture sensor are given in Section 4.4. If the heater is employed, then either
the case or the heat sink to which it'is attached must be isolated thermally
from the cold finger of the Dewar vessel. Stainless steel screws and washers
can provide the required thermal resistance.
2.3 . AMBIENT-TEMPERATURE ELECTRONICS
The ambient electronics consist of two entities--a signal-condi
tioning amplifier (SCA) and an electronics control unit (ECU).
2.3.1 Signal-Conditioning Amplifier
This equipment was designed around the 5534 operational amplifier.
It is shown schematically in Figure 11, and a component layout is presented
in Figure 12. Two amplifiers, one for each channel, were constructed in a
cast-aluminum case to permit placement at close proximity to the test Dewar
4
Report 6184
containing the MESDA array. Each SCA has a gain of 200 from 700 Hz to 50
kHz. Included in the aluminum case are the source supplies for the two cryo
genic MOSFETs.
2.3.2 Electronics Control Unit
The ECU contains the bulk of the ambient-temperature electronics.
It provides the timing and drive functions for the scanner, the sample-and-
hold circuitry used in measuring the AMeID output, and the controls for the
f~cal plane electronics. The major components are identified in Figure 13,
and Section 4 describes the operation of the unit in detail.
2.3.2.1 Tianng and Drive
The timing and drive circuitry is on Boards 1, 2, and 3. (Fig
ures 14 and 15 present schematics for Boards 1 and 2.) A pulse generator
provides the clock input for the 4040 counter (ICl). By selecting N = 0 to
7, the 4051 multiplexer (IC4) divides the clock-pulse frequency by 2N. The
resultant clock is fed into the 74C193 4-bit counter (IC7) and is then sent
via the 4035 shift register (ICI4), the 4011 quad NAND gates (IC16), and the
two DG303 analog switches to generate enable pulses for the cryogenic scanner.
The output of IC7 is also fed into the 74C154 4-bit to 16-bit
decoder (IC8), which is always enabled. The outputs of this decoder are sent
to the 4067 16-channel multiplexer (IC6). By choosing 1 of 16 positions on
a selector switch, the digital-synchronizing pulse is selected on that pixel.
The output of IC4 is also sent to two more 4040 clocks (IC2 and IC3), Whose
outputs are routed to the inputs of another 4067 multiplexer (ICS). By se
lecting M = 0 to 15, a delay time is introduced before the 74LS76 dual J-K
flip-flop (IClI) is loaded. This delay time is (2M-I) times the time for
one readout frame. The integration time is thus the sum of the read and de
lay times--i.e., [2N + 2N(2M-l)] times clock time = 2M 2N times clock time.
The 4051 multiplexer (IC17) is used to select Which of the four
groups the SYNC SELECT is synchronized to.
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Report 6184
One 75451 dual AND driver (IC23) is used to provide digital syn
chronization and another (IC24) is used to provide dc-restore and sample-and
hold (StH) pulses for the StH circuitry. Further details are provided in
paragraph 2.3.2.2, below.
A potentiometer on Board 3 is connected to IC19 to vary the width
of the read-enable pulse. Another potentiometer on Board 3 is connected to
IC22 to vary the delay in the StH pulse.
A 7400 quad NAND gate (IC13) is used as an OR gate to allow the
StH circuit to function on all the pixels (~tH ALL) or on just one pixel (StH
SELECT).
2.3.2.2 Sample and Bold
Figure 16 presents a timing diagram for the StH function. The
dc-restore pulse sets a reference level for measurements. The StH pulse can
be delayed to any part of the read-enable pulse. Here it is appropriate to
define ~s as the time interval between the end of the dc-restore pulse and
the end of the SIR pulse, as illustrated in Figure 16.
The StH circuitry is shown schematically in Figure 17, and a com
ponent layout is presented in Figure 18. The dc-restore and S/H pulses from
the timing and drive functions are coupled to the StH circuitry with the HPL
2630 optical isolator (U6). The digital synchronizer is used to produce ana
log synchronization via another HPL 2630 optical isolator (U7). Electrical
isolation of the analog and digital electronics is crucial for maintaining
low noise in the output stages. A pair of HA2425 sample-and-hold operational
amplifiers (U1 and U2) provide the SIR function, While LH0002 current ampli
fiers (U3 and U4) can drive an output of 200 mA with a 50-ohm load.
2.3.2.3 Focal Plane Control
The ECU also contains the controls for two of the focal plane
components--the heater and the bottom-guard voltage. The heater power is
tapped off the -15 V supply as shown in Figure 17. The bottom-guard voltage
is powered from the analog voltage supply on the back panel.
6
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Report 6184
Sec:tion 3
TESTING AND PERFORMANCE
For test and evaluation purposes it is convenient to partition
a MESDA system between the ambient electronics and the cryogenic AMCID arrays.
3.1 NOISE IR AMBIENT ELECTRONICS
After the first AMCID-array/SCA/ECU set was constructed, noise
spectra and signals were measured with amplifier bandwidths of 30, 50, and
80 kHz and with As (as defined in paragraph 2.3.2.2) set to 10, 12, and 14
microseconds, in order to determine the optimum amplifier configuration.
A typical plot is shown in Figure 19. Table 1, below, summarizes the sig
nal, noise, and signal-to-noise ratio (SIN) data. The MOSFET gate capaci
tance is 5.7 pF. On the basis of the results, a compromise 50-kHz bandwidth
was selected for all three amplifiers. It can be seen that operation at' lower
backgrounds may benefit from the use of smaller As values to minimize noise.
Noise spectra of the warm electronics were measured with the SIH
input and the amplifier input shorted. Typical data are shown in Figure 20;
they indicate that the noise contributions of the SIH circuit and the amplifier
are significantly smaller than those of the cryogenic preamplifier (see Fig
ure 19).
3.2 DETECTOR ARRAY
3.2.1 Responsivity
The infrared response of each detector array was checked under
low-background conditions using an indium antimonide light-emitting diode
(LED) source. Whenever possible, response ~as measured as a function of LED
current [i. e., photon (ph) fluxes (~)J, temperature, store vOlt"age (VS), read
voltage (VR) , guard voltage (VG), integration time, As, and sampling frequency
(Fs ). Because no satisfactorily responsive arrays were fabricated until
7
Report 6184
TABLE 1 SIGNAL AND NOISE FOR FIRST AMCID-ARRAY/SCA/ECU SET
Values at Indicated
AmpJifier Bandwidths
Parameter 30 kHz 50 kHz 80 kHz
~s = 10 usec
Signal, V 7.4 x 10-3 9.Q x 10-3 1.0 x 10-2
Noise, V 6.0 x 10-5 7.5 x 10-5 9.0 x 10-5
SIN 122.3· 120 III
~s = 12 usec
Signal, V 7.2 x 10-3 8.8 x 10-3 8.9 x 10-3
Noise, V 6.5 x 10-5 1 x 10-4 1 x 10-4
SIN 111 88 89
~s = 14 J,tsec
Signal, V 7.0 x 10-3 8.0 x 10-3 8.0 x 10-3
Noise, V 8.0 x 10-5 1.0 x 10-4 1.1 x 10-4
SIN 88 80 72.7
Average Noise <e> electrons/sample
~s = 10 193 241 290
~s = 12 209 322 322
~s = 14 257 322 354
several months after the originally scheduled delivery dates, early delivery
of these working arrays became of paramount importance, and only cursory checks
were made on most of the arrays. Figures 21 through 25 present typical data
for the five arrays. Table 2, below, summarizes the average current res pons
ivity (RI' in amperes/watt), and the operability of all pixels (gate pairs).
3.2.2 Noise
Under low-background conditions the limiting noise is that of
the cryogenic preamplifier. Because all output HOSFETs were selected for
their very low noise characteristics, the cryopreamplifier noise is dominated
by the Johnson ,noise of the load resistors. The fact that all the load resis
tors were selected to have nearly identical values caused the limiting noise
8
Report 6184
of all the arrays to be likewise nearly identical. The noise shown in Fig
ure 19 is thus typical of all the MESDA arrays.
TABLE 2 AVERAGE RESPONSIVITY AND OPERABILITY OF MESDA AHCIn PIXELS
AMCID Average ,
SN Array SN RI (A/W) Operability of Pixels i
8101 225-9.6-7 1.0 Gate pairs 25, 26, and 60 inoperative
8106 225-7.7-2 1.2 All gate pairs operative I
8107 299-6.7-4 0.8 Gate pairs 1, 22, 26, 41, 54, 56, 60, and 63
inope ra t i ve
810B 225-7.7-4 0.4 All gate pairs operative
8115 225-8.0-4 0.9 Gate pairs 24 a.n!i_~4_!noperative I
3.2.3 Relative Spectral Response
The relative spectral responses of the MESDA arrays were not di
rectly measured. A typical relative spectral response for Si:Bi detector
material is shown in Figure 26.
9
Report 6184
Section 4
ECD DESCRIPTION AND MESDA OPERATION
4.1 ELECTRONICS CONTROL UNIT
The ECU contains the electronics for the timing-and-drive (Tin)
circuits, MOSFET preamplifiers, heater, and SIH circuits. It can be rack
mounted and requires power from two dual supplies (~15 volts, 500 mAl. A
pulse generator is also required for the TID circuits. The ECU features ate
identified in Tables 3, 4, and 5, following.
4.2 IBITIAL CHECKOUT
4.2.1 On-Focal-P1ane Electronics (Cryogenic)
The scanner cannot be checked at room temperature because the
detector is grounded to the can, which prevents the observation of read pulses
through the preamplifier.
The preamplifiers can be checked by providing the source voltage
to them and measuring that voltage. In proper operation the source voltage
drops to about 4.5 V.
4.2~2 Ambient-Te!p!rature Electronics
The array is not required to be at cryogenic temperatures in order
to check out the Tin and SIH circuitry. The procedural steps are as outlined
below.
4.2.2.1 Front Panel of ECD
a. Power Check: With none of the BNC connectors connected to
the control panel, set the two external power supplies to +15 V and switch
the power-supply meter function to read currents. Now connect the digital
power suppplies to the appropriate double GR connectors. The current draw
on the +15 V supply should be about 260 mA; for the -15 V supply it should
10
Report 6184
TABLE 3 FRONT PANEL OF ECU
Label Purpose/Function/Description
CLOCK IN
READ CLOCK
RESET
EN 1 (or EN 2 or EN 3
or EN 4)
STORE
READ
OUTPUT SYNC
SAMPLE AND HOLD INPUT 1
(or 2)
SAMPLE AND HOLD OUTPUT 1
(or 2)
TM
SYNC
2N
BNC Connectors
Brings in ti~ng pulses from an external pulse
generator (2 microseconds to 50% duty cycle).
Sends timing pulses into the cryogenic counter.
Sends reset pulses to the cryogenic counter that
are synchronized with the first pixel.
Sends enable pulses to the decoder chip for the
1st (or 2nd or 3rd or 4th) group of 16 pixels.
Provides store voltage for the counter and
decoder chips.
Provides read voltage for the counter and decoder
chips.
Brings out a pulse synchronized with the digital
electronics at the pixel chosen by the SYNC
SELECT gwitch.
Sends the output of Amplifier 1 (or 2) into the
sample-and-hold circuit.
Extracts the output of Sample and Hold Circuit 1
(or 2) for analysis.
Takes the output of the temperature monitor to
the digital volt-ohmmeter.
Is synchronized with the digital electronics
through an optical· isolator.
Switches
An a-position thumbwheel switch used to set the
interval between read pulses of successive
pixels. This interval is 2N times the base
time set by the master clock (external pulse
generator).
(continued)
11
Report 6184
TABLE 3 FRONT PANEL OF ECU (CONT.)
Label Pur~ose/Function/Description
2M
P (or S)
EN 1 (or EN 2, 3, or 4)
RESET
SIH SELECT (or"S/H ALL)
SYNC SELECT
HEATER OFF
HEATER
Switches (cont.)
A l6-position thumbwheel switch used to set the
interval between the last read pulse of a read
out and the first read pulse of the next read
out. This interval is (2M-I) times the base
time. Therefore, the total integration time
is 2N x (2M-I) x base time.
Used to select parallel-mode (or serial-mode)
readout.
Sends an enable pulse to the 1st (or 2nd, 3rd, or
4th) group of 16 pixels when reading out in the
parallel mode. In the serial mode, these are
overridden so that all groups are enabled se
quentially.
Used to reset the counter to the beginning when
an interruption is desired in a long integra
tion-time interval.
Switches on the sample-and-hold circuitry on a
selected pixel (or on all pixels). In the SE
LECT mode, the pixel is the one indicated by
the SYNC SELECT switch.
A dual thumbwheel switch (one 4-position and
another l6-position) used to select the pixel
to which" a synchronization pulse is synchro
nized. The second number displayed indicates
the pixel group (1 through 4) and the first in
dicates a pixel (1 through 16) in that group.
Turns on or off (up or down) the power to the re
sistance heater in the Kovar can.
Potentiometer
Used to adjust the power supplied to the heater
to regulate the temperature of the Kovar can.
12
Report 6184
TABLE 4 REAR PANEL OF ECU
Label , Purpose/Function/Description BNC Connectors
HT Supplies power to the heater. TM Connects the temperature monitor to the control
panel. GD Supplies bias (+15 V to -15 V) to any guard. DC Rest. A test point used to bring out the dc-restore
pulse. S/H A test point used to bring out the sample-and-
hold pulse. Double General Radio (GR) Connectors
+15A (-15A) Used to connect a +15V(-15V) 100-200 mA supply for the analog circuitry.
+15D (-15D) Used to connect a +15V(-15V) 100-200 mA supply for the digital electronics.
Unlabeled Winchester Used to connect the control box to the SCA. Connector
Potentiometer GD ADJ I Adjusts the voltage supplied at the guard.
TABLE 5 ECU INTERIOR*
Label I Purpose/Function/Description BNC Connector
S/H Used for looking at the sample-and-hold input I
after it has been dc-restored. I
Switch I
I-ADJ/ONE (2-ADJ/ONE) In the ADJ position, switches a gain potentiom- !
eter into the sample-and-hold circuitry for Channell (or 2). The gain is adjustable from 1.5 to 2.0 times. In the ONE position, the gain is unity.
Potent10meters READ PW Used in adjusting the read-pulse width. SIH DELAY Adjusts the delay of the sample-and-hold pulse. 1 (2) Adjusts the sample-and-hold gain when in the ADJ
mode. *See Figure 13.
13
'.
Report 6184
be about 40 mAe Next connect the analog power supply. With the preamplifiers
in operation, the current draw should be about 120 and 25 mA for the +15 and
-15 V supplies, respectively.
b. STORE and READ Check: Connect the STORE output to a digital
voltmeter (DVM) and adjust to +2.00 Vdc. Connect the READ output to the DVM
and adjust to -2.00 Vdc.
c. READ CLOCK Check: Now connect an extemal clock (~S V square
wave pulse at 64 kHz) to CLOCK IN. Connect the READ CLOCK output to an oscillo
scope synchronized with the extemal clock. With N = 0 and M = 0, which gives
the fastest integration time, the output should be 1- to I.S-ndcrosecond pulses
of +2.00-Vdc height at IS.6-microsecond intervals.
d. RESET Check: Next connect the RESET output to the oscillo
scope and synchronize intemally. Because the reset pulse should come just
before the first pulse, this output should be +2.00 Vdc, be 1 to 15 ndcro
seconds wide, and occur at I-millisecond intervals.
e. OUTPUT SYNC Check: Next set SYNC SELECT to 1-1 and synchro
nize with the reset pulse. Look at the output of the OUTPUT SYNC (digital
synchronization). Verify that this is a positive pulse going from ground
to +2.0 Vdc, is 1 to 1.5 microseconds wide, and occurs at I-millisecond inter
vals.
f. S~C Check: Next verify that the (analog) SYNC is a negative
pulse going from. +5.0 Vdc to ground, is 1 to 1.5 microseconds wide, and occurs
at I-millisecond intervals.
g. EN Check: Next synchronize the oscilloscope with the OUTPUT
SYNC and look at the enable pulses. Looking at EN 1 with the read-pulse-width
(READ PW) control fully counterclockwise, the output should occur at 15.6-
microsecond intervals, with the group of 16 pulses repeating at I-millisecond
intervals. The same should be true for EN 2, EN 3, and EN 4.
14
Report 6184
h. SYNC SELECT Check: Keeping the output of EN 4 connected
to the oscilloscope and synchronized with the OUTPUT SYNC, change the SYNC
SELECT setting to 16-4 (16th pixel of 4th group). A single pulse should be
seen. Change the SYNC SELECT to 15-4; two pulses should be displayed. Con
tinue reducing the first number of SYNC SELECT by increments of unity and
observe that one pulse is added each time until 1-4 is selected. This pro
cedure should display all 16 pulses of the fourth group.
i. 2N and 2M Control Check: With Nand M set at 0-0, change
SYNC SELECT to 1-1. Connect the EN 1 and RESET outputs to the oscilloscope
to display alternately. Synchronize to OUTPUT SYNC. The time between the
reset pulse and the first read pulse should be about 2 microseconds. Adjust
the sweep of the oscilloscope to display two complete frames. Now change
N to 1; the read time should double and (because the delay is unchanged) the
total time for the entire frame will double. Consequently, only one complete
frame will be seen in the time that two frames were seen before. Now change
Nand M to 0-1. The read time should be the same as for 0-0, but the delay
time will be equal to the total read time (2M - 1 = 1). The first train of
read pulses will thus occur in the same time interval as When N,M = 0-0, but
there will be a delay interval to replace the second train of N,M = 0-0.
j. DC-Restored StH Input Check: Connect the EN 1 output to
StH inputs 1 and 2. With the oscilloscope synchronized to the analog SYNC,
monitor the StH BNC connectors inside the control panel. The read pulses
should be 0 to -4 V.
k. StH Slew Rate Check: With the StH switch on the front panel
in the StH ALL position, increase the read-pulse width to 6 microseconds.
Adjust the StH pulse to sample Where the read pulse reaches its maximum neg
ative voltage. Now, looking at the S/H outputs, the output should go from
o to -4 V within about 1 microsecond. The slew rate is about 5 to 8 V/micro
second. The output-voltage level should also return to zero after the previ
ous read pulse.
15
Report 6184
4.2.2.2 Rear and Interior of ECU
The outputs in these locations can also be checked without the
array and scanning electronics!
a. aT Check: Connect to a DVM. With the HEATER switch on the
front panel in the up position, a potential of -15 V should be measured.
b. GO Check: Connect to a DVM. The voltage should be adjust
able from -15 to +15 V by turning the guard (GD) control to its two extremes.
c. DC Rest. Check: Compare the dc-restore pulse with the read
pulse, using an oscilloscope. The pulse width should be 1.0 to 1.5 micro
seconds, with a height of about 2.0 V. The dc-restore pulse should be set
about 100 nanoseconds before each read pulse.
d. SIH Check: Compare the S/H pulse with the read pulse. The
pulse width should be 2.0 to 2.5 microseconds, with a height of about 2.0
V. The S/H pulse can be set at 2 to 30 ~croseconds from the read pulse or
at the start of the next read pulse, whichever is a shorter period.
4.3 OPERATION
4.3.1 General Procedures
After the initial checkout has shown that the ECU is operating
properly, the following must be adjusted to the proper operating conditions:
a.
b.
c.
The
The
The
frequency of the pulse generator
store voltage (STORE») Do not exceed
read voltage (READ) differential!
a 15-V
d. The read-pulse width (READ PW) R:2 microseconds.
The following items are then connected to a cooled Dewar vessel
containing the array: RESET; EN 1, EN 2, EN 3, EN 4; STORE; READ; and (on
the back panel) HT and TH.
16
Report 6184
The timing pulses are monitored by means of one of the enable
inputs. Here the digital OUTPUT SYNC should be used.
The preamplifiers are connected to the SCA. The common drain
and the two loads are grounded. The power cable from the back of the ECU
is connected to the SCA. The two sources are connected to the inputs (IN)
of the SCA. The source voltage can be monitored here; it should be about
4.5 V. The outputs (OUT) of the SeA are connected to an oscilloscope in
order to monitor the read pulses of the MESDA. The analog SYNC should be
used to synchronize the oscilloscope.
Presuming that the operation is still proper, the outputs of the
SCA are connected to the S/H inputs. The SIH BNC connectors on the sample
and-hold board are connected to the oscilloscope so that the dc-restored sam
ple-and-hold inputs may be monitored. The SIH delay is adjusted with the
S/H DELAY potentiometer to the desired amount. The S/H outputs are then con
nected to the oscilloscope or to other data-collecting equipment for measure-
ments.
At this point the sampling rate may be adjusted. The temperature
of the array should be monitored, because higher sampling rates result in
higher heat loads.
4.3.2 Precautions
It is emphasized that the differential values of the store and
read voltages must not exceed 15 V or the scanner may latch up.
The READ CLOCK must always be connected last and be disconnected
first, to prevent possible CMOS-chip destruction.
To maintain separate grounds for the analog and digital electron
ics, the OUTPUT SYNC should be used When digital electronics are monitored
and SYNC (near the HEATER OFF switch) should be used When analog electronics
are monitored.
17
...
Report 6184
4.4 TEMPERATURE-SENSOR CALIBBATION
The temperature sensors are carbon-glass resistors with nominal
room-temperature resistances of 5.6 kilohms. Each was calibrated at cryogenic
temperatures. The results are presented in Table 6.
TABLE 6 CALIBRATION OF TEMPERATURE SENSORS FOR MESDA AMCIDs
Part or
Temp (K) Resistance (kilohms) for Indicated Serial Nos.
Array SN 225-9.6-7 225-7.7-2 299-6.7-4 225-7.7-4 225-8.0-4
AMCID SN 8101 8106 8107 8108 8115
Temp Sensor SN 188 190 189 197 201
7 121.2 118.0 120.1 122.6 118.5
8 92.1 89.7 91.5 93.2 90.1
9 73.7 11.8 73.3 74.6 72.1
10 61.2 59.7 61.0 62.0 59.9
11 52.3 51.0 52.2 52.9 51.2
12 45.6 44.5 45.6 46.2 44.7
13 40.5 39.6 40.5 41.1 39.8
14 36.5 35.7 36.6 37.0 35.8
15 33.3 32.5 33.4 33.8 32.7
16 30.6 29.9 30.7 31.1 30.1
17 28.4 27.8 28.5 28.9 27.9
18 26.6 26.0 26.7 27.0 26.1
19 25.0 24.4 25.1 25.4 24.5
20 23.6 23.1 _ .. ___ ..t3.~ 24.0 23.2
18
S
DC RESTORE
MIPLE AND HOLD
I-- READ CLOCK -
MASTER
CLOCK --TIMING
AND
DRIVE
+15 Com -15
DIGITAL POWER SUPPLY
EN 1
EN 2
EN 3
EN 4
RESET
VR Vs
SOURCE 1
-FOCAL
PLANE
- SOURCE 2
-
FIGURE 1. MESDA AMCm SYSTEM
SIGNAL
PROCESSING
CHANNEL
1
SIGNAL
PROCESSING
CHANNEL
2
+15 Com -15
ANALOG POWER SUPPLY
ROW 1 OUTPUT
ROW 2 OUTPUT
~
...
TOP GUARD
'-
i~
I
-125 JLm
-175 I-Lm
Si02
Report 6184
TOP GUARD
-J ... ,
-350 ILm
.J
BOTT~-I----~~--~-- ---~~--l GATE I [BOTTOM
GUARD MET~LIZATION GUARD
FIGURE 2. CROSS SECTION OF SINGLE CID CELL
20
to.) .....
~~: ---------=:1:1 FIGURE 3. ARTWORK FOR FRONT-SURFACE METALIZATION
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
FIGURE 4. ORIGINAL ARTWORK FOR BACK-SURFACE METALIZATION
• • • • • •
FIGURE 5. REVISED ARTWORK FOR BACK-SURFACE METALIZATION
--.
LOAD 1 c=:4
0 0 ~ TEMP MONITOR
~ SOURCE 1 d ~ TEMP MONITOR
COMMON DRAIN ENABLE 4
SOURCE 2 : : ENABLE 3
~ LOAD 2 ENABLE 2 : : I
, . TOP GUARD c=:I ~ I i
f==' ENABLE 1 ; I ~
\' ,j
j' I: . 'I N BOTTOM GUARD ~ i: ' t::==::I STORE N ! ,
CASE -=I
\' ; I
r ! , , I===a READ
HEATER ===I I ;f
~ ~ t=====t CLOCK
~ '=== RESET HEATER ===I
CASE -==I F CASE
CASE s:::::t 0 0 I===a CASE ~ III
'tJ 0 11 rt
'" .... FIGURE 6. "ARRAY IN MICROELECTRONICS CASE, SN 8101, 8106, AND 8107
Q) .po
---------_. CASE
0 0 CASE
CASE r---:
i' f ENABLE 4
I
HEATER ENABLE 3
HEATER ENABLE 2
BOTTOM GUARD ... ! ENABLE 1
TOP GUARD STORE
N SOURCE 2 ; READ w
.LOAD 1 CLOCK
LOAD 2 RESET
COMMON DRAIN TEMP MONITOR
SOURCE 1 TEMP MONITOR
CASE 0 0 ~ CASE 11)
'tJ 0 --_.- ---- tot rt
0\ ..... 00
FIGURE 7. ARRAY IN MICROELECTRONICS CASE, SN 8108 .to-
r
CASE c:::==::t
0 0 1===== CASE
CASE~ r rr J===I ENABLE 4
HEATER c::::=t I : I 1===== ENABLE 3 I j !
HEATER~ ~ ENABLE 2 : .
I
BOTTOM GUARD ~ • .! r- ENABLE 1 · .
TOP GUARD d t===' STORE
N oil-
SOURCE 2 · . READ
LOAD 2 CLOCK
LOAD 1 RESET
COMMON DRAIN c:=::I \.-J / ~ TEMP MONITOR
SOURCE 1 ~
~ 1===== TEMP MONITOR
0 0 ~ CASE
~ III
CASE ---. '0 0 '1
" 0\
FIGURE 8. ARRAY IN MICROELECTRONICS CASE, SN 8115 .... 00 ~
Pixels Pixels Pixels Pixels
49-64 33-48 17-32 1-16 -
C154 C154 C154 C154 C193
A A A A C .n ~A u
Read Clock
Bi- B- BI-- B ~BQ QR <> S D C S D C S D C S D C C D
Reset
• 0
4 0 () c) () 0 Enable 4 Enable 3 Enable 2 Enable 1
FIGURE 9. ON-FOCAL-PLANE SCANNING ELECTRONICS
,
~~KFlG1~ 48 rJ:1M ENABLE SlUFf U u u Ir
...., 0\
ENABLE 1
ENABLE 2
ENABLE 3
ENABLE 4
LOAD
RESET
-----------------------~ ____ ... _._._. __ ~. .. __ , ___ ...... _._~_.____________ L
FIGURE 10. TIMING DIAGRAM FOR ONE READ FRAME
~ 'tI o t1 rt
0\ .-00 ~
IN RI PWR +0 IS ~-G.I SoUp
IN ISICQ' I 2.0 )+ 15 " ~" T tnf • -IS ,
2.0
COM 1 I etn;' ) . CHS
o rh
,1 ~20?2SK tnf tnf
+15
.50 P~5
CH
6 R.S '\/'VI
IS ZOK \-10
,SO Pf
C.6 ".2-5 pf
CH
+15 2.OK
-15
Report 6184
OUT
2
OUT
FIGURE 11. SIGNAL-CONDITIONING AMPLIFIER, SCHEMATIC
27
1 os "
\Q 11. 1'; "lb .;IO.ll. ~'i. ~r. 303:1 "3~Ua 3'1 .. 11 · • • • • . ... • • ~. . . . • • •
(~"' IT~II~ ~
~~ • ~ I · • . . .
gl);IILi : rr ~ )~
Co\ IS •
N I, • 00
. 6 A,
jO • ;)\ • _./1 _ , ...., ,,. , " , 12
~
j~1 • .;t •
I -~~~~----::::::==::::::ar~::::::=-... Q-" : .~J'==;:~~.;;;;;;;;:-;~~!======~~I~:::TIC ?l~"~
~
FIGURE 12. COMPONENT LAYOUT FOR SIGNAL-CONDITIONING AMPLIFIER
j:Q /I) ." o 11
" 0\ .... 00 .po
IOAID 1 IOAID 2 IOA.'ID 3 IOAID .. IOA1UI 5 IOAID 0
~--~--------~r~----~----~~~~--------~----~------~----~~-------~------- ~ I' N I II ::: J:?i ~ ~ ,!-.<I .... ~ ,Q, -g-- (:0 +g -:;- CO'"
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Tc rca ~ tr It" \! 15 17 22 21 20 27
Ii i1il ~. rt !,l 0 [! ':'r -Q!±}- -{E]-
IC
::re4tl ~ .... "c': r"DIIIP 13 COIIP
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o o
SIll GoA/AI
II OJ
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B El
o
0-- --0 (;;- -Po ~ ________________ ~I~ ______________ ~~~ ______________ ~~ ______________ -4~ _________________ ~L-____ -- ----____ ~
CONP,
R I,Z C. I J 3 C. lJfo
VAW£ I K
D.IM.~
IDOA-II
:r:c.... ()c"/~ P .. "I I ~o"o II
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~ I/O (.1 2.' " '10 ,. T z.f 7 7i1C'U .3
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rc~
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[;~ ."o! r 7 i'/.S l' 11il$OO
4IO'~ ~oS"'o
(/0 'I 'Ion 1"1UIlJ 15'¥~1
DC; .lOJ
FIGURE 13. COMPONENT LAYOUT FOR AMBIENT-TEMPERATURE ELECTRONICS
:r.<!.* VI
VI. u, U¥ uS" lJ' c.J7
D.""t:.Hlf :J"'~S' 111. J,."J,S i.HODO'2.
LlloOO2-DG-.1oa HPL.2U, HPL 1'30
w o
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211
•
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3 % ,. rJ,
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r---f! 8
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lit vv
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lfo '/0 CD
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~ .. / 1,0 ~RC' 0, Q~ I~ 9 0
Q? I", I I
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3 ~ ® Q, IliI S " K>--rc •
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~
~ _"-A-
,/ -AA"--
JS III -5
£/0-1 Cc~l> "
,
SI'""a., S~"",C.T
FIGURE 14. SCHEMATIC FOR TIMING AND DRIVE CIRCUIT BOARD 1
$It! (1)
'tJ o '1 rt
0\ .... co ~
w ....
. S#ll~ ----+--------IRt .. "f(t ••
r-----------1=~~~----O~ •
FIGURE 15. SCHEMATIC FOR TIMING AND DRIVE CIRCUIT BOARD 2
W N
,
PIXEL 3 PIXEL 4 PIXEL 5 . I
READ CLOCK J ,"------in n I DC RESTORE ~ I ~ I n I rL
READ ENABLE ,. ,
I
SAMPLE/HOLD n n n ... _______ _ \+-As...f
FIGURE 16. TYPICAL TIMING DIAGRAM FOR MESDA sIR CIRCUIT
~ 'tJ o 11 rt
Q\ ..... 00 .po
1N?\STZ
~~\.oc;. @ S'(~
~
1_
~~ ! ,,,
HA~~~~ U1
t
....,..----------
~~ ~1 'TP'2. ~Cr "!o~
u~
L -.11\, - \~ J ~~ ~~~ .-:1. ~~ '. =::I a_ ~
w\G-. -= , !I .~~e..
J ~~ HVL. ~'!o "--...... ·t u'
~
\~
Report 6184
sll-\ ~2. O\.\~.'l>UT
~1 L~OOO~ U3
·1 , ' a~SV
s(\-\
~<\ 1~ O\.l\?\S\"-
"G L\\O.~~ 1 U4\
·u_ • .~sv
/ Ii; ,.... -50 "\11 ,,-w:. -1'i.V ~ " ~~ ..e. ell
_ • _ .' ...-'V\IIa ~ . R"J :i::
•
FIGURE 17. SIH CIRCUIT, SCHEMATIC
33
"
o
to :1 0...,4
~ C ~
¢I
to. ~N to
(0 Ct~ ,,2 :te 0
'Be c ;i.i-"'II' c(l 0
•
Ul
•
Ll"
•
us
\ ~
'@ T~1
..... '5 o
•
•
U'3
U4
-IS CZ)
G J.-" III ~.
~a: p elf a
@ 'Tl>~.
o-§]---o
G o 0 ~sv GR\)
FIGURE 18. COMPONENT LAYOUT FOR siR BOARD
34
Report 6184
~I ~~ ~)
oj N~
o 0)
'1 ~~
~" u-.j 0"c!.
0)
') 0:r
"iii 0)
o )
~ 0)
o }tJ cJ:l -'7 Or/'
0)
Report 6184
10-2
,... > ..... 10-3
:;! :z; t:I .... III
co: 0 ,... ~ -CD
S >~ ..... III 10-4 III .... 0 :z;
10-5
PUOIJEHC! (1&)
FIGURE 19. SIGNAL AND NOISE SPECTRA FOR FIRST AMCID-ARRAY/SCA/ECU SET
35
"
..
,..,.
~ -en S
:;:.$.1
'-'
~ CIJ ~ 0 z
Report 6184
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10-2 =:~~:~:~i:~::~~:":_1 :j<:i ~~l· ;1-, :~~~F;~ :~~--~~·~1.:,· <F:~.hT-~1 .::!: :J':'~; __ J~J~:~~~' :+:i~:1
10-3
10-4
~~~'-~l·U·~~~::· ':;<·1:; ;::-j.: .!.::'.' :'~ ".: 1 ~~~ :;~:t;:··I.:::r:::j:; ::-~l. 'J.::: .:;~~~:~ ... ;·:~;~~;~L;~:L~!;;:t:.;::~ cic:i'r:;"!: -.: :i ;.-! .. : . :,:i:: ';'J:H:i':l::!':' i:'J ·t~! :. ,',' '.; :~ .. ::;~.j::'~ :J:o:t~~}::"h.:i.i
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Report 6184
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41
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1. Report No. 2. Government Accession No. 3. Recipient's Citalog No.
NASA CR-166323 4. Title and Subtitle . 5. Repon O.te
Final Report - Multiplexed Extrinsic March 1982 Silicon Detector Array 6. Performing Org.1nization Coda
)I
1. Authorlsl 8. Performing Organization Report No.
James F. Vee 10. Work Unit No.
.. 9. Performing Organization Name and Address
I-SJf9~ . Aerojet E1ectrosystems Company 11. Contract or Grant No:
Azusa, California NAS2-10643
13. Type of Report and Period Covered 12. Sponsoring Agency Name and Address .
Contractor Final Report National Aeronautics and Space Administration 14. Sponsoring Agency Code
Washington, DC 20546 50 " - G/-SI 15. Supplementary Notes
Char1es·M. Winget, Mail Stop 239-7, NASA Ames Research Technical Monitor: Center, Moffett Field, CA 94035 (415) 965-5753 or FTS 448-5753
16. Abstrlct
This report covers work by Aeroject E1ectroSystems Company (AESC) on the development and testing of multiplexed extrinsic silicon detector arrays (MESDAs) for infrared astronomical applications. The work was performed under National Aeronauti cs and ·Space Administration (NASA) Contract NAS2-l0643 for the Ames Research Center and Kitt Peak·Nationa1 Observatory during the period from May 1980 through January 1982.
The AESC design and fabrication efforts for detector arrays and cryogenic electronics were directed by Dr. James F. Vee, and for ambient-temperature electronics by Robert R. Quaintance. Both collaborated in MESDA system testing, and together they acknowledge the contributions of Dr. Christopher M. Parry in many helpful discussions throughout the program.
In addition, dialogues with and the cooperation of Dr. Craig McCreight of NASA-Ames and Dr. Fred Gillette of Kitt Peak are greatly appreciated.
., 17. Key Words (Suggested by Author(s" 18. Oimibution Statement
Detector arrays Unclassified - Unlimited Cryogenic electronics Extrinsic silicon STAR Category - 89
19. Security Oassif. (of this report) 20. Security C:.ssif. (of this page) 21. No. of Pages 22. Price·
Unclassified Unclassified 45
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