12 Dillon Poster

8/10/2019 12 Dillon Poster

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Copyright 2007, Dillon Engineering Inc. All Rights Reserved.

Accelerating Algorithm Implementation

in FPGA/ASIC Using Python


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Modeling

Algorithm Development MATA! replacement

"se Python mod"les #"mPy$ SciPy$ Matplotli%

Algorithm &eri'ication

Floating to Fi(ed point conversions

)"ic*ly e(plore %it +idth and S#, tradeo''s

Fi(ed point precision

'i(ed point data type *eeps trac* o' precision

inear alge%ra

Canned math '"nctions$ FFT$ 'ilters$ ---

.asy integration o' math and control '"nctions

Simple model re"se via mod"les


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ASIC/FPGA ogic !"ild

C"stom tools$ i-e- D.0s ParaCore Architect

1D generation

simple to ma*e a class to generate 1D

.''icient mod"le re"se %y +rapping 1D +ith Python

My1D code logic in Python$ a"togenerate &erilog

or &1D

Po+er'"l scripting lang"age$ 'orget Perl and TC/T2

gen3ise-sh availa%le on D. +e%site$ generates IS. %"ild 'iles

pro4ect %"ild scripts

sim"lation scripts$ regression


4/12


&eri'ication

Use Python unittestmod"le to generate test cases

Generate veri'ication data 'rom Python model

simpli'ies test %ench

increases test coverage %eca"se o' ease o' generating corner

cases and random data 'rom Python

Allo+ higher level tests "sing My1D to control

sim"lation

Data can %e 'eed 'rom Python to 1D code and %ac* %y means

o' CoSim"lation

Simple 1D test%ench$ can %e driver %y Pythongenerated data 'or '"ll system veri'ication

,egression test control


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Par*sMcClellan Filter Design .(ample

MATA! approach

' 5 67 7-8 7-9 7-: 7-;

a 5 67 7 < < 7 7=>

% 5 'irpm?


6/12


Python Matplotli% Plot !andpass


7/12Copyright 2007, Dillon Engineering Inc. All Rights Reserved.

Fi(ed Point Modeling

Use a Python class to create a ne+ data type

.(ample class created %y D. DeFi(edInt?@

Model signed 'i(ed point data

speci'y integer and 'ractional +idth

Use operator overloading to allo+ %asic arithmetic

,epresenting signed 'i(ed point n"m%ers A?a$%@

A represent signed 'i(ed point n"m%er

a integer val"e representing integer +idth

% integer val"e representing 'ractional +idth

.(ample A?E$@



DeFi(edInt?@ .(ample

1o+ addition changes

the representation

a 5 DeFi(edInt?E$@

% 5 DeFi(edInt?E$7@

c 5 a %

print c-rep

A?$@

1o+ addition changes

the val"e

a-val"e 5



Hhy Python

Jpen so"rce o%4ect oriented programming

Int"itive lang"age$ even hard+are engineers can %e

prod"ctive "sing

Single lang"age can handle all programming

re)"irements

scripting

modeling

logic generation

veri'ication

Jpen so"rce mod"les availa%le 'or almost any

'"nction

Concise$ e(plicit 'ormat$ easy to code$ read and

maintain



Jpen So"rce ,eso"rce S"mmary

Python http//+++-python-org

n"mpy http//+++-n"mpy-scipy-org

scipy http//+++-scipy-org

My1D http//myhdl-4andecal"+e-com/

Jctave http//+++-octave-org/

Icar"s http//icar"s-com/eda/verilog

matplotli% http//matplotli%-so"rce'orge-net/

Dillon .ngineering http//+++-dilloneng-com/
http://www.python.org/http://www.numpy.scipy.org/http://www.scipy.org/http://myhdl.jandecaluwe.com/http://www.octave.org/http://icarus.com/eda/veriloghttp://matplotlib.sourceforge.net/http://www.dilloneng.com/http://www.dilloneng.com/http://matplotlib.sourceforge.net/http://icarus.com/eda/veriloghttp://www.octave.org/http://myhdl.jandecaluwe.com/http://www.scipy.org/http://www.numpy.scipy.org/http://www.python.org/



D. IP Availa%le 'or ASIC/FPGAs

Horld0s 'astest and most e''icient FFT architect"res$

'i(ed and 'loating point

F"ll Parallel

D"al Parallel

Parallel !"tter'ly

Ultraong FFT

D FFT

Mi(ed ,adi(

Pipelined

Floating Point Mod"les

A.S .ncryption/Decryption



D. Services Availa%le

DSP/1P.C Algorithm Development

AlgorithmtoFPGA/ASIC

Image and &ideo Processing

Medical IC Development

,T &eri'ication

CPU and SJC Systems

DSP Fi(ed/Floating Point Models

C"stom IP Design and &eri'ication

Documents

12 Dillon Poster