(12) United States Patent Kamin et al.

USO09529953B2

US 9,529,953 B2 Dec. 27, 2016

(10) Patent No.: (45) Date of Patent:

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SUBTHRESHOLD STANDARD CELL LIBRARY

Applicants:Nackieb M. Kamin, Kapolei, HI (US); Gregory Lum, Honolulu, HI (US); Henry Au, Honolulu, HI (US)

Inventors: Nackieb M. Kamin, Kapolei, HI (US); Gregory Lum, Honolulu, HI (US); Henry Au, Honolulu, HI (US)

Assignee: The United States of America, as Represented by the Secretary of the Navy, Washington, DC (US)

Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

Appl. No.: 15/049,762

Filed: Feb. 22, 2016

Prior Publication Data

US 2016/02O3243 A1 Jul. 14, 2016

Related U.S. Application Data Continuation-in-part of application No. 13/564,902, filed on Aug. 2, 2012.

Int. C. G06F 7/50 (2006.01) U.S. C. CPC ........... G06F 17/505 (2013.01); G06F 17/504

(2013.01); G06F 17/5031 (2013.01); G06F 17/5068 (2013.01); G06F 17/5081 (2013.01);

G06F 2217/84 (2013.01) Field of Classification Search None See application file for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

5,266,848 A * 11/1993 Nakagome ....... HO3K 3,356O17 326.62

5,763,907 A * 6/1998 Dallavalle ........... HOL27/02O7 257/2O2

6,634,015 B2 * 10/2003 Lee ....................... GO6F 17,505 438/14

(Continued)

OTHER PUBLICATIONS

T. Gemmeke et al., “Variability Aware Cell Library Optimization for Reliable Sub-Threshold operation.” 2012 IEEE, pp. 58-61.*

(Continued)

Primary Examiner — Leigh Garbowski (74) Attorney, Agent, or Firm — SSC Pacific Patent Office; Arthur K. Samora; Kyle Eppele

(57) ABSTRACT

A subthreshold standard cell library addresses the energy efficiency of electronic systems, thereby significantly reduc ing power consumption. Recent energy performance requirements are causing the next-generation system manu facturers to explore approaches to lower power consump tion. Subthreshold operation has been examined and imple mented in designing ultra-low power standard cell designs that operate beyond the normal modes of operation, with the potential for large energy savings. Operation of CMOS (Complementary Metal Oxide Semiconductor) transistors in the Subthreshold regime, where the Supply Voltage used in operation is orders of magnitude below the normal operating Voltage of typical transistors, has proven to be very benefi cial for energy constrained systems as it enables minimum energy consumption in Application Specific Integrated Cir cuits (ASICs).

4 Claims, 5 Drawing Sheets

Subthreshold Standard Cell fibrary

y S

f f - 2 d 28

Fiysical Library

1 23

Figital fining Jepeattle C. Characteristics

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ask layout

- - 5 52 5.

Syntol Schieftai:

U.S. Patent Dec. 27, 2016 Sheet 3 of 5 US 9,529,953 B2

Oxide (SiO2) S. Sotirce G - gate D - drain

Oxide (SiO2) S. SOLifice G - gate Y D - drain

US 9,529,953 B2 5

TABLE 2

WW, (R) L = L = 0.24 Lim Average power (W)

0.72/0.36 (2) 6.536.192 pW 1.08/0.36 (3) 10.16797 pW 1.44/0.36 (4) 1.237374 pW 1.8/0.36 (5) 7.625445 p.W

2.16/0.36 (6) 7.981612 pW 2.52/0.36 (7) 7.521682 pW 2.88/0.36 (8) 7.817873 pW 3.6/0.36 (10) 2.029605 pW

3.96/0.36 (11) 0.503949 pW 4.32/0.36 (12) 0.571025 pW 4.68/0.36 (13) 0.723670 pW 5.04/0.36 (14) 2.895852 pW 5.4/0.36 (15) 4.079439 pW

From the above, it can be seen that the average power is lowest for inverter 222 when ratio R of 11 is used. Finally, Table 3 is a table of average power consumption for a standard foundry model with varying R (using the same conditions as Table 2).

TABLE 3

W.W., (R) L = L = 0.24 Lim Average power (W)

0.72/0.36 (2) 19.22355 pW 1.08/0.36 (3) 18.84233 pW 1.44/0.36 (4) 12.76747 pW 1.8/0.36 (5) 14.58337 pW

2.16/0.36 (6) 16.58434 pW 2.52/0.36 (7) 17.54507 pW 2.88/0.36 (8) 27.88722 pW 3.6/0.36 (10) 19.86581 pW

3.96/0.36 (11) 20.00879 pW 4.32/0.36 (12) 19.57516 pW 4.68/0.36 (13) 20.70518 pW 5.04/0.36 (14) 26.59364 pW 5.4/0.36 (15) 26.26062 pW

From Table 3, it can be seen that the lowest average power (which for the standard model occurs at R=4) is approxi mately 12.78 pW, which is roughly twenty-five times the average power of 0.5 pW for the inverter 222 building block for logic gate 20 of library 10.

From the above, it can be seen that by maximizing the rise delay, fall delay, propagation delay rise and propagation delay fall to determine the ratio R of nMOS/pMOS channel widths, the systems and methods of the present invention according to several embodiments can be achieved. Refer ring again to FIG. 5, the ratios R for inverter 222 can be 11:1, 10:1 for tristate inverter 224, 11:1 for buffer 226 and 26:1 for NOR gate 228. Similarly, ratio R can be 2:1 for three-input NAND 230, 3:1 for two-input NAND 232, 4:1 for two-input AND 234 and 20:1 for two-input OR. Still further ratio R can be 2:1 for D latch 238 and 4:1 for D flip flop 240. The ratios R for logic gates 222-240 can allow for efficient operation in the subthreshold region. It should also be appreciated that the ratios above were determined for a Taiwan Semiconductor Manufacturing Company, Limited (TSMC) 0.25 um process. Other processes can have differ ent ratios for logic gates 222-240. The data which resulting in the above ratios is included in this Specification as an Appendix.

To demonstrate the above ratios for logic gates 222-240, a 4 bit counter test vehicle was fabricated and the test vehicle was operated using the library 10 of the present invention. Other test runs were also accomplished, using other designs. FIG. 6 depicts the results of the test vehicle runs. From referring to FIG. 6, curve 62, which can be the results of the

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6 counter test using the systems and methods of the prevent invention, can be compared to curves 64 (a design that optimized equal mobility value between nMOS and pMOS transistor in the logic gates 20), curve 66 (results for a standard cell library with standard cells where ratios R were not modified), curve 68 (standard model received from a foundry) and curve 70 (standard transistor operation in the weak inversion region). As shown in FIG. 6, in addition to a reduction in power an improvement in operating frequency that can be realized from the library 10 of FIG. 1 for the same Voltage, when compared to systems of the prior art. As shown by FIG. 6, when the ratios R for logic gates are determined so that the rise and fall delay and propagation delay are substantially equal, a higher operation of operation for the same input Voltage can be achieved. As shown in FIG. 6, the ratios R can be determined by optimizing the mobility values for nMOS and pMOS components in the gate 20, but the frequency response will not be as great. However, in both cases, the frequency range of operation is still better the standard low power and standard mobility designs of the prior art (curves 66-70). The subthreshold standard cell library can further be

applied to any ASIC that can require reduced power con Sumption/improved battery life over outright performance. The library can be used with other fabrication process technologies in design of ASICs. One embodiment is designed on the TSMC 0.25 um process, but it can be applied to other processes, such as Intel(R), IBM(R) and other TSMC feature sizes. For these processes, different ratios R of W/W for logic gates 222-240 can be used, if channel length is kept constant and equal delay between rise and fall and propagation is used as the primary criteria. The subthreshold standard cell library can further be

applied to any ASIC that needs reduced power consumption/ improved battery life over outright performance. The use of the terms 'a' and “an and “the' and similar

references in the context of describing the invention (espe cially in the context of the following claims) is to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by con text. The terms “comprising”, “having”, “including and “containing are to be construed as open-ended terms (i.e., meaning “including, but not limited to.”) unless otherwise noted. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring indi vidually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein.

All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as') provided herein, is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.

APPENDIX

The following tables list the experimental data resulting in the optimized ratios R for the library logic gates 20 for the systems and methods of the present invention.