12.2 Silicon Solar Cells

12.2.1. High Efficiency Crystalline Solar Cellsa. Monocrystalline silicon solar cells on p-type substrates (Ketan Warikoo, Kalaivani

S., Sandeep S. S.):The following processes are being developed using the infrastructure available in the centreof excellence in nanoelectronics (CEN) at IIT Bombay. In the meanwhile PV specific processand characterization equipment are being procured and the learning would be further refinedusing the characterization tools and transferred to the new processing tools.

The solar cells were fabricated on a p-type <100> wafer with a resistivity of 1-5 Ω-cm. Thejunction was formed by means of solid source diffusion process and the deadlayer wasremoved as discussed in the previous quarterly report. A silicon nitride layer with a thicknessof 75nm and a RI of 1.9 was deposited on the wafer. The nitride was patterned, contactwindows opened, and a three layer stack of Ti/Pd/Ag each of thickness 50/50/100 nm wasthermally evaporated onto the wafer. Thermally evaporated Al with an approximate thicknessof 150 nm was used back contact.

Characteristics of the best cell are shown in Fig 12.1. The solar cell exhibited a Voc = 590mV, Jsc = 39.5 mA/cm2, FF = 64 %, and efficiency = 14.9 %. Except for the FF all otherparameters have shown significant improvements from the previous quarter. The contactprocess was not optimized so far. We are presently focussing on contact optimization withdedicated transmission line structures incorporated on the mask set being used for cellfabrication. A new mask was designed for this purpose. This is currently being written usingthe CEN Laser writer facility.

0.0 0.2 0.4 0.60

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J (C

urr

ent D

enst

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m2 )

Voltage

Fig. 12.1: Characteristics of the best cell from the most recent cell fabircation experiment.See the text for details.

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Optimization of SiNx for ARC: (Sandeep S. S., Ketan Warikoo):

We have optimized SiNX for ARC application using a two step ICP-CVD process. The resultsof process optimization are shown in the Figs. 12.2 and 12.3 below. A surface recombinaitonvelocity of 1.9 cm/s, which is comparable to the best reported in the lterature, has beenobtained. These results would be presented at the 38th IEEE Photovoltaic conference to beheld at Austin, USA duing 3-8 June, 2012.

Fig. 12.2: Variation of RI with SiH4 flow rate. Graph shows a threshold SiH4 flow beyond which blistering begins.

Fig. 12.3: Variation of RI and deposition rate with SiH4:N2 flow rate.

12.2.2. 3D Junctions (Student: Som Mondal)

Salient features: The proposed solar cell structure is an emitter wrap-through structure withdiffused bulk channels those transport the carriers separated near top emitter to the rear sidecontacts.

Research publications: Diffused Bulk Channels Instead of Laser Drilled Via-Holes inEmitter Wrap-Through Solar Cell Structure: a TCAD Simulation Study - communicated tothe IEEE Journal of Photovoltaics

The laser assisted diffusion process is being studied using long wavelength laser (1070 nm).There are various parameters those affect the amount of energy deposited in Si with eachpulse per unit area. The parameters are Laser power (PL), pulse repetition rate (fL), pulseon/off ratio (DL) and scan speed (Vs). Longer pulse width (lower fL) and higher DL leadhigher amount of energy deposition. If the energy deposited is high, melting occurs afterabsorbing the radiation and craters form on the surface. However if the laser power density ishigh enough, it melts and ablates the surface which is not acceptable for the application.Apparently it is seen that if the surface gets ablated, lots of particles (in the form of dust) arefound on the sample surface near the processed area. If there is no dust found on the surface,it is expected, that no ablation has occurred. However it's a crude observation and needs moreproof from diffusion results.

While varying all those parameters mentioned above during laser irradiation on bare Si wafer,some particular sets of values have been obtained at which crater formation on surface havebeen observed. Figs. 12.4 and 12.5 are the optical microscope images of the craters formed

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on the surface under different sets of values for these parameters. Interestingly it is observedthat fL and DL are much more influential than PL. Little change in values of the first two createmuch difference in appearance of the surface than the last one. Diffusion studies are beingdone now on p-type Si with P-SOD spin-coated on top of it. Carrier lifetimes of two sampleshave been measured using Sinton Lifetime Tester. Carrier lifetime values obtained before andafter LAD are 0.1 - 0.2 µs and 1 - 2 µs respectively. However no other measurements havebeen done on these samples.

Fig. 12.4: Craters formed on surface. Fig. 12.5: Overlapping craters.

12.2.3. Novel technology for contact formation using temperature sensitive paste (Student:

Sastry)

Photovoltaic solar cell uses solar radiation and converts it into electricity. Even though theconverting efficiencies are reached to 25% for a crystalline silicon solar cell, thecommercially available cells are at 17%. Hence, there is a huge gap between the commercialand laboratory scale production.Patterning (Pre-metallization) of the solar cells at front side is an alternative method to thecommercially available screen printing technique in order to achieve better features of finger-grid at front side (finger width < 100µm). Patterning of half – finished solar cells are done byusing a mechanical structure. Using EDM (Electro Discharge Machines) wires also patterning can be done. This methoduses very thin (30 µm) Tungsten wire to pattern. From previous experiments it is evident thatby using this method the finger width could be as low as 78 µm. The experiments wereperformed for single finger to ensure continuity of etching and uniformity.

Patterning by EDM Wire:For a single finger, it was observed that the minimum finger width using a 30 µm wire couldbe 78 µm. This method could be expanded for complete patterning of a solar cell with size 4x 4 cm2. Before that,

1. To eliminate the manual patterning while experimentation, mechanical design issuggested.

2. Simulation of a finger grid pattern best suited for the 4 x 4 cm2 solar cells. 3. Metallization using Ni/Cu electroless deposition for front contacts.

Design for the patterning of solar cell

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To ensure the continuity and fine patterning, a mechanical device is proposed for patterningof solar cell. It is proposed with acrylic sheets. Wheels with gearing mechanism are made andare kept inside a container with etching paste. Paste is in contact with the wire. Wire is takenout from a small slit such that sufficient amount of paste is on the wire and excess paste willbe removed. This wire is taken with some other wheels with gearing mechanism to the end part where inthe solar cell is contacted to the paste applied wire. Depending upon the number of fingers,the grooves are made on the contacting wheel. Solar cell is governed by up and downmechanism. Once the patterning is done, the cell is removed and wire is passed. Usingcontinuous motion of wire, always sufficient amount of paste is applied on the wire and iscontacted with solar cell. This design is under progress.

1. Simulation of a finger grid pattern best suited for the 4 X 4 cm 2 solar cells:A simulation process of finger grid optimization best suited for the 16 cm2 solar cells is underprogress.

2. Metallization of solar cells using Ni/Cu electroless deposition The metallization is done on the samples which were etched by EDM wire manually. Ni layerheight of 0.2 µm on which 10 µm Cu layer plated is observed with the experimental results.The patterned cells by above described design (co mplete solar cells) could be metalizedfurther.

Fig. 12.6: Design for patterning of solar cell.

12.2.4. Ni-Cu Front side Metallization of c-Si solar cells (Vishnu Kant Bajpai)

ObjectiveThe Ni/Cu front-contact metallization scheme for c-Si solar cells is a low cost and potentiallyuseful for high efficiency solar cells manufacturing. But due to lower adhesion betweennickel and silicon, this technique left behind the screen printing technology currently beingused in solar industry. So the ultimate target is to get better adhesion of nickel with siliconwithout any performance sacrifice.Experimentation

Mainly the experiments were performed to study the screen printed contacts and thegrowth mechanism of nickel film using electroless nickel deposition.

ARC (antireflective coating) at front side of the complete screen printed solar cell isremoved using HF solution so that the only front side metal grid remains on the solar

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cell. Now the scotch tape test is performed to check the adhesion of screen printedcontact with the solar cell.

The 16 cm2 mono c-Si semi-processed and complete screen printed solar cells procured fromBEL, Bangalore were characterized using CORESCAN (a solar cell characterizationinstrument @NCPRE). The cells performance was satisfactory and compatible with respectto recent industrial solar cells. Some of the scan results are shown below in the form of 2Dand 3D graphs. The instrument is mainly for qualitative measurement/scanning of four basicparameters related to solar cell performance: metal-semiconductor front side contactresistance, open-circuit voltage, light beam induced current and shunt resistance in a solarcell. Using these scans, the solar cell processing steps can be optimized.

Fig. 12.7: 2D and 3D maps in a Corescan (contact resistance scan) of a 16 cm 2 mono c-Si screen printed solarcell.

Fig. 12.8: 2D and 3D maps in a LBIC scan (Light Beam Induced Current scan) of a 16 cm 2 mono c-Si screenprinted solar cell.

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Fig. 12.9: 2D and 3D maps in a Voc scan (Open Circuit Voltage scan) of a 16 cm 2 mono c-Si semi-finished(without front contact) solar cell.

Fig. 12.10: 2D and 3D maps in Shunt scan (locate junction shunts) of a 16 cm2 mono c-Si screen printed solarcell.

Since the thickness of the nickel film should be in the range of 200-300 nm because

higher thickness will cause unnecessary contact resistance increment and the onlypurpose of this nickel film is provide uniform metal layer for subsequent copperelectroplating and to prevent copper diffusion into the junction region.

So it is tried to get uniform nickel layer thickness by the subsequent annealing

process. For this, the nickel deposited samples were prepared using alkaline bathnickel deposition for 1 min, after that the samples were annealed @420 deg C for 1min.

Fig. 12.11: SEM images of (a) before, (b) after annealing process of nickel film deposited on textured emitter of a solar cell at 420 deg C for 1 min

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To study the growth process of nickel deposition using electroless deposition

technique, the silicon substrate was immersed into the deposition bath (alkalinesolution with pH ~7.5) for very small periods of time (10s and 30 s) and characterizedusing scanning electron microscope.

Fig. 12.12: SEM images of (a) 10s, (b) 30s of nickel deposition on textured emitter of a solar cell.

Results and Discussions On applying the scotch tape test on the screen printed contacts after removal of ARC,

it is found that the adhesion of screen printed contacts is also very poor as in the caseof nickel-copper. But due to the metallization process applying on the front side ofsolar cell without removing the ARC layer enhances the adhesion of the contacts.

After annealing the deposited nickel film in the form of spheres gone through some

changes but they are not completely agglomerated.

It is observed that in most of the cases the electroless nickel deposition on textured siliconsubstrate is in the form of spherical drops. Initially some nucleation sites are created and asthe deposition progresses these nucleation sites grow in form of spherical drops. This isundesirable because the droplet size varies with the deposition condition and this sphericaldrop like deposition may be a stronger reason for lower adhesion with silicon substratebecause the contact area reduces as the spherical drop grows and when the spheresagglomerate, there is a chance of hydrogen gas trapping.

Fig. 12.13: SEM image of Ni deposited sample on textured Si solar cell showing the lower contact area with the substrate.

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The nucleation sites created due to surface defects and displacement reactions

occurring at the interface which is purely a surface phenomenon and there is no roleof reducing agent. The reducing agent comes into play after creation of nucleationsites and then it contributes to the growth process.

Future Plan The annealing time and temperature needs to be optimized to get uniform nickel layer

thickness by proper agglomeration process. To find out the reason of higher deposition at the tops of textured silicon substrate

compared to valley region because this leads to do deposition for larger period of timeto cover the whole exposed area and unnecessary nickel buildups at the tops oftextures.

To metalize semi-processed solar cells using nickel-copper scheme and will try to

optimize the adhesion improvement process using Corescan instrument, so that wecan cross check any adverse effect of metallization on the solar cell performance.

We are developing an adhesion measuring tool. If successful, we will use this to

optimize the metallization process with respect to adhesion.

12.2.5 Characterization of Background plating for varying bath temperature(Mehul Raval)

Objective:Given the possible impacts of background plating on a solar cell, it is important to investigatethe influence of various bath parameters and define an optimum process window to minimizethe same. In current work, effect of bath temperature and sample activation on thebackground plating under nickel plating has been analyzed. QSSPC and Reflectance studiesafter plating and annealing have been performed to ascertain its impact on the solar cells.Sample Preparation and Experimental Conditions:

Solar cells of size 4cm x 4cm were procured from an industrial solar cellmanufacturer which were laser diced from 12.5cm x 12.5cm c-Si p-type solar cells with abase resistivity of 1 ohm-cm and thickness of 220µm. The sheet resistance of the diffused n-region was in the range of 40-60 ohm/square with ARC thickness of 75nm. The cells wereprocessed till the ARC and no front or backside metallization were present. For thebackground plating experiments, the back side of the cells were covered with a polymer sheetand hence only the front side was exposed to electroless Ni plating solution. PdCl2 basedactivation of samples was performed prior to exposure to the bath solution. Since the aim ofthe experiments was to observe background plating, no patterning of the front side wasperformed.

An optimized Ni bath was selected for experiments. Bath temperatures of 70°C and80°C were used to check the influence of different degrees of bath activity. The bath pH was5.2. Samples were exposed to the plating solution for 60 seconds and then annealed at 400°Cfor 30 seconds. The cells were cleaned in an ultrasonic DI water rinse for 10 minutes afterexposure to plating solution and then the back side polymer sheet was removed. To avoidbuild up of the miscellaneous ions due to bath ageing, a fresh bath was taken for each set ofexperiments at different temperatures.Sample Characterization:

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The lifetime and front surface reflectance studies were done after the exposure andannealing steps. For the life time measurements, IR and UV filter were used in the QSSPCsetup to ascertain the area of impact due to background plating. A UV-Vis setup withintegrating sphere was used for the reflectance measurements.Results and Discussions:

Fig. 12.14 and 12.15 represent the front surface reflectance data for bath temperatureof 70°C and 80°C respectively. It can be observed that there is not much variation in the frontreflectance for bath temperature of 70°C, while there is a noticeable shift in the reflectancespectrum for bath temperature of 80°C. The change was also reflected by change in the colorof ARC. This would in turn change the optical constant value for the life time measurementsin the QSSPC setup. However, the reflectance data doesn’t change post-annealing of thesamples. So the changes in the life time measurements after accounting for optical constantvariation would indicate changes in the bulk properties of the cells.

Fig. 12.14. Reflectance data for cells exposed to Ni bath temperature = 70°C and pH = 5.2

Fig. 12.15. Reflectance data for cells exposed to Ni bath temperature = 80°C and pH = 5.2

Based on the change in reflectance, variation in the optical constant for cells treated at a bathtemperature of 80°C were obtained as shown in table 12.1. It can be observed that for IR andUV illumination in QSSPC setup, the changes in the optical constant are of opposite signsdue to variation in the two sections of reflectance data. The subsequent variations in the lifetime are shown in tables 12.2 and 12.3 under IR and UV illumination respectively. The trendfor variation for a bath temperature of 80°C is same for both types of illumination and the lifetime tends to recover after annealing. The trend was different for bath temperature of 70°Cand since UV illumination will only probe the region close to emitter, it indicates anirreversible decrease in the life time due to background plating.

Table 12.1. Variation in optical constant based on reflectance data forbath temperature of 80°C

Cell Processing % change in opticalconstant for IRillumination

% change in opticalconstant for UVillumination

No processing 0 0Exposed to Ni bath -2.7 +3.28Annealed post exposure

-3.23 +3.1

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Table 12.2. Life-Time data with IR illumination in QSSPC setup for differentbath temperatures

Bathtemperature(°C)

%change in Lifetime afterplating(sec) @ 1014cm-3

%change in Lifetime afterannealing(sec) @ 1014cm-3

70 -8.64 -1.480 -8.2 -2.0

Table 12.3. Life-Time data with UV illumination in QSSPC setup for differentbath temperatures

Bathtemperature(°C)

%change in Lifetime afterplating(sec) @ 1014cm-3

%change in Lifetime afterannealing(sec) @ 1014cm-3

70 -19.66 -20.6280 -7.0 -2.3

Plan for coming six months:In continuation of the background plating studies, impact of variation in temperature

and pH would be checked for activated samples. Studies of optimization of nickel seed layerwill also be continued and then solar cells will be fabricated with optimum seed layer andcharacterized for various parameters.Research Publications:

1) Mehul C. Raval and Chetan Singh Solanki, “Surface and Lifetime Studies forUnintended Deposition on Solar Cells during Ni-Cu Plating”, Accepted for EUPVSEC 2012, Frankfurt, Germany.

12.2.6 Slicing of silicon wafers for PV applications using Wire Electric Discharge Machining (We-EDM)

(Supervisor: Prof. Suhas S. Joshi, Prof. Ramesh Singh, Ph.D. Student: Dongre G.G., Dual Degree M. Tech. student: Ashwin P.)

Salient features: Existing silicon ingot slicing processes like ID (inner diameter) saw and abrasive wire cuttinghave drawbacks of high kerf loss, lower finish and limitation on the thickness of wafer. In thepresent study, wire-EDM process was used for Si ingot slicing with wire EDM appears tohave a very large potential as compared with the conventional slicing methods. It is clear thatthe wire EDM process could potentially produce thin wafers (up to 100 µm) with minimumkerf loss (around 15-20%) and higher slicing rate (~1 mm/min).

Research publications:Journal publication:

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1. Dongre Ganesh, R.K. Singh, Suhas S. Joshi, "Response Surface Analysis of Slicing of

Silicon Ingots with Focus on Photovoltaic Application," Accepted for publication in

Journal of Machining Science and Technology (Taylor and Francis publisher).

Innovations:Development of efficient silicon ingot slicing method for photovoltaic applicationApplication potential: Development wire-EDM setup for silicon ingot slicing.a) Long term: Availability of wire-EDM technology for fabricating silicon wafers of size as small as 150 µm or less.b) Medium term: Prototype of a wafer slicing machine based on WEDM technology and processes for slicingof 100 µm to 500 µm Silicon wafers from ingot c) Short term: Wire EDM process optimization where we will minimize kerf loss and maximization of slicing speed and minimization of wafer thickness by using small diameter wire.Research/development work to be done in next six months:Various activities of the project planned for future work are as follows:• Process Optimization: Parametric optimization for slicing of silicon ingot process forminimizing wafer thickness, reduction in kerf loss and subsurface damage• Mathematical Modeling of Slicing of silicon ingot process: Numerical Model for wirevibrations during ingot slicing, effect of thermal spalling and fracture mechanics of siliconingot slicing. • Advanced experiments: Investigate prospective use of rotation of Si ingot during cuttingfor debris removal, wire- EDM process improvement (use of different dielectric and differentwire materials) in improvement of slicing rate and reduction in kerf loss. • System Development: Development of dedicated table top setup for slicing of silicon ingotand scrutinize use of multi wire-EDM.

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Detailed progress report: This report is based on the experimental work carried out to study effect of wire-EDM process parameters on silicon ingot slicing

Fig. 12.16: Photograph of experimental setup

Fig. 12.16 shows schematic experimental setup for silicon ingot slicing. In this process a thin

single-strand metal wire, usually brass, is fed through the work piece which is submerged in a

tank of dielectric fluid. The wire is constantly fed from a spool and is held between upper and

lower diamond guides. Due to the inherent properties of the process, wire-EDM can easily

machine complex parts and precision components out of hard conductive materials but the

process not has been used extensively for the semiconductor materials like silicon. As shown

in Fig. 12.16 a 100µm diameter brass wire was used as a tool electrode (cathode) and three

inch square polycrystalline silicon ingot with resistivity 0.5 Ω-cm is used as a work piece.

Fig. 12.17: Photograph of silicon wafer cut by wire-EDM process

Fig. 12.17 (a) shows photographs of silicon ingot sliced by wire-EDM process. However, itwas observed that the slicing speed remains more or less identical for entire depth of thewafer. Therefore, in this investigation on slicing speed, kerf width and surface roughness, it

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was felt that machining shorter depth of 5 mm over the height of 75 mm would be sufficient.So, in each experiment a 3” wafer of 500 µm thickness and length of cut is approximately5mm was generated as shown in Fig. 12.17 (b). In this experimental analysis, slicing speed,kerf width and surface roughness have been considered as the response.

Fig. 12.18: Theme of experiments

Various levels of processing parameters as indicated in the Table 12.4. Experiments wereperformed using constant parameters as wire tension 3N, conductivity of dielectric water as 3micro-Siemens and water pressure at 10 Kg/cm2. All these experiments are repeated in orderto assess the reputability of results.

Table 12.4: Process parameters with their levels

Variable SymbolLevels

1 2 3Current (A) I 3.5 4.5 5Pulse off-time (µs) Toff 30 35 40Servo Voltage (V) SV 87 85 80Pulse on-time (µs) SA 8 10 ---Wire feed rate (mm/s) WP 14 16 18

Effect of process parameters on slicing speed

Fig. 12.19 gives effect of processing parameters on slicing speed. It is observed from Fig.12.19 (a and c) that slicing speed increases with the current and pulse on-time as the energyof sparks increases by increasing current and pulse on-time. However, increase current above5A or increase in pulse on-time above 10 µs will either leads to wire breakage due to smallsize of wire (100 µm dia.) used in experiments or it will lead to breakage of thin wafer (500µm) due to increase in energy of sparking. This concludes that for cutting thin wafers using100 µm diameter wire low energy must be used for cutting. In this experimental study authorshad studied effect servo voltage on slicing speed. In order to understand this a typical pulsecycle is studied by Tarang et al. in 1995. This depicts that higher the servo reference voltagegives longer discharge delay time and hence lower cutting speed, while, lower value of theservo voltage gives shorter discharge delays and higher cutting speed. The same trend wasobserved in Fig. 12.19(d), where decrease in servo voltage increases the cutting speed.

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Fig. 12.19: (a-e) Effect of processing parameters on slicing speed

Effect of processing parameters on kerf widthAs shown in the Fig. 12.20 (a-e) increase in energy parameters like current, servo voltage andpulse on-time kerf width increases. However, increase in off-time shows decrease in kerfwidth, this due to fact that increases in off-time reduces the frequency of sparking and hencethe material removed per unit time. The effect of wire feed rate is negligible on kerf width.However, it is observed that the kerf width is maximum at the middle as compared to theends of the cross section. This is mainly due to the wire vibrations, as this work involvessmall wire diameter of 100 µm used for slicing of silicon ingot of height 75mm. It is evidentfrom the Fig. 12.20 (d) that pulse on-time is the most significant factor for increase in the kerfwidth, this due fact that the increase in the pulse on-time increases the discharge energy of thepulse and hence the kerf width dimension. The maximum kerf width was observed at pulseon-time of 10 µs, so in-order decrease the kerf width the minimum value of pulse on-time (8µs) must be used. Pulse on-time below this value gives non practical cutting speed and wasused only for finishing cuts.

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Fig. 12.20: (a-e) Effect of processing parameters on kerf width.

Effect of processing parameters on surface roughness

Surface roughness of the wafer measured at three locations that are at the top, middle and end(5 readings at each position). It does not show (Fig. 12.21 (a-e)) any prominent correlationwith the processing parameters. However, it increases slightly with increase in pulse on-time,due to fact that increase pulse on-time will increase the energy of sparking and hence thedepth of the craters. Nevertheless, increase pulse-off time decreases surface roughness due tobetter evacuation of debris from the inter-electrode gap. The other parameters like current,servo voltage and wire feed rate does not influence the surface roughness by a significantamount. The results show lot of variation in the surface roughness for the repeat experiments,this is due to fact that the surface roughness in wire-EDM operation dependent on the craterdimensions and it is difficult to maintain that value for rough cut operation like slicing ofsilicon ingot.

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Fig. 12.21: (a-e) Effect of processing parameters on surface roughness.

ConclusionParametric analysis will give an idea for process optimization and understanding the processmechanics. This work will leads to the development of a novel wire-EDM process for slicingof silicon wafers for application in Photovoltaic cells. Finally, the aim is develop thetechnology by keeping the view on transferring value of research to the benefit of Industry.Applied Materials have shown interest in this work and started collaborative project on thiswith IIT Bombay.

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