124 Lecture 4

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ECE 124AECE 124A

Prof. Kaustav BanerjeeElectrical and Computer Engineering

E-mail: kaustav ece.ucsb.edu

Lecture 4, ECE 124A, VLSI Principles Kaustav Banerjee

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M Pr

M Pr

A single-well CMOS.

different transistors

A problem with LOCOS is.Birds Beak!......which can eliminate the


..

(solution: use STI-shallow trench isolation)

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Si Wafer:

Sin le-cr stalline li htl -do ed wafer 6-12 inch diameter

Thickness of at most 1mm Obtained by cutting a single crystal ingot into thin slices An epitaxial layer is grown over the surface of the wafers

e ore ev ce process ng A starting p- wafer has a typical resistivity of 25-50 Ohm-cm,

which corresponds to a doing level of the order of 1015

cm-3

Well dopings are of the order of 1016 to 1017 cm-3 (this

explains the lower doping of the p substrate Crystal orientation: all ICs are manufactured using (100)

sur ace or entat on. y ewer mper ect ons on asurface.gives significantly better Si/SiO2 interface)


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A M rn M Pr A M rn M Pr

AlCu

gate-oxide

TiSi2

poly

2

Tungsten

p-well n-well

+

p-epi

SiO2

n+ p+

DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process

--------


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Basic StepsBasic Steps--IIII Photolithography:

Applied throughout the manufacturing process

In each rocessin ste a certain area of the chi needs to

be masked out---using an appropriate optical mask Desired processing step can be selectively applied to the

remaining regions

Needed for a number of processing steps:

oxidation, etching, metal and polysilicon deposition, ion

implantation eren opera ons nvo ve n a yp ca p o o ograp c

process

Oxidation layering, photoresist (PR) coating, stepper exposure,PR develo ment and bake acid etchin s in-rinse-dr

Negative PR: a light sensitive polymer that is originally soluble in an organicsolvent, but has the property that the polymers cross-link when exposed to light,


.

Positive PR: originally insoluble but soluble after exposure

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Photolithography:

Photomasking with negative photoresist


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PhotoPhoto--Lithographic ProcessLithographic Process

oxidation

opticalmask

Start.

- -automated handling of wafers.

2A glass mask orreticle containin

3b

photoresist coatingphotoresist

removal (ashing)stepper exposure

3athe patterns that wewant to transfer tothe Si

Selectively removeremaining PR usinghigh-temperatureplasma without

damaging devicelayers

process spin, rinse, dryacid etch

photoresistdevelopment

Typical operations in a single

photolithographic cycle (from [Fullman]). In acid or basesolutions to removethe non-exposedareas of PR

-Ex osed area read

8

step

baked to hardenthe remaining PR5

6

for any processsteps such asimplantation, metaldeposition etc. 7


Material is selectively removed from areasof wafer that are not covered by PR

Clean wafer withdeionized water

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Patterning of SiO2Patterning of SiO2Si-substrate

Hardened resist

Chemical or plasmaetch

(a) Silicon base material

Photoresist

SiO2

2

Si-substrate

(d) After development and etching of resist,

(b) After oxidation and deposition

of negative photoresist

Si-substrate

SiO2

chemical or plasma etch of SiO2

Hardened resist

UV-light

Patternedoptical mask

-su s ra e

(e) After etching

Si-substrate Si-substrate

SiO2

f Final result after removal of resist


c epper exposure

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CMOS Process at a GlanceCMOS Process at a GlanceDefine active areas

Etch and fill trenches

Device isolation: Local Oxidationof Si (LOCOS)Birds Beak

Implant well regions

Shallow Trench isolation (STI):better suited for small devicegeometries. Plasma etch trench +

Deposit and patternpolysilicon layer

grow t n ner ox e 10-20 nm) layer + deposit oxide intrench

Implant source and drainregions and substrate contacts

Create contact and via windowsDe osit and attern metal la ers


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Wafers placed in quartz tube embedded in a heated furnace(900-1100 C) Dopants introduced through a gas Dopants diffuse into the exposed surface Final dopant concentration greatest at the surface and

decreases in a gaussian profile deeper into the material on mp an a on:

Dopants are introduced as ions in the material Implantation system directs and sweeps a beam of purified

Wafer needs annealing (wafer is heated to 1000 C for 15-30minutes) to repair lattice damage and to activate the dopants


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Many of the materials (gate oxide, silicon nitride, poly etc)are directly deposited

Using a chemical deposition process (CVD etc)

Etching:

Dry etching: uses plasma (like sandblasting)

Planarization

Surfaces must be flat Chemical Mechanical Polishing (CMP) before deposition


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M Pr W l M Pr W l Thr Thr

p+

- a ase mater a : p+ su stratewith p-epi layer

p-epiSiO

2

3SiN

4

(b) After deposition of gate-oxide and

sacrificial nitride (acts as abuffer layer)p+

p+

(c) After plasma etch of insulatingtrenches using the inverse ofthe active area mask


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M Pr W l M Pr W l Thr ThrSiO

2

d After trench fillin CMPplanarization, and removal of

sacrificial nitride

(e) After n-well andn

Tp

(f) After p-well andV

Tnadjust implants

p


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M Pr W l M Pr W l Thr Thrpoly(silicon)

(g) After polysilicon deposition

and etch

(h) After n+ source/drain and

p+n+

p+source ra n mp an s. esesteps also dope the polysilicon.

SiO

(i) After deposition of SiO2insulator and contact hole etch.


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M Pr W l M Pr W l Thr ThrAl

(j) After deposition andpatterning of first Al layer.

(k) After deposition of SiO2insulator, etching of vias,

AlSiO

2

second layer of Al.


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A v n M lliz i A v n M lliz i

interconnect technology:

used AlCu for lines and Wor v as.


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Advanced Metallization: Cu baseAdvanced Metallization: Cu base


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Full Processed WaferFull Processed Wafer

Single die

Wafer

Going up to 12 (30cm)


From http://www.amd.com

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New Transistors: Double Gate FETsNew Transistors: Double Gate FETs

----Tri-gate

Multi-Fin Structure

WSiLg

GateGate

TSiGate 1

Gate 2Source SourceSource

DrainDrain

-

Source: IntelSource: Intel

Higher ON current for lower SD Leakage

Even better FETs: i Gate-All-Around FETs--- ultimate case is GAA Si Nanowire FET or


ii) Carbon Nanotube FETs (back-gated or top-gated structures)

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124 Lecture 4