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1/2550 A. Yaicharoen 5
(a) Unprogrammed and-gate (b) Unprogrammed or-gate (c) Programmed and-gate realizing the term ac (d) Programmed or-gate realizing the term a + b (e) Special notation for an and-gate having all its input fuses intact (f) Special notiation for an or-gate having all its input fuses intact (g) And-gate with nonfusible inputs (h) Or-gate with nonfusible inputs
PLD Notation
1/2550 A. Yaicharoen 6
Types of PLDs
• Programmable ROM (PROM) Fixed AND-array, programmable OR-array
• Programmable Logic Array (PLA) Programmable AND-array and OR-array
• Programmable Array Logic (PAL) Programmable AND-array, Fixed OR-array
1/2550 A. Yaicharoen 13
Example of combinational logic design using a PLA. (a) Maps showing the multiple-output prime implicants. (b) Partial covering of the f1 and f2 maps. (c) Maps for the multiple-output minimal sum. (d) Realization using a 3 4 2 PLA.
Example
1/2550 A. Yaicharoen 14
(a) Circuit diagram. (b) Symbolic representation.
Ex-Or-gate with a Programmable Fuse
1/2550 A. Yaicharoen 15
General structure of a PLA having true and complemented output capability
More on PLA
1/2550 A. Yaicharoen 16
Karnaugh maps for the functions
f1(x,y,z) = m(1,2,3,7) and
f2(x,y,z) = m(0,1,2,6)
Example
1/2550 A. Yaicharoen 17
Two realizations of f1(x,y,z) = m(1,2,3,7) and f2(x,y,z) = m(0,1,2,6).
(a) Realization based on f1 and 2
(b) Realization based on 1
and 2
f
ff
Example