126569114-Simulation-of-Power-Electronic-Systems-Using-PSpice.pdf

1

Simulation of Power Electronic

Systems Using PSpice

Presented by Nik Din Muhamad

2

Presentation Outlines

Know background of SPICE

Understand Power Electronics Circuits/Systems

Know how to use VPULSE to generate useful waveforms

Know how to make simple models using ABM

In order to use Pspice for power electronic

systems, we have to:

3

Scope

PSpice

System/Circuit Level Simulation

Power Electronic Circuits/Systems

Simulation

This presentation covers:

4

SPICE/PSpice

SPICE turns 38 years old this year I Knew SPICE when she was 17 years old I love PSpice because she can do almost anything I need with FOC. I like to talk about her.

Did you know?

5

Why simulation?

Saving of development time

Saving of costs (burnt power circuits tend to be expensive)

Better understanding of the function

Simulations are essential ingredients of the

analysis and design process in power

electronics:

6

continued

Testing and finding of critical states and regions of operation (Worst Case Analysis)

Stress test (Smoke Analysis)

Optimization of system

Testing new ideas

7

Overview

Simulation of analog circuits normally

uses three basic tools: SPICE simulator, Mathematical analysis package, and Microsoft Excel.

8

SPICE

Simulation Program for Integrated Circuit Emphasis

Intended for ICs, not for power electronics.

Uses iterative Newton-Raphson Algorithm to solve a set of nonlinear equations.

9

SPICE LIMITATIONS

The Newton-Raphson algorithm is guaranteed to converge if the equations is continuous.

The transient analysis has the additional possibility of unable to converge because of the

discontinuity in time.

10

Voltage and currents are limited to +/-1e10.

Derivatives in PSpice are limited to 1e14.

The arithmetic used in PSpice is double

precision and has 15 digits of accuracy.

Computer Hardware Limitation:

SPICE LIMITATIONS

11

Power Electronic Circuit

Power electronic circuits are characterized by switching

on and off of power

semiconductor switches; the

generated waveform is

passed through inductors and

capacitors for filtering.

12

Power Electronic Circuit

Due to switching action of the switch, discontinuity (in circuit variables and in

time) can easily occur during simulation,

which leads to convergence problem.

Avoid discontinuity

13

Discontinuity Analogy: A Bump on the Road

Whole car shakes when I hit a bump on the road

PSpice doesnt like discontinuity as we dont like a bump on the road.

Unacceptable Bump

Acceptable Bump

14

Avoid Discontinuity

G

S

VGS

t

VGS

t

All signals must be made less discontinuous All relationships must be continuous

15

VPULSE Waveform generator

PULSE SAWTOOTH TRIANGULAR

16

VPULSE Waveform generator

In order to use PSpice for power electronic

circuits, the first thing you have to know is to

program VPULSE to produce these waveforms:

PULSE Sawtooth Triangular

17

VPULSE Waveform Generator Part

V1=

V2=

TD=

TR=

TF=

PW=

PER=

V1

V2

TD

PW

PER

has 7 parameters to set TD can be zero, others can not!

know what parameters to adjust and to fix.

18

VPULSE To Generate Pulse Waveform

V1=0

V2=12

TD=0

TR=10n

TF=10n

PW=10u

PER=20u

Very small values for TR and TF Duty cycle = PW/PER

PW

TR 0 TF 0

PER

V1

V2

19

A Typical application Buck Converter (Open Loop)

V2

20V

0

V+

MU R1520V3

TD = 0TF = 10nPW = 10uPER = 20uV1 = 0TR = 10nV2 = 12V

V-

10680uF

M2IR F150

100uH

A Pulse waveform is used to drive a MOSFET

ON and OFF.

20

Its Pulse (I)

V1=0

V2=12

TD=0

TR=10n

TF=10n

PW=10u

PER=20u

Duty Cycle, %5020

10

PER

PWD

21

Its Pulse (II)

V1=0

V2=12

TD=0

TR=10n

TF=10n

PW=5u

PER=20u

Duty cycle of the waveform is adjusted by adjusting PW

%2520

5

PER

PWD

22

V1=0

V2=12

TD=0

TR={20u-20n}

TF=10n

PW=10n

PER=20u

Very small values for TF and PW TRPER

PW

TF

PER

VPULSE To Generate Sawtooth

23

A Typical application Buck Converter (Closed Loop)

10

100uH

0

M2IR F150

V4

680uF

-++ -

E1

EGAIN = 4

0

MU R1520

V2

20V

Comparator

Sawtooth

Gen.

Control

Signal

+

-

Gate

Driver

For Closed-loop, the control signal

is compared with a sawtooth

waveform to produce the pulse

waveform.

24

PSpice Implementation

Sawtooth VPULSE Control VDC Vpulse

Comparator Control

Signal

Gate

Driver

100uH

-++ -

E1

EGAIN = 1

0

10

0

M2IR F150

0

MU R1520

680uF

E2

V(%IN +, %IN-)

ETABLE

TABLE = (0,0 (200u,12)

OU T+OU T-

IN +IN -

V5

2.5Vdc

0

V2

20V

V3

TD = 0TF = 10nPW = 10nPER = 20uV1 = 1VTR = {20u-20n}V2 = 4V

Gate Driver E Comparator ETABLE

25

Its Waveform (I)

Sawtooth

Control

Pulse

D = 50 %

26

Its Waveform (II)

Sawtooth

Control

Pulse

Duty Cycle of the Pulse is adjusted by adjusting

Control Signal.

D = 33%

27

V1= -1

V2= +1

TD=0

TR= {10u-10n}

TF= {10u-10n}

PW=20n

PER=20u

Very small value for PW TRTF PER/2

PW

PER

VPULSE To Generate Triangular wave

28

VPULSE Its Triangular Wave

29

Triangular Wave Typical applications

VV1

TD = 0

TF = {(1/(F TRI* 2)-10n)}PW = 20nPER = {1/F TRI }

V1 = -1

TR = { (1/(F TRI *2))-10n}

V2 = +1

SI NE

0

V

V

0

TR I

PARAMETERS:Ma = 0.8Mf = 21FTRI = {FSINE*Mf }FSINE = 50VD C = 100

VD C*(V(SI NE)-V(TRI))/ ABS(V(SINE)-V(TRI) )

SPWMV2

FR EQ = {F SIN E}VAMPL = {Ma}VOFF = 0

PH ASE = { -90/ Mf }

Bipolar SPWM

Comparator

30


Bipolar SPWM

Time [ms]

40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60ms V(SPWM) 0

-100

0

100 V(TRI) V(SINE) 0

-1.0V

0V

1.0V

31


Unipolar SPWM

BV2a


PH ASE = { -90/ Mf +180}

SI NE1

V

V2


PH ASE = { -90/ Mf }

0

A

0

V

V

0

TR I

0.5*VD C*(V(SI NE2)-V(TRI))/ABS(V(SIN E2)-V(TRI))

SI NE2

0.5*VD C*(V(SI NE1)-V(TRI))/ABS(V(SIN E1)-V(TRI))

VPARAMETERS:Ma = 0.8Mf = 21FTRI = {FSINE*Mf }FSINE = 50VD C = 100

VV1

TD = 0

TF = {(1/(F TRI *2)-10n)}PW = 20nPER = {1/F TRI }

V1 = -1

TR = { (1/(F TRI *2))-10n}

V2 = +1

Comparator 1

Comparator 2

32


Unipolar SPWM

Time [ms]

40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60ms V(A)-V(B)

-100V

0V

100V

V(A)-V(B)

V(SINE1) V(SINE2) V(TRI) -1.0V

0V

1.0V

33

Analog Behavior Model (ABM) Makes the Circuit Simpler

Use equations to model circuits

Comparator Single Phase Rectifier Three Phase Rectifier Buck Converter in CCM Single Phase Inverter

34

ABM Behavior Model of Comparator

IF the voltage at the terminal V(+) is

greater than the voltage at terminal

V(-) the output V(out) is HIgh,

otherwise the output is LOw.

IF(V(+)>V(-),HI, LO)

(1) Using IF-Then-Else function

(2) Using signum function

(V(+)-V(-))/ABS(V(+)-V(-))

- V(-)

V(out)

+ V(+)

35


- V(-)

V(out)

+ V(+)

(4) Using Op-amp alike

0

V(+)

V(-)

+ - A*(V(+)-V(-))

V(out)

(3) Using I/O graph

0 V(+)-V(-)

V(out)

36

ABM Comparator in PSpice

TR I

V1

TD = 0

TF = {(1/(F TRI *2)-10n)}PW = 20nPER = {1/F TRI }

V1 = -1

TR = { (1/(F TRI *2))-10n}

V2 = +1

out3

V

LIMIT(10k* (V(SINE)-V(TRI)),10,-10)

0

IF (V(SINE)>V(TRI) ,10, -10)

V

out1

PARAMETERS:Ma = 0.8Mf = 21FTRI = {FSINE*Mf }FSINE = 50VD C = 10

0

out4

E1

V(%IN +, %IN-)ETABLE

TABLE = (-100u,-10) (100u, 10)

OU T+OU T-

IN +IN -

TR I

V

V

V

V2


PH ASE = { -90/ Mf }

0

out2

V

SI NE

SI NE

VD C*(V(SI NE)-V(TRI)) /ABS(V(SINE)-V(TRI ))

NO 2 is implemented using ETABLE Others are implemented using ABM part NO 2 & NO 4 are suitable for Op-amp (Error Amplifier)

1

2

3

4

37


Time [ms]

40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60ms V(OUT3) V(OUT2) V(OUT1) V(OUT4)

-10V

0V

10V V(TRI) V(SINE)

-1.0V

0V

1.0V

These waveforms come from the outputs of four comparators

38

ABM Behavior Model of Rectifier (I)

V1a

FR EQ = 50VAMPL = 340

VOFF = 0R1a

1k

DbreakD6

0

DbreakD4

DbreakD5

DbreakD3

in

R1b

1k

E1

ABS(V(IN))

EVALU E

OU T+OU T-

IN +IN -

V1

FR EQ = 50VAMPL = 340

VOFF = 0

00

V(out)=ABS(V(IN))

39

ABM Behavior Model of Rectifier (II)

Van Vbn

Vcn

+

-

V(out) = 0.5*(ABS(V(an)-V(bn)

+ABS(V(bn)-V(cn))

+ABS(V(cn)-V(an)))

40

ABM Behavior Model of Buck in CCM

0

RLMU R1520

100uH

680uF

IR F540

V3

TD = 0TF = 10nPW = 10uPER = 20uV1 = 0TR = 10nV2 = 12V

V2

20 Vdc

+

-

Vd

Vd = d*Vin

100uH

d

0

680uF RL

Vin

E1

V(%IN+)*V( %IN-)

EVALU E

OU T+OU T-

IN +IN -

+

-

Vd

d is a PWM signal with 1V amplitude.

41

ABM Behavior Model of Inverter

a

b

+

- Vab

Bipolar SPWM

0

+

-

E1

VDC*(V(%IN+)-V( %IN-))/ABS(V(%IN+)-V( %IN-))

EVALUE

OUT+ OUT-

IN+ IN-

SINE

TRI Vab

VDC

42

#TIPS

There are many different ways to model the same thing. So, be

creative!

Use a simple model wherever possible to reduce modeling time

and make simulation run faster

and converge better!

43

Quote about Model !

Models are like shoes; there is no one-size- fits-all model.

44

Our Case Study A Buck Converter with VMC

A Simple PWM Controller IC Model A PWM IC Controller IC Model including Soft-start

A PWM IC Controller IC Model Including Soft-start, Duty Cycle Max and Current

Limiter

45

Our Case Study A Buck Converter with VMC

SG3525

PWM Controller IC

- +

+

-

0

0

46

SG3525 PWM Controller IC

Key Functions:

Oscillator (Sawtooth Generator)

PWM Comparator and SR Flip-flop

Error Amplifier 5.1 V Reference Pulse Steering Logic

Shutdown and Soft-start Circuitry

47

SG3525

We do not need to have SG3525 model in PSpices library to simulate buck converter with VMC.

Error Amplifier Comparator Sawtooth generator

To verify the controller design, all we need are functional models of these:

48

SG3525 A Simple Model

To MOSFET

Driver -

+ +

-

Sawtooth

Error Amp. Comparator

49

A Buck Converter with VMC

-++ -

-

0

-

VPULSE

0

Vref

+

0

0

+

Comparator Error Amp.

Sawtooth

Buck Converter

Consider we know all circuit parameters.

Our interest is to simulate the system.

The controller is used to regulate the output

voltage at 5 V.

50

The controller is a linear controller and the design is based on a small-signal model.

So, the controller can not cope with large signal scenario such as start-up.

Initial values, which are equal to their steady state values, for the inductor current and the

capacitor voltage must be set.

A Buck Converter with VMC

51

Load Disturbance

How to set a load disturbance ?

Let the load disturbance is:

0 A

1 A

8 ms 8.5 ms

3A

R = 5 W

R = 1.666 W

R = 5 W

R is changed from 5 W to 1.666 W

52

Our Case Study How to set load disturbance ?

Using IPULSE

I1

TD = 8m

TF = 0.1u

PW = 0.5m

PER = 1m

I1 = 1

I2 = 3

TR = 0.1u

ILOAD

Allocate enough times for TR and TF

1

53

Load Disturbance

How to set load disturbance ?

5

TOPEN = 8.5m

1 2

TCLOSE = 8m

2.5

Using SW_tclose and SW_topen

5//2.5 =1.666

2

54

Load Disturbance: PSpice

0

R4av

{R3}

R7av

{R1}

R2av

{Resr}

ILOAD0VdcI

0

0

I1

TD = 8m

TF = 0.1uPW = 0.5mPER = 1m

I1 = 1I2 = 3

TR = 0.1u

-++ -

E1

EGAIN = 3

0

DbreakD5

L1

{L}

IC = 1A

E1av

-V(%IN+, %IN-)ET ABLE

(0,0) (250u,6)

OUT+OUT-

IN+IN-

0

I

V

E2av

V(%IN+, %IN-)ET ABLE

(0,0) (250u,5)

OUT+OUT-

IN+IN-

C4av

{C1}

input

V2av

{Vref }

C2av

{C2}

M1IRF150

R2

{Rbias}

R1av

50m

V1

TD = 0

TF = 10nPW = 10nPER = 10u

V1 = 0

TR = {10u-20n}

V2 = 3

V2

15Vdc

C1av

{C}IC = 5V

C3av

{C3}

out

R6av

{R2}

0

55

Load Disturbance: Results

Time [ms]

7.8ms 7.9ms 8.0ms 8.1ms 8.2ms 8.3ms 8.4ms 8.5ms 8.6ms 8.7ms 8.8ms I(L1) I(ILOAD)

0A

2.0A

4.0A V(OUT)

4.8V

5.0V

5.2V

Inductor Current

Output Voltage

56

Input Disturbance

How to set an input disturbance ?

Let the input disturbance is:

0 V

15 V

25 V

8 ms 8.5 ms

57

Input Disturbance

How to set an input disturbance ?

Use VPWL (Piece-Wise Linear Voltage Source)

0 V

15 V

8 ms 9 ms

25 V

PWL(T1,V1)(T2,V2)(T3,V3)(T4,V4)(T5,V5)

PWL (0,15) (8m,15) (8.0001m,25) (9m,25) (9.0001m,15)

58

Input Disturbance Responses

Time [ms]

7.8ms 8.0ms 8.2ms 8.4ms 8.6ms 8.8ms 9.0ms 9.2ms 9.4ms 9.6ms 9.8ms 10.0ms I(L1)

0A

1.0A

2.0A V(OUT)

4.8V

4.9V

5.0V

5.1V

V(INPUT) 10V

20V

25V

30V

Input Voltage

Inductor Current

Output Voltage

59

Start-up Scenario

Previous simulation skips start-up scenario. To know how the controller handles start-up, set the initial values for iL and vc to zero.

Time [s]

0s 100us 200us 300us 400us 500us 600us 700us 800us I(L1) V(OUT)

0

5

10

15

20

Output Voltage

Inductor Current

60

Start-up Scenario A very large overshoot and undershoot occur in inductor current. The duty cycle is at first at 1 for a long time and later at 0 for a long time too, then after that it gradually increases.

Convergence problem can easily occurs at this extreme condition.

Time


0

5

10

15

20 V(E1:1)

0V

2.5V

5.0V

Gate Signal

61

Start-up In practical circuit, another auxiliary controller is required to handle start-up.

This circuit is known as soft-start.

Soft-start circuit works by gradually increasing the duty cycle. So do the inductor current and capacitor voltage.

Time [s]


0

5

10

15

20 V(E1:1)

0V

2.5V

5.0V

Gate Signal

Soft start

Controller

VMC

Controller

62

Soft-start To add Soft-start

The previous PWM IC model is very useful and it is simple to set-up in PSpice.

It is enough to verify the design of controller based on small signal model.

However, to add soft-start controller and other protection circuits, we need a more flexible PWM IC

model.

63

A Modified PWM IC Model

R S

Oscillator

-

+

+

- Q

Sawtooth

Clock

Error Amp.

Comparator SR Flip-flop

The output of SR flip-flop is set by the Clock. The output of SR flip-flop is reset by Comparator.

64


Analog signals can be added at minus terminals of the comparator.

Digital signals can be added at the input Resets of FF.

R S

R R

Oscillator

-

+ +

- Q

Sawtooth

Clock

Error Amp.


-

- Analog

Signals Digital

Signals

65

Soft-start To add Soft-start Signal

Sawtooth is still compared with the control signal.

But, Control Signal can be either Error Amp. output (EAO) or Soft-start signal (SS), whichever is lower.

-

+

-

Sawtooth

Error Amp.

Output

Soft-start

To R of SR

Flip-Flop Control

Signal

66


The soft-start voltage is the capacitor voltage. The capacitor C is charged by a constant current source of 50 A. The result is a ramp voltage.

C determines the duration of soft-start.

-

+

-

Sawtooth

Error Amp.

Output (EAO)

Soft-start (SS) To R of SR

Flip-Flop

C

50 A

67

Soft-start How Soft-start works?

10 ms

Soft-start

Voltage

t

Use PWL to emulate soft-start voltage For the graph, PWL(0,0)(10ms,4V)

t

VCI

4 V

Slope = C

50

C = 125 nF

68


We need a selector to select either SS or EAO, whichever is lower, to be Control Signal.

We can use IF-Then-Else function IF(SS < EAO, SS, EAO)

+

-

Sawtooth

EAO

SS To R of SR

Flip-Flop

C

50 A

Control

Signal

Selector

69

Soft-start In PSpice

IF( V(%IN2)

70

Soft-start Start-up Signals

Time [ms]

Control Signal

0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms 0V

1.0V

2.0V

0V

2.5V

5.0V

0V

2.5V

5.0V

Soft-Start Signal

Error Amplifier Output

Control = IF(SS < EAO, SS, EAO)

71

Soft-start C = 125 nF (Too Small!)

Time [ms]

I(L1)

V(OUT)

0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms 0A

2.0A

4.0A

0V

2.5V

5.0V

7.5V

Soft-start signal ramps up too fast

tstart-up = 1ms

72

Soft-start Start-up Current and Voltage

Time [ms]

0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms

I(L1)

0A

1.0A

2.0A

V(OUT)

0V

2.5V

5.0V

7.5V

Still has a small overshoot and undershoot in inductor current

has a room for improvement by increasing C.

tstart-up = 3.2 ms

C = 25 nF

73

Soft-start Start-up Current and Voltage

C = 125 nF ; Start-up time is 30 ms. Time

0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms I(L1)

0A

1.0A

2.0A

SEL>>

V(OUT) 0V

2.0V

4.0V

6.0V

I(L1)

V(OUT)

74


To add digital signals for protection. For examples, Maximum Duty Cycle and Current Limiter Flip-flop can be reset either by PWM comparator, or Maximum duty cycle, or Current Limiter.

R S

R R

Oscillator

-

+ +

- Q

Sawtooth

Clock

Error Amp.


-

- Analog

Signals Digital

Signals

75

To Add Digital Signals DutyMax and CurrentLimit

Maximum duty cycle limiter is in digital form. It can be applied directly to the Reset of FF.

The switch current (or inductor current) must be compared with its limit value to produce a digital signal.

0U12A7432

1

23

U16A7432

1

23

8A

U11A7402

2

31 R

I(L1)

0

U10A7402

2

31

VClock

TD = 0

TF = 1nPW = 0.1uPER = 10u

V1 = 0

TR = 1n

V2 = 5V

Vdutymax

TD = {10u*0.85}

TF = 10nPW = {(10u-10u*0.85)-20n}PER = 10u

V1 = 0

TR = 10n

V2 = 5V

0

S

QEcurr_l imit

+V(%IN+, %IN-)ET ABLE

(0,0) (250u,5)

OUT+OUT-

IN+IN-

Dutymax

RESET 1 (EAO)

RESET 2 (CL)

RESET 3 (DMax)

SET

Set only by one i. e. the clock Reset can be done by three, whichever

comes first.

76

Time

0s 20us 40us 60us 80us 100us 120us 140us 160us 180us 200us V(SAWTOOTH)

0V

2.0V

4.0V V(DUTYMAX)

0V

2.5V

5.0V

V(DUTYMAX)

V(S) 0V

2.5V

5.0V

DUTYMAX

CLOCK

SAWTOOTH

DUTYMAX signal will only reset FF if the duty cycle is more than 0.85 This DUTYMAX is to make sure that the MOSFET always turns-off for each cycle

CurrentLimit signal will only appear and reset FF if the peak switch is greater than pre-specified value.


77

Time

5.6ms 5.7ms 5.8ms 5.9ms 6.0ms 6.1ms 6.2ms 6.3ms 6.4ms 6.5ms 6.6ms V(OUT) I(L1)

0

5

10


We want to limit this current at 8A

Inductor Current

Output Voltage

78

Time

5.6ms 5.7ms 5.8ms 5.9ms 6.0ms 6.1ms 6.2ms 6.3ms 6.4ms 6.5ms 6.6ms V(OUT) I(L1)

0

5

10

Output Voltage

Inductor Current

8A Limiter


What do we expect ?

Reset by EAO Reset by

DutyMax

Reset by

CurrentLimit Reset by EAO

79

A Load disturbance

at 6.0 ms

Time [ms]

5.90ms 5.95ms 6.00ms 6.05ms 6.10ms 6.15ms 6.20ms

V(DUTYMAX) V(Q)

0V

2.5V

5.0V V(CURRENTLIM) V(Q)

0V

2.5V

5.0V V(PWMCOMP) V(Q)

0V

2.5V

5.0V V(CLOCK)

0V

2.5V

5.0V


80

Knowing

There is no substitute for knowing what we are doing

81

CONCLUSION

Know how to program VPULSE for Pulse, Sawtooth, and Triangular waveforms.

Avoid discontinuity at any cost Use the simplest model possible Use a simple model first, and add complexity in stages.

No replacement for good understanding

In order to simulate power electronic circuit:

82

Q & A

Documents

126569114-Simulation-of-Power-Electronic-Systems-Using-PSpice.pdf