15 Jun 2006 1

Digital Video Transfer Results (WP2)

15 Jun 2006 2

Video Switch Unit

15 Jun 2006 3

Video Switch Subunit

15 Jun 2006 4

VIDEO HUB

15 Jun 2006 5

Video HUB Video Subsystem

15 Jun 2006 6

Supported Display modes Resolution

name Resolution Dot frequency

(pixel clock) MHz

Refresh rate (Hz)

Horizontal frequency

(kHz)

Notes

4:3 modes SVGA 800 x 600 36 – 56 56 – 85 35 – 53 XGA 1024 x 768 45 – 94 60 – 85 35 – 69 SXGA 1280 x 1024 108 – 157 60 – 85 64 – 91 1400 x 1050 101 - 180 60 - 85 65 - 85 *1) UXGA 1600 x 1200 162 – 229 60 - 85 75 – 106

Wide modes (720p) 1280 x 768 68 - 117 60 - 85 47 – 69 *1) 1680 x 1050 119 – 214 60 - 85 65 - 94 *1) HDTV 1920 x 1200 154 - 281 60 - 85 74 - 107 *1) HDTVplus 1920 x 1440 234, 297 60, 75 90, 112 *1)

15 Jun 2006 7

Changes in D1f: Video Switch Unit and Video Hub Technical Document

v.0.5

USB voltage lines to the connector updated

Commands to the table unit updated

15 Jun 2006 8

Video Switch Unit schematics, D2a

Page 1: Block Diagram Page 2: FPGA Page 3: Bus_A_Rcv, Page4: Bus_A_Tr Page 5: DVI_From_PC, Page6:

To_Monitor Page 7: Control (microcontroller) Page 8: Bus_B_Rcv, Page 9: Bus_B_Tr Page 10: Power + To_Table_Unit

15 Jun 2006 9

Video Switch Unit PCB, D2b

Video Switch Unit Proto1 PCB

15 Jun 2006 10

Video Hub schematics, D2a

Page 1: Block Diagram Page 2: FPGA Page 3: Bus_A_Rcv, Page4: Bus_A_Tr Page 5: Bus_C_Rcv, Page6: Bus_C_Tr Page 7: Control (microcontroller) Page 8: Bus_B_Rcv, Page 9: Bus_B_Tr Page 10: Power + To_Table_Unit

15 Jun 2006 11

Video Hub PCB, D2b

Video Hub Proto1 PCB

15 Jun 2006 12

Video Switch Unit FPGA, D2c

VHDL code written and simulated place & route made meets time constraints same FPGA design for both Video

Switch Unit and Video Hub

15 Jun 2006 13

Video Switch Unit SW, D2d

Video Switch Unit’s MCU code

•C code and Powerpoint slides in

the project web page

15 Jun 2006 14

Documents

Code based on:– D1f:

”D1f_VideoSwitchUnit_Technical_document_v_0_4.doc”

– D1g: ”ProposedInstructionsetV11.doc”

– 3rd Project Meeting Minutes, Braunschweig: ”Third project meeting agenda.doc”

15 Jun 2006 15

µController

Atmel AVR ATmegaAVR162:– 16 kB Flash– 512 B EEPROM– 1 kB RAM– 35 IO pins– 2 x USART– 2 x 16-bit Timers/Counters OR 4 x 8-bit

Timers/Counters– 3.3V (reduced operating frequency below

4.5V)– TQFP32 for production/DIP40 for prototype

15 Jun 2006 16

Toolchain used

1. C compiler: CodeVisionAVR 1.24.8 Standard Version

2. Debugger: AVR Studio 4.12 Service Pack 2

3. Emulator: JTAGICE mkII4. Programmer: AVR ISP mkII5. Editor: Emacs 21.3.1

15 Jun 2006 17

Main tasks of AVR

receive commands from UI/Master and decode:– reprogram FPGA (Crosspoint Switch

for DVI streams)– control DVI chips– redirect USB related commands to

ARM board– handshake with Table Unit (at the

moment not yet defined)

15 Jun 2006 18

Code Development statusMay 8, 2006

Switch Unit and Table Unit handshaking (RS-232) not done (waits for spec. approval)

STUALIVE response not done (waits for spec. approval)

Video Command decoding might need minor adjusting for special cases (Beamer, Teacher, etc.)

Audio and Voting not done (branch structure is in place)

Unit programming should disregard a requirement to send Master signal every 200ms