MERITS AND LIMITATIONS OF CIRCUIT SIMULATION IN POWER ELECTRONICS APPLICATIONS

SEPTEMBER 2005

Brian T. Irving

Member of R&D StaffDelta Products Corp.

RTP, NC

OBJECTIVE

Electrical circuit simulators have existed for more than 30 yrs. Despite the astonishing progress that simulators have made in that time, limitations still exist which restrict the designer from developing a complete, practical, "virtual" prototype of a power electronics circuit prior to hardware development. The goal of this presentation is to highlight these limitations, as well as merits, using simple comparisons between hardware measurements and simulation results.

OUTLINE

• Limitations• computation of characteristics related to detailed switching phenomena

• 90-W flyback converter used as example• inaccuracy during switching transitions

• causes• voltage stress• switching loss

• Merits• computation of characteristics related to multiple switching cycles

• 600 W two-switch forward converter used as example• loop gain• transient response

INTRODUCTION TO CIRCUIT SIMULATORS

• Two types of simulators used in power electronics applications which exist today

• SPICE simulators (e.g., PSPICE, SIMetrix, ICAP, etc.) which are designed to simulate both analog and digital circuits in linear and nonlinear implementations

• Piecewise linear simulators (e.g. SIMPLIS) which specialize in quickly modeling nonlinear systems by treating the circuit as a series of straight (linear) line segments to avoid solving the nonlinear differential equations, thereby significantly increasing the simulation speed

LIMITATIONS OF CIRCUIT SIMULATIONSWITCHING TRANSITIONS

• Circuit diagram of 90W quasi-resonant flyback converter

• Comparison made between hardware and simulation using SIMetrix (SPICE-type)

• simulation models obtained from manufacturer

• common parasitics incorporated into model

• dc resistance of windings used

• leakage inductance referenced to primary

• investigation of switch transition and voltage stress of main switch

RL VO

VCC

FE3D(fast)

1N5406(slow)

700nH (bead)

SPP20N60C3

45Ω2.2nF

2.2nF51k

51k

61mΩ 2.9µH

4xYA868C12

1nF 33Ω

4.3Ω

VCC

5.1Ω

RGP10M

VIN120 V

19 V

15 V

6mΩ

-3

-2

-1

0

1

2

3

4

5

6

7

0.E+00 1.E-07 2.E-07 3.E-07 4.E-07 5.E-07 6.E-07 7.E-07-300

-200

-100

0

100

200

300

400

500

600

700

drain-source voltage

drain current

measured

[seconds]

[A] [V]

• Simulated waveforms exhibit excessive ringing• AC resistance RAC not modeled

• measured RAC(@f = 23 MHz) > 33 Ω, which is >500x dc resistance• RAC is highly nonlinear, and practically unpredictable• simulation cannot achieve correct dc operating point using ac values

SWITCH TURN OFF TRANSITION OF MAIN SWITCH

simulated

≈ 23 MHz

LIMITATIONS

SWITCH TURN OFF TRANSITION OF MAIN SWITCH

drain-source voltage

drain current

measured

700nH clamp bead removedfrom simulation

• Simulated waveforms again exhibit excessive ringing• AC resistance RAC not modeled

• measured RAC(@f = 3 MHz) > 25 Ω, which is >400x dc resistance• RAC is highly nonlinear, and practically unpredictable• simulation cannot achieve correct dc operating point using ac values

[seconds]

[A] [V]

LIMITATIONS

≈ 3 MHz

simulated-3

-2

-1

0

1

2

3

4

5

6

7

0.E+00 1.E-07 2.E-07 3.E-07 4.E-07 5.E-07 6.E-07 7.E-07-300

-200

-100

0

100

200

300

400

500

600

700

0.00

200.00

400.00

-3.E-07 -1.E-07 1.E-07 3.E-07 5.E-07

-210

-100

10-3

-1

1

3

5

CLAMP INVESTIGATION

VCLslow

VCLfast

iCLfast

iCLslow

VDS

iCLslowiCLfast

VCLslowVCLfast

VDS

tA tB

tRR

IRM

dIFdt

IF

0

VRM

VR

0

-3

-1

1

3

5

-210

-100

10

0.00

200.00

400.00

-3.E-07 -1.E-07 1.E-07 3.E-07 5.E-07

CLAMP INVESTIGATION700nH clamp bead removed

VCLslow

VCLfast

iCLfast

iCLslow

VDS

iCLslowiCLfast

VCLslowVCLfast

VDS

• Reverse-recovery characteristics of clamp diodes not accurate

tA tB

tRR

IRM

dIFdt

IF

0

VRM

VR

0

• TA too short• TB nearly zero• manufacturers often do not

provide sufficient data to model reverse recovery phenomena

-100.00

0.00

100.00

200.00

300.00

400.00

-1.E-07 1.E-07 3.E-07 5.E-07-4

0

4

8

12

16

[V]

[seconds]

[V]

drain-source voltage

gate-source voltage

GATE DRIVE INVESTIGATIONLIMITATIONS

measured

-100.00

0.00

100.00

200.00

300.00

400.00

-1.E-07 1.E-07 3.E-07 5.E-07-4

0

4

8

12

16

GATE DRIVE INVESTIGATIONLIMITATIONS

[V]

[seconds]

[V]

• Simulation shows delay in switch turning off• gate drive parasitic impedance not accurately modeled• gate-drain capacitance may not be accurately modeled

• Measurement shows slight resonance in gate-source waveform, resulting in drain-source "pedestal", which is due to gate drive parasitics

drain-source voltage

simulatedmeasured

gate-source voltage

-400.00

-300.00

-200.00

-100.00

0.00

100.00

200.00

300.00

400.00

500.00

600.00

0.E+00 1.E-07 2.E-07 3.E-07 4.E-07 5.E-07 6.E-07 7.E-07

INSTANTANEOUS POWER AT SWITCHING TRANSITION

measured

[W]

[seconds]

LIMITATIONS

-400.00

-300.00

-200.00

-100.00

0.00

100.00

200.00

300.00

400.00

500.00

600.00

0.E+00 1.E-07 2.E-07 3.E-07 4.E-07 5.E-07 6.E-07 7.E-07

INSTANTANEOUS POWER AT SWITCHING TRANSITION

simulated

measured

[W]

[seconds]

• Poor matching of instantaneous power

700nH clamp bead removed in simulation

LIMITATIONS

MODELING AC RESISTANCELIMITATIONS

R1 L1

R2

L2

R3

L3

Rn

Ln

RC C

• AC resistance can be modeled by first measuring, and then curve fitting with a series of resistors, inductors and a capacitor

“Modeling of high frequency inductors”, L. Heinemann, R. Schulze, P. Wallmeier, and H. Grotstollen, PESC 1994

• A drawback to measurement based simulation is that hardware must be available before simulation can be accurate• once hardware is available,

simulation becomes less valuable since it is no longer a design tool and more a tool to facilitate understanding

• A point of diminishing returns exists when it takes longer to accurately simulate a circuit then it takes to build and test the hardware

ADDITIONAL LIMITATIONS OF SPICE-TYPE SIMULATORSLIMITATIONS

• A fast, accurate, and stable integration method is highly desirable

• Several integration methods are employed by Spice-based simulators• backwards Euler (equivalent to first order Gear)

• less accurate• trapezoidal

• accurate but converges in an oscillatory manner (triangular shaped oscillations)

• Gear (a.k.a. backward differentiation)• not accurate when simulating resonant phenomina because it introduces

numerical damping • used exclusively by PSPICE

INTEGRATION METHOD

V STEP 01 V C

C

L

1µH

253µF

• Example using simple LC circuit subjected to a step input voltage

LIMITATIONS

LIMITATION DUE TO GEAR INTEGRATION METHOD

0

0.4

0.8

1.2

1.6

0

0.4

0.8

1.2

1.6

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

0.4

0.8

1.2

1.6

RELTOL = 0.001(DEFAULT)

RELTOL = 0.0001(SLOWER

SIMULATION TIME)

RELTOL = 0.00001(SLOWEST

SIMULATION TIME)

• Gear integration method introduces numerical damping

• Damping factor decreases as relative voltage tolerance (RELTOL) decreases

• Simulation time increases significantly as RELTOL decreases

• Example

V STEP 01 V C

C

L

1µH

253µF time [msec]

VC [V]

LIMITATIONS

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

COMPARISON BETWEEN GEAR AND TRAPEZOIDAL INTEGRATION

GEAR

TRAPEZOIDAL

• Trapezoidal integration yields correct (i.e., undamped) solution

• PSPICE does not offer trapezoidal integration as an option

• Example

time [msec]

VC [V]

V STEP 01 V C

C

L

1µH

253µF

SUMMARY OF SUB-SWITCHING PERIOD SIMULATIONS

• Accurately modeling switching transition detail is impractical, and nearly impossible without measuring the hardware and curve fitting the model• discussed

• accuracy of diode models• modeling of AC resistance• importance of gate-drive impedance• inaccuracy due to simulator

• not discussed• accuracy and availability of switch model (e.g. MOSFET)• predicting parasitic inductances and capacitances which are highly dependent

on layout

• In a practical design cycle, very little time is permitted for such an intensive study

• Best design strategy mixes empirical data with practical simulation in order to meet the derating specifications and the project deadline

MERITSCIRCUIT DIAGRAM OF TWO-SWITCH FORWARD CONVERTER WITH CURRENT MODE CONTROL

• Hardware specifications• 410-V input• 12.3-V/600-W output• 200 kHz switching frequency

• SIMPLIS™ simulation• piecewise linear simulation of

closed loop switching model• ideal switching devices• most parasitics ignored• fast simulation time

• < 5 sec

V IN V O

CONTROL & ISOLATED DRIVE

i L

T V0

0

-75

-50

-25

0

25

50

75

0

0.175

0.35

0.525

0.7

-6

0

6

12

0 2 4 6 8 10time [µsec]

Gate Voltage

Ramp Voltage

Secondary Voltage

STEADY STATE WAVEFORM COMPARISONMERITS

Output Voltage

-6

0

6

12

0

0.175

0.35

0.525

0.7

-75

-50

-25

0

25

50

75

0 2 4 6 8 10time [µsec]

Gate Voltage

Ramp Voltage

Secondary Voltage

STEADY STATE WAVEFORM COMPARISON

• Gate drive matching is poor, but large signal parameters, such as duty cycle and switching period, match well

• ideal switches and diodes used• no effort made in modeling parasitics

• Ramp voltage shape is very similar• equal slopes

• slopes a result of current sensing circuit, and additional slope compensation

• Secondary winding voltage spikes and reset not modeled

MERITS

Output Voltage

MERITS

50

25

0

25

50

100

50

0

50

100

BODE PLOTS COMPARISON BETWEEN MEASUREMENTS AND SIMULATION

GAIN [dB]

PHASE [deg](+180o)

1 10 1000.1frequency [kHz]

• Voltage loop gain• excellent matching

• superior to average model• hardware measured and simulation

tuned to obtain such close matching

• Optimum design strategy is to choose placement of compensation poles and zeros based on established control theory to ensure stability and optimum performance over any operating range

• Simulation of loop gain provides validation of chosen component values prior to hardware build saving development time and money

• Simulation models can be shared with customers to facilitate understanding and to demonstrate functionality of a circuit

PM=80o

GM=14dB

MERITSLOAD STEP TRANSIENT COMPARISON BETWEEN MEASUREMENTS AND SIMULATION

time [µsec]

• Output current load step response• constant current sink featuring a 25%

load change at 2A/µsec

• Excellent matching between simulation and measurements

• slight difference in output voltage setpoint

• Accurate prediction of undershoot extremely difficult to obtain through analytical means

• Piecewise-linear simulation provides a simple, accurate means of obtaining large-signal behaviour prior to hardware build

11.9

12

12.1

12.2

12.3

12.4

OUTPUT VOLTAGEMEASUREMENT

35

40

45

50

55

0 50 100-50

SIMULATION

OUTPUT CURRENT

SUMMARY

• Simulation of sub-switching period phenomena, such as detailed switching transitions, is practically impossible

• Simulations of multiple switching period characteristics, such as small-signal loop gain and loop response to a step load change, can be very accurate

• Although many challenges still remain, simulation can be a valuable tool during the design cycle• validation of the loop design can be obtained prior to hardware build• models can be shared with customers to facilitate understanding and to

demonstrate functionality of a circuit