19 Nov 2014 1 SPP-FIELDS Antenna Electronics Board (AEB) CDR Peer Review J. W. Bonnell, D. N. Seitz Space Sciences Laboratory UC Berkeley

19 Nov 2014 1

SPP-FIELDS Antenna Electronics Board (AEB)

CDR Peer Review

J. W. Bonnell, D. N. SeitzSpace Sciences Laboratory

UC [email protected]@ssl.berkeley.edu

mailto:[email protected]

mailto:[email protected]

19 Nov 2014 2

Work Since PDR, Work To Be Done• Interim CogE split between is Bonnell and Seitz (Mar

2014, Heavner’s departure for ICON).• New staffing has tightened up collaboration with PA design

effort (Seitz, Bonnell, Goetz) and kept relevant interfaces (power, signal, noise) consistent and well-understood (work load is high, however).

• EM design, schematics, layouts finalized, reviewed, fabricated, assembled (1x AEB1; 2x AEB2), and functionally tested:– Bench and INT configs.– DC and AC sweeps at bench test level.– End-to-end analog input to digital output (Science and HSK).– Sensor bias control and readback (Science and HSK time series).– PA+AEB1+RFS-Analog (noise floor and power supply lines).

• Still to come before FM fabrication:– Thermal testing

• PA+AEB1 – noise, bandwidth, calibration changes.– TVAC testing

• MEP thermal tests to establish board ops temperature ranges.• Support of PA/V5 TVAC testing

– Final Parts approvals (MAX256, Single Event Transients)

19 Nov 2014

SPP FIELDS PA

3

19 Nov 2014

LF Section Details: Bootstrap

4

19 Nov 2014 5

LF Section Details: Biasing

19 Nov 2014 6

Scope of AEB Design Effort

• Antenna Electronics Board (AEB, see following block diagram slide)– Full AEB functionality split into two boards:

• AEB1 (V1, V2, V5) – primarily controlled by DCB.• AEB2 (V3, v4) – primarily controlled by TDS.

– FGND Driver:• 1 channel each for 4 forward whips (V1..4).• 1 channel for aft antenna (V5).

– Sensor bias current, Stub and Shield bias voltage drivers:• 3 channels of each for V1..4.• Sensor bias current and “Box” bias voltage driver for subset for aft whip or dipole.

– Sensor preamp bias range relay control:• 1 channel each for 4 forward whips (3 ranges). • one for V5.

– Floating Power Supplies:• 2 floaters to support opposing pairs of forward whips.• 1 floater to support aft whip or dipole (AEB1 only).

– V5 Preamp Power and Heater Control:• FSW-controlled floating power supply and pre-heater resistor.

– HF Output Stage Power Regulation:• +/- 6V from LVPS1/2 regulated down to +/- 5V for wide (4x) current consumption (signal

amplitude).– Passthrough of LF signal to DFB. – Serial Command and Data (HSK) I/F to DCB/TDS.

19 Nov 2014 7

AEB1 BLOCK DIAGRAM

LNPS 1

Preamp1 (PA1)

Preamp2 (PA2)

Preamp5 (PA5)

DCB

AEB±100V

AEB+12V

+3.3V Digital

PA±6V

300KHz SYNC

±5V PA_REGULATOR

+5V Analog

DAC CONTROL

MUXAEBHKSEL[3:0]

AEB1 AHKP

5VREF AD584 CHANNELS

AEBDAC_DATAEBDAC_CLK

AEBADR[3:0]

Decoder ENABLE

Latching Relay Controls

BIAS DACSTUB DACHEATSHIELD DAC

DAC HSK

HTR RES RELAY

BIAS RES RELAYS

BIAS RES RELAYS

FGND DRV

AEB 1 BLOCK DIAGRAM

±15V FLOATER

±15VF

FGND DRV

FGND DRV

FGND DRV

FGND DRV

FGND DRV

±15VF

±15VF

±15VF

AEB-12V

19 Nov 2014 8

AEB 2 BLOCK DIAGRAM

LNPS 2

Preamp3 (PA3)

Preamp4 (PA4)

TDS

AEB±100VAEB+12V

+3.3V Digital

PA±6V

300KHz SYNC

± 5V PA_REGULATOR

+5V Analog

DAC CONTROL

MUXAEBHKSEL[3:0]

AEB2 AHKP

5VREF AD584 CHANNELS

AEBDAC_DATAEBDAC_CLK

AEBADR[3:0]

Decoder ENABLE

Latching Relay Controls

BIAS DACSTUB DACHEATSHIELD DAC

DAC HSK

BIAS RES RELAYS

BIAS RES RELAYS

FGND DRV

±15V FLOATER

±15VF

FGND DRV

FGND DRV

FGND DRV

FGND DRV

±15VF

±15VF

AEB-12V

19 Nov 2014 9

AEB Requirements (stable since Dec 2012)

• Preamp signal characteristics – DC voltage level: ± 60Vdc w.r.t. AGND (± 60 Vdc at full bias offsets; up

to +/- 100Vdc at reduced bias current and voltage levels).– AC voltage level: ± 10V w.r.t. floating ground up to 70 kHz (± 13V

capability up to several 100 kHz)• Floating Ground Driver

– Input: LF Preamp signal– Input filter roll off: 500 Hz (~450 Hz actual, soft requirement due to

limited AC dynamic range).– Output voltage level: ± 60Vdc w.r.t. AGND– Floating supply rails: ± 15Vdc.

• Bias, Stub, Shield Drivers (Bias and Box on V5)– Reference Input: LF Preamp signal– Reference input filter roll off: 500 Hz (~450 Hz actual, match FGND)– Output voltage level: Vref ± 40Vdc (max, programmable) w.r.t. AGND– DAC resolution: 12-bit (~.025%).

• Noise voltages at Bias, Stub, and Shield outputs consistent with noise floor requirements, downstream filtering and processing, and predicted coupling to antenna (TBD).

19 Nov 2014 10

AEB Requirements, con’t.• Bias, Stub, Shield Drivers (Bias and Box on V5) – Output

Currents– Bias ranges (AEB+PA, V5 is lowest range only):

• +/- 802 nA (360 nA CBE @ 1 AU).• +/- 14 uA (0.25 AU).• +/- 414 uA (184 uA CBE @ 9 Rs).

– PA1..4 Stub and Shield Currents (max is photoelectron-dominated):• Stub: 60 nA (1 AU), 30 uA (9.5 Rs, nominally shadowed!).• Shield: 200 nA (1 AU), 100 uA (9.5 Rs).

– V5 Box Currents (nominally shadowed; max is photelectron-dominated):

• Box: ~40 nA (1 AU).

– Sunlit surfaces dominated by photoelectron and possibly thermionic electron emission, and so currents tend to be sinking of current from exposed surfaces (sourcing e- to surfaces consistent with sheath I-V curves).

19 Nov 2014 11

AEB 1 POWER BLOCK DIAGRAM

148µAx3

148µAx3

-12V

+12V(2.4-3.5mA)x3

+6V-6V

PREAMPHF OPAMP

V1+V2

+100V

-100V

AD648, AD584

AD648

+3.3VDDAC CONTROL

BIAS

STUB

HEATSHIELD

829µA

(2.4-3.5mA)x3

5.7mA

5.7mA

(25mA 10ms)x2Latching relays (AEB ICD)

Reg to 5V

Reg to 5V

100ms

LNPS 1

NOTES: 1. Ignore current estimates on this diagram – OBSOLETE.2. Delay is relative to turn on time of 5V Floater primary supply (next slide).3. +/- 12V, +/- 6V on same delay as +/- 100V.

19 Nov 2014 12

AEB 1 POWER FLOATING SUPPLY

FV1_P15VA

FV1_N15VA

FV1_GND

FV2_P15VA

FV2_N15VA

FV2_GND

FV5_P15VA

FV5_N15VA

4.5-6mA

V1-V2

V5

4.5-6mA

4.5-6mA

4mA

4mA

SYNC 300KHz

SYNC 300KHz

4.5-6mA

FLOATING GND DRIVER

and PREAMP

FLOATING GND DRIVER

and PREAMP

FLOATING GND DRIVER

and PREAMP

FV5_GND

+5VA

IMON

IMON

80mA

40mA

HSK MUX

From DCB

From DCB

19 Nov 2014 13

AEB 1 Coax Cable and Connector DIAGRAM

LNPS 1 TDS

AEB 1 Preamp1 (PA1)

Preamp2 (PA2)

Preamp5 (PA5)

RFSDCB

DFB

HFMF

MFHF

J32 J31J37 J36

J34

J38

J33

19 Nov 2014 14

• All LF HRN Shields tied to AGND rather than mix of AGND and FGND.• Regularized input and output timing constants for drivers (FGND, Bias,

Stub, Shield all to 450-Hz 3-dB frequency).• Replaced HSK MUX (failures of original in UMN EM units) and added 5-

to-3.3-V level shift transistors required for digital IF to DCB/TDS.• Addressed “0x000” startup state (FS negative) on bias DACs at DCB

level (AEB1/2 start up includes setting DACs to mid-scale, 0x7FF).• Changed floater transformer winding ratio to accommodate +/- 15-V PA

supply rails (legacy design was +/- 10-V).• Added 10-kohm series resistors on Floater SYNC inputs to prevent

“powered via SYNC” anomaly.• Added zeners and transistors to FGND input stage power supply to

meet derated max supply voltages on AD648 (to be implemented).• Defined all shield connections on PA1, 2, and 5 connectors and

harnesses.• Added current limit diodes to PA5 power supply relay outputs to protect

relay contacts from inrush/outrush currents.• Rewired PA5 power supply relay rails to ground rails to FGND via 100-

ohm instead of AGND to minimize DC potential difference across relay.

Changes to AEB EM During Design, Assembly, and Test

19 Nov 2014 15

Bench Testing - Setup

19 Nov 2014 16

Bench Testing – Power In (AEB1/SN002)

Supplies, max loads:Volts Amps

100 100.1 0.000-100 -99.7 0.000

12 12.00 0.008-12 -12.01 0.003

6 6.001 0.027-6 -5.999 0.0275 4.996 0.101

3.3 3.3 0.000PA1 +15F 13.720 0.006PA1 -15F 13.730 0.006

PA1 +5 4.627 0.013PA1 -5 4.598 0.013

PA2 +15F 13.67 0.006PA2-15F -13.67 0.006

PA2 +5 4.618 0.013PA2 -5 -4.613 0.013

All supply Amps quantities taken from bench supply displays

Amps calculated from Vout/Rload

Supplies, nom loads:Volts Amps

100 100.1 0.000-100 -99.7 0.000

12 12.00 0.008-12 -12.01 0.003

6 6.001 0.012-6 -6.000 0.0125 4.998 0.083

3.3 3.3 0.000PA1 +15F 14.300 0.004PA1 -15F -14.300 0.004

PA1 +5 4.721 0.006PA1 -5 -4.703 0.006

PA2 +15F 14.7 0.004PA2-15F -14.7 0.004

PA2 +5 4.722 0.005PA2 -5 -4.724 0.005

All supply Amps quantities taken from bench supply displays

Amps calculated from Vout/Rload

19 Nov 2014 17

Bench Testing – Floaters (AEB1/SN002)

9/10/2014 Summary of power supply performance

MAXIMUM loads = 2.5k, +5V in at MINIMUM:PA1 +15 PA1 -15 PA2 +15 PA2 -15 PA5 +15 PA5 -15 Lowest Vout: *Requirement Pass?

14.67 -14.67 14.48 -14.49 14.28 -14.28 Volts, measured at loads 14.28 13 YES0.0059 -0.0059 0.0058 -0.0058 0.0057 -0.0057 Amps (calculated for 2.5k loads)

R152 R154 R217 R219 R264 R266 AEB 10Ω sense resistor designator0.0173 -0.0173 0.0168 -0.0168 0.0169 -0.0169 AEB 10Ω sense V measured across resistor0.0017 -0.0017 0.0017 -0.0017 0.0017 -0.0017 AEB 10Ω sense I calculated0.1115 0.1115 0.1082 0.1083 0.1057 0.1057 Watts calculated

5V in: 5V current: Pin Pout Pout/Pin4.750 0.1495 0.710 0.545 77% EFFICIENCY MEASURED VIN AT AEB R7/R3 JUNCTION; SERIES FLUKE 85DMM MEASURING CURRENT

NOMINAL loads = 2.5k, +5V in at NOMINAL:PA1 +15 PA1 -15 PA2 +15 PA2 -15 PA5 +15 PA5 -15

16.13 -16.15 15.72 -15.72 15.78 -15.79 Volts, measured at loads0.0042 -0.0042 0.0041 -0.0041 0.0041 -0.0041 Amps (calculated for 3.83k loads)



MINIMUM loads = open, +5V in at MAXIMUM:PA1 +15 PA1 -15 PA2 +15 PA2 -15 PA5 +15 PA5 -15 Highest Vout: **Requirement Pass?

17.03 -17.17 17.12 -17.14 17.1 -17.16 Volts, measured at L1, L4, L6 outputs 17.17 17.6 YES0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 Amps (zero, no loads)



*Minimum voltage requirement calculated by applying minimum output swing from OP15 SMD 5962-89542 to 10V FIELDS LF output requirement.** Maximum voltage requirement calculated by applying EEE-INST-002 linear IC derating factor of 0.8 to absolute maximum supply voltage from OP15 SMD 5962-89542.

AEB +/-15F Performance

19 Nov 2014 18

Bench Testing – +/5V Regs (AEB1/SN002)

Iout measured across 100Ω resistor in series with 10kΩ potentiometerAEB +6in AEB -6 in V100Ω + V 100Ω - I out + I out - Requirement Pass?

5.702 -5.699 1.403 -1.404 0.0140 -0.0140 4.300 -4.316 *** 4.29 YES6.002 -5.998 0.906 -0.907 0.0091 -0.0091 4.640 -4.653 typical case: use 6Vin, 9mA load6.302 -6.299 0.4006 -0.4003 0.0040 -0.0040 4.992 -5.002 **** 5.08 YES 5mA for AD8001

leaves 4mA for output loadIout measured across 100Ω resistor in series with 10kΩ potentiometer output load resistance = 100Ω||237Ω+79Ω = 76Ω

AEB +6in AEB -6 in V100Ω + V 100Ω - I out + I out - Requirement Pass? 4mA * 76Ω = 304mV DC equivalent Vout5.702 -5.699 1.405 -1.404 0.0141 -0.0140 4.305 -4.315 *** 4.29 YES6.002 -5.998 0.901 -0.901 0.0090 -0.0090 4.647 4.6546.302 -6.299 0.401 -0.4 0.0040 -0.0040 4.996 -5.002 **** 5.08 YES

*** Minimum requirement based on Type III event amplitude at PA output and AD8001 SMD 5962-94593 minimum output swing for 100Ω load. Assuming PA gain = 5 and 10 ohm supply resistors on AD8001:TypeIII = 3.5Vpp = 1.75Vp Max swing with +/-5 and 100Ω load = +/-2.6V, so max swing = Vsupply-2.4 14mA IR drop = 140mV Min Vsupply = 1.75+2.4+0.14 = 4.29V

**** Maximum requirement derived by applying EEE-INST-002 linera IC derating factor of 0.8 to AD8001 SMD 5962-94593 absolute max rating of +/-6.3 and also accounting for 4mA IR drop in 10 ohm supply resistors on AD8001:6.3 x0.8 = 5.04 10Ω IR drop = 40mV Max Vin = 5.04+0.04=5.08V

+ PA1 Vout -

+ PA1 Vout -

PA1

PA2

AEB +/-5V regulator performance

19 Nov 2014 19

Bench Testing – AC Response (AEB1/SN002, V5)

3-dB

19 Nov 2014 20

Bench Testing – DC Response (AEB1/SN002, PA1)

19 Nov 2014 21

Bench Testing – DC Response, con’t (AEB1/SN002, PA1)

Residuals correspond to < 1nA at lowest IBIAS range – AOK.

19 Nov 2014 22

I&T Testing – Setup(PA+AEB1+DCB+DFB+LNPS1, 31 Oct

2014)

• Safe-to-Mate.• Power Consumption – as expected.• LF/MF/HF response check (crude, LF and

MF termination off-nominal).• PA/AEB Bias ranging and setting (HSK

and Science readback) – as expected.

19 Nov 2014 23

BACKUP SLIDES

19 Nov 2014 24

AEB 2 Coax Cable and Connector Diagram

LNPS 2 TDS

AEB 2 Preamp3 (PA3)

Preamp4 (PA4)

RFSTDS

DFB

HFMF

MF

HF

J52 J51J57 J56

J54

J58

J53

19 Nov 2014 25

AEB 2 POWER BLOCK DIAGRAM

148µAx2

148µAx2

-12V

+12V(2.4-3.5mA)x2

+6V-6V

PREAMPHF OPAMP

V3+V4

+100V

-100V

AD648, AD584

AD648

+3.3VDDAC CONTROL

829µA

(2.4-3.5mA)x2

5.7mA

5.7mA

(25mA 10ms)x2 Latching Relays (AEB ICD)

Reg to 5V

Reg to 5V

BIAS

STUB

HEATSHIELD

LNPS 2

100ms

19 Nov 2014 26

AEB 2 POWER FLOATING SUPPLY

FV1_P15VA

FV1_N15VA

FV1_GND

FV2_P15VA

FV2_N15VA

FV2_GND

4.5-6mA

V3-V4

4.5-6mA

4.5-6mASYNC 300KHz

4.5-6mA

FLOATING GND DRIVER

and PREAMP

FLOATING GND DRIVER

and PREAMP

IMON80mA

HSK MUX

+5VA

From TDS

19 Nov 2014 27

PARTS

• PARTS – All parts conditionally approved by Parts Control Board (Nov

2014).– Single-Event Transient (SET) effects analysis on MAX256 to be

completed (by I-CDR; no obvious impact from infrequent short transients).

19 Nov 2014 28

I-PDR Peer Review Items (24 Oct 2013)

Description Originator Type Response

Put a relay on AEB to turn on and off the heater. See if RC filtering is necessary and look into +/- supply instead of single supply to see if that will reduce possible EMI.

K. Hatch (SSL) Advisory Independent relays for V5 PWR and HTR control added; both feed off of floating +/- 15V V5 supply; no additional EMI filters added at this time.

Add “on box bias on V5” on chart, level 4 requirement update

J. Hoberman (SSL) Advisory To be updated by I-PDR.

Remove LF coax requirement from AEB and Redo coax diagram

J. Hoberman (SSL) Advisory Done; also requirement for all on-PCB coax runs removed.

19 Nov 2014 29

I-PDR Peer Review Items, con’t (24 Oct 2013)

Description Originator Type Response

What happens to the output when the sync is removed from AEP? Is it a smooth transition? Test and document.

P. Berg (SSL) Advisory Question raised in I-PDR as well; removal of SYNC disabled MAX256 in Floater supplies; after discusion of risks, MODE drive set to LOW to force external-clock-only operation in EM.

Test DAC turn on characteristics when connected to preamp box. What happens when the DAC comes on at 0 volts instead of mid-scale?

J. Hoberman (SSL) Advisory Done at bench test level – no obvious issues. Will check at INT level as well.

Concern about incomplete analysis of the output stage of the floater circuit (Q19, Q20)

K. Hatch (SSL) Advisory No further analysis done at this time for legacy design; EM implementation works as expected.

19 Nov 2014

HF Section Details: Input Coupling

30

19 Nov 2014

AEB – FGND Bandwidth and LF Dyn Range

AEB-31

The FGND bandwidth needs to be higher than one expects to allow for low-distortion

measurement of large-amplitude LF fields.

• The top panel shows a 120-Vpp 100-Hz signal (solid black line) and the response of the Floating Ground Driver (FGND, green dashed) and positive and negative Preamp Floating Supply Rails (red and blue dash-dot).

• This example is consistent with the initial RBSP-EFW-BEB FGND design and the OP-15 used in the EFW PRE circuit (~2-V headroom on pos and neg supplies to give harmonic amplitudes < -40dB relative to fundamental).

• The FGND is a one-pole RC low-pass filtered version of the input signal, with corner (3-dB) frequency of 300 Hz (three times the input signal!).

• The region between the red and blue lines at any give time indicates the range of signal input voltages that will be faithfully reproduced.

• When the voltage margin on the pos or neg rail goes negative, the output will be distorted by clipping.

19 Nov 2014

AEB – LF->HF Dynamic Range

AEB-32

The dynamic range (maximum amplitude signal measured meeting maximum distortion requirements) varies with input frequency:

• At very low frequencies, the dynamic range is set by the AEB HV output stage rails.• At frequencies well above the FGND rolloff, the dynamic range is set by the PRE floating supply rails

and the headroom the preamp requires on those rails.• At intermediate frequencies, the dynamic range falls off remarkably fast as the rolloff frequency of

the FGND is approached.

450 Vpp(± 225 V,~100 V/m),BUT…

26 Vpp(± 13 V,~7 V/m)

At FGND 3-dB Frequency500 Hz:36 Vpp (± 18 V, ~9 V/m)

Frequency

Max

imiu

m A

mpl

itude

19 Nov 2014

AEB – LF Response At Different Frequencies

AEB-33

• Examples using Flight RBSP-EFW AEB and PRE floating supply designs (500-Hz FGND bandwidth).

• Left plot is threshold case for 100-Hz input frequency (65 V amplitude [130 Vpp]).• Right plot is threshold case for 500-Hz input frequency (18 V amplitude [36 Vpp]).

19 Nov 2014

AEB – LF->HF Dynamic Range

AEB-34

19 Nov 2014

AEB –Biasing Reduces LF Dynamic Range

AEB-35

V_BIAS, V_GUARD, V_STUB, etc.(up to ± 40 V; typ. ≤ ± 20 V).

• The full HV rail-to-rail voltage is not available to the signal at low frequencies if current and voltage biasing is active and one wants stable DC current and voltage biasing.

• For typical conditions and designs (current biasing to half possible range, +/- 40 V offset system), this eats up another 20 V or so of the dynamic range in a conservative (worst-case) design.

• Similarly, any stable SC potential offset (SC floating potential, VSC) eats up part of the LF dynamic range (few to tens of volts) in a conservative (worst-case) design. Large values of VSC are typically driven by biasing, but will also be driven on SPP by the space charge in the SC wake.

Documents

19 Nov 2014 1 SPP-FIELDS Antenna Electronics Board (AEB) CDR Peer Review J. W. Bonnell, D. N. Seitz Space Sciences Laboratory UC Berkeley