MemoryTri-State BufferBusRegister FilesMemory

Scratch Pad Register RAM Operation Non-Volatile Memory (ROM) PROM EPROMEEPROM

Tri-State Buffer

In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic level, effectively removing the output from the circuit.

In active high control, if C=1, Y=X and In active low control, if C=0, then C=0, Y is isolated from X. Y=X and when C=1, Y is isolated from X.

Multiplexer a) Using Basic Gates b) Using TSBTri-State Buffer (TSB) - Application

Bus

Set of n signal lines (conducting wires) used together to carry signal corresponding to address or control or data or program (code) is known as BUS.

Fig (1)General diagram to show DATA, Address and Control BusFig (2) PIC 16F877A - Program and Data Memory to show DATA, Address and Program Memory Bus

Register Files

A set of registers arranged in an orderly manner is called a register file.

Types: Serial Data is loaded one behind the other and read in the similar manner

Parallel The register to which the data to be transferred is directly accessed.

First In First Out (FIFO) Register file

FIFO

InputOutput

Reg Add.Content before first clockI/PByte 0A0A1A2A3O/P

Content after first clockByte 1Byte 0

Content after second clockByte 2Byte 1Byte 0

Content after third clockByte 3Byte 2Byte 1Byte 0

Content after fourth clockByte 4Byte 3Byte 2Byte 1Byte 0

Content after fifth clockByte 5Byte 4Byte 3Byte 2Byte 1Byte 0

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Last In First Out (LIFO) Register file

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Memory Parallel Register FileA parallel register file is more widely known as a memory.

Classified based on 1. Hardware.

2. Size.3. Function.

Generally an RS flip-flop is used as basic memory cell 1 bit read/write. Scratch Pad Register (Read/Write)

4-Byte RAM Register File

M-Byte RAM Register FileNumber of registers :M = 2n Where n is number of address lines.

RAM Read operation

RAM Write operation

RAM - TypesDRAM

SRAM

ROM - TypesPROM

EPROM

EEPROM

Example of PROM

Microcontroller V/S Microprocessor Harvard Von NeumannRISCCISC

Harvard v/s von Neumann Block Architectures

PIC Microcontroller 16F877A.

16F877A Block - Diagram

DATA TRANSFER UNITA set of functional elements linked together to facilitate a variety of data transfer is called Data Transfer Unit (DTU).

RE Read EnableWE Write EnableRCLK RAM write ClockRAWE RAM Address Write EnableRAMACLK RAM Address Clock WR Working register ReadWW Working register WriteWCLK - Working register Write ClockOWE Output Write EnableOE Output EnableOCLK Output ClockIE Input EnableICLK Input Clock

RAM file registers

RAM address decoder

RAM address register

Working register

Output register

Input register

OE

Output

Input

OCLK

IE

ICLK

RCLK

RAMACLK

WCLK

RE

WE

RAWE

WW

WR

Data bus

OWE

Memory address

RAM file registers

RAM address decoder

RAM address register

Working register

Output register

Input register

OE

Output

Input

OCLK

IE

ICLK

RCLK

RAMACLK

WCLK

RE

WE

RAWE

WW

WR

Data bus

OWE

Memory address

RAM File Registers RCLKRAMACLKRAWEMemory Address (9) REWE

RAM File Registers Write OperationRCLKRAMACLKRAWEMemory Address (9)

WEData

RAM File Registers Read OperationRAMACLKRAWEMemory Address (9) REData

Input Port InputICLK Data Bus IE

Output PortData BusOCLK OutputOWE OE

Working Register Data BusWCLK OutputWW WR

Input

Working Register - Write Data BusWCLKWW

Input

Working Register - Read Output WR

Data Bus

DTU Operation and Clock GenerationThe DTU as a whole has 13 control signals. Five of these are clock signals used to load data into the respective registers.These can be generated from a single clock signal as shown below.

CLK

WE

RAWE

WW

OWE

IE

RCLK

RAMACLK

WCLK

OCLK

ICLK

DTU Operations

Status of control linesSl.No.RAWEREWEIEOWEWWWRActivity010001010Transfer data from input port to working register021000000Write address into RAM address register (get ready to select an address location in the register file)030010001Transfer data from working register into the selected RAM location040000101Transfer data from working register to the output port050100010Transfer data from selected RAM location into the working register060100100Transfer data from selected RAM location into the output port070011000Transfer data from input port to the selected RAM location

Enhanced DTU

Enhanced DTU With addition of ALU

Opcode and Program

Program -A set of instructions for a computer to perform a specific task.An instruction set, or command set, is the basic set of commands understood by the microcontroller. Instruction set is unique for a microcontroller.Instruction consists of a mnemonic a keyword and data / address ( In some cases only mnemonic).

- movlw 0x76 movlw - keyword, 0x76 data - movwf 0x24 movwf - keyword, 0x24 - addr- Clrw Only key wordFor each keyword we have a unique binary bit pattern known as Opcode Operation Code

Program ExecutionOnce an instruction sequence (program) is prepared and loaded into the PM, the EDTU is ready for operation: The operational sequence is as follows:PC is initialized and points to the location where the first instruction to be executed is storedThe instruction is fetched and loaded into the instruction register; this constitutes the fetch cycle phase of instruction execution

Program Execution (Contd)The instruction in the instruction register is decoded by the instruction decoder and executed; this constitutes the execution phase of instruction execution.PC is incremented. The instruction fetch operation during fetch cycle and execute operation during execute cycle are carried out for the second instruction.The PC is again incremented, the third instruction fetched and executed and so on.

Program Execution (Contd)The instruction fetch and execute cycles together is called a Machine Cycle. Thus program execution is a sequence of machine cycles carried out as desired. Process continues till the last instruction of the program.

Processor operation timing and sequence

Processor operation timing and sequence

The clock has 4 phases designated 1, 2, 3 and 4. Four successive clock pulses together represent an interval in which an instruction can be fetched or executed. It is called the instruction cycle.As such a machine cycle fetch and execute operations together lasts for 2 instruction cycles or 8 clock periods. Parallel processing takes place Hence while executing ith instruction (i+1)th instruction can be fetched. ( Harvard Architecture )

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