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AT1013 Super Low Noise FET in DFN PKG 1 / 6 Features Low noise figure and high associated gain NF=0.5dB TYP., Ga=12.8dB TYP. @VDS=2V, ID=11mA, f=12GHz Applications DBS LNB 2nd/3rd gain-stage, Mix-stage Low noise amplifier for microwave communication system Description Excellent Low Noise. High Associated Gain. Small package size. Super Low Cost. Package Dual Flat No-lead 4-pin package Figure 1 is pakcage view Figure 1 Package view of AT1013 Below table is the PIN definition and function for AT1013. AT1013 Pin Definition and Function Pin NO. Pin Name Function Note 1 Drain Supply Drain to Source Voltage and RF output Positive voltage is suggested 2 Source Connect to GND 3 Gate Supply Gate to Source Voltage and RF input Negative voltage is suggested 4 Source Connect to GND 5 N/A N/A Not connect Note: According to the bottom view in Figure 1, there is a semi-circular notch in PIN 5, the semi-circle pointing direction is PIN1. 1 2 3 4 1 2 3 4 5 Top view Bottom view

2 3 Dual Flat No-lead 4-pin package 3 2 5 4 1 Top view Bottom vie · 2020. 9. 1. · Dual Flat No-lead 4-pin package Figure 1 is pakcage view 1 Figure 1 Package view of AT1013 Below

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  • AT1013 Super Low Noise FET in DFN PKG

    1 / 6

    Features:

    Low noise figure and high associated gain

    NF=0.5dB TYP., Ga=12.8dB TYP.

    @VDS=2V, ID=11mA, f=12GHz

    Applications:

    DBS LNB 2nd/3rd gain-stage, Mix-stage

    Low noise amplifier for microwave

    communication system

    Description:

    Excellent Low Noise.

    High Associated Gain.

    Small package size.

    Super Low Cost.

    Package:

    Dual Flat No-lead 4-pin package

    Figure 1 is pakcage view

    Figure 1 Package view of AT1013

    Below table is the PIN definition and function for AT1013.

    AT1013 Pin Definition and Function

    Pin NO. Pin Name Function Note

    1 Drain Supply Drain to Source Voltage and RF output Positive voltage is suggested

    2 Source Connect to GND

    3 Gate Supply Gate to Source Voltage and RF input Negative voltage is suggested

    4 Source Connect to GND

    5 N/A N/A Not connect

    Note: According to the bottom view in Figure 1, there is a semi-circular notch in PIN 5, the semi-circle pointing direction is PIN1.

    1

    23

    41

    2 3

    4

    5

    Top view Bottom view

  • AT1013 Super Low Noise FET in DFN

    PKG

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    Absolute Maximum Ratings:

    Parameter Symbol Rating Unit

    Drain to Source Voltage VDS 4 V

    Gate to Source Voltage VGS -2.4 V

    Drain Current ID 30 mA

    Gate Current IG 80 μA

    Total Power Dissipation Ptot 125 mW

    Channel Temperature Tch 150 ℃

    Storage Temperature Tstg -55 to +125 ℃

    Operation temperature Top -20 to +105 ℃

    Attention: Stresses exceeding the max. values may cause permanent damage to the device.

    Recommended Operating Range:

    (TA=+25℃, unless otherwise specified)

    Parameter Symbol MIN. TYP. MAX. Unit

    Drain to Source Voltage VDS +1.2 +2 +2.8 V

    Drain Current

    (ID constant circuit) ID 8 11 16 mA

    Electrical Characteristics:

    (TA=+25℃, unless otherwise specified)

    Parameter Symbol Condition MIN. TYP. MAX. Unit

    Gate to Source Leak Current IGSO VGS=-3.0V - 0.45 10.0 μA

    Saturated Drain Current IDSS VDS=2V, VGS=0V 42.0 65.0 mA

    Gate to Source Cut-off Voltage VGS(off) VDS=2V, ID=100μA -1.0 -0.72 V

    Transconductance Gm VDS=2V, ID=10mA 54.0 66.0 - mS

    Noise Figure NF VDS=2V, ID=10mA,

    f=12GHz

    - 0.5 dB

    Associated Gain Ga 10.8 12.8 - dB

  • AT1013 Super Low Noise FET in DFN PKG

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    Reference Schematic

    Layout

    Layout for DFN

    PKG only

    Red line area is the PCB

    land pattern to PIN2PIN

    the PKG of Flat-lead 4-pin

  • AT1013 Super Low Noise FET in DFN PKG

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    TYPICAL CHARACTERISTICS:

    (TA=+25℃, unless otherwise specified)

    DRAIN CURRENT vs.

    GATE TO SOURCE VOLTAGE

    MIMIMUM NOISE FIGURE &

    ASSOCIATED GAIN vs. FREQUENCY

    DRAIN CURRENT vs.

    DRAIN TO SOURCE VOLTAGE

    S-PARAMETERS vs. FREQUEN

    0

    10

    20

    30

    40

    50

    -0.8 -0.6 -0.4 -0.2 0

    I_D

    S(m

    A)

    V_GS(V)

    0

    10

    20

    30

    40

    50

    60

    0 1 2 3 4 I_

    DS(

    mA

    ) V_DS(V)

    V_GS=0 V V_GS=-0.2 V

    V_GS=-0.4 V V_GS=-0.6 V

  • AT1013 Super Low Noise FET in DFN

    PKG

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    OPTIMAL NOISE PARAMETER

    Package Dimensions:

  • AT1013 Super Low Noise FET in DFN

    PKG

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    AT1013

    Super Low Noise FET

    In DFN PKG

    For more information, please contact us.

    Airtouching Intelligence Technology (Shanghai) Co., Ltd

    Website: www.airtouching.com

    Mailbox: [email protected]

    http://www.airtouching.com/mailto:[email protected]