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Lesson 03:Multiprocessor System Interconnects─
Hierarchical Bus and Time Shared bus Systems and multi-port memory
Chapter 12: Multiprocessor Architectures
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Objective
• To understand multiprocessor system interconnects using system, hierarchal and time shared buses
• Use of SEND and RECEIVE functions and multiport memories
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Fast System-Bus based Inter-communication Network for
Sequential and Parallel Processors
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Simple Interconnection network between multiprocessors
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
5
Simplest single network using a system-bus interconnection
• A contention problem when more than one processor seeks bus access at the same time
• Specialized design can solve the contention issue to large extent
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Hierarchical Bus Systems forSequential and Parallel Processors
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Hierarchical Tree-like Design of the Processing Nodes with each Node having two dedicated interprocessor Buses
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
8
Buses in a hierarchical tree-like design of multiprocessors
• A root processor with two or more dedicated buses at each node
• Each node─ an independent processor and memory
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Buses in a hierarchical tree-like design of multiprocessors
• Hierarchical design with two independent processing node buses
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
10
Buses in a hierarchical tree-like design of multiprocessors
• Communication─ by message-passing• Each processor node executes a RECEIVE
(buffer) operation, wait till SEND not completed• The sending processor executes its matching
SEND (data, destination) operation before the RECEIVE operation executes
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
11
Buses in a hierarchical tree-like design of multiprocessors
• RECEIVE─ a wait operation for taking message when a processor node A raises the need to receive data
• SEND ─ message post operation by other processor node B presently using the bus
• The processor A gets the needed bus for receiving the data after the SEND
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
12
Time shared Bus Systems forSequential and Parallel Processors
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Time shared Bus Design of the Processing Nodes- PCI Bus Example
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Example of Time-shared System Bus
• System bus shares the time slots between Processors, Input-OutputProcessors (IOPs) and Connects to PCI Bus for I/O Devices
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Use of Multiport Memories for Interconnections of simultaneous accesses
by multiprocessor memories
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Multiport Memory
• A multi port memory has the cells in which there are two or more ports where write can be made to one, while two or more ports can be simultaneously addressed and read
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Multiport memory network
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Multiport memory
• Supports simultaneous access, sometimes across different bus widths and voltages
• When it imposes no delay on either port during a read or write operation, then its maximum performance exceeds the traditional multiplexed SRAMs by a factor of at least two
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Use of Synchronization mechanism in hardware in multi-port port memory
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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A hardware synchronization mechanism
• Solves the simultaneous access for read and writes to the same port
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
21
New synchronous dual-port memories
• Collision detection logic support• Speeds up to 200 MHz• Bandwidth up to 1.75GB/s achieved for the
multiprocessor systems
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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Summary
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
23
• Simple system bus interconnect network• Hierarchical Tree like bus interconnect
network • Time shared bus structure• Use of RECEIVE and SEND functions for
message passing from one processor to another• Use of multiport memories for simultaneous
accesses to the memory in a multiprocessor system
We Learnt
Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009
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End of Lesson 03 on Multiprocessor System Interconnects─Hierarchical Bus and Time Shared bus
Systems and multi-port memory
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