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2002/06/11 Rational You p.3 SOI CMOS FET (a) Fully Depleted SOI (b) Partially Depleted SOI (PD SOI) (c) Double Gate/Back Gate CMOS Source: (2002/05)http://www.materialsnet.com.tw
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p.1
[email protected]; 2002/06/11Rational You
Non-Classical CMOS
Dr. Rational YouIEK/ITRI
2002/07/11
Source: http://www.materialsnet.com.tw (2002/05)
p.2
[email protected]; 2002/06/11Rational You Outline
• SOI CMOS FET• Double Gate MOSFET• 3 Double Gate MOSFETs• DG-MOSFET-Type 1 (Planar Device)• DG-MOSFET-Type 2 (Vertical Device) • Processes of DG-MOSFET-Type 2 (Vertical Device)• Processes of FinFET• 3D Structure of FinFET• 3D Structure of Strain MOSFET• Mobility of Strain MOSFET (Improve 70%)
Source: http://www.materialsnet.com.tw (2002/05)
p.3
[email protected]; 2002/06/11Rational You SOI CMOS FET
(a) Fully Depleted SOI (b) Partially Depleted SOI (PD SOI) (c) Double Gate/Back Gate CMOS
Source: http://www.materialsnet.com.tw (2002/05)
p.4
[email protected]; 2002/06/11Rational You Double Gate MOSFET
(a) Bulk MOSFET(b) Ultra-Thin Body MOSFET(c) Double Gate MOSFET
Source: http://www.materialsnet.com.tw (2002/05)
p.5
[email protected]; 2002/06/11Rational You 3 Double Gate MOSFETs
Source: http://www.materialsnet.com.tw (2002/05)
p.6
[email protected]; 2002/06/11Rational You DG-MOSFET-Type 1 (Planar Device)
Source:Wong, Chan, Taur (IEDM, 1997); http://www.materialsnet.com.tw (2002/05)
p.7
[email protected]; 2002/06/11Rational You DG-MOSFET-Type 2 (Vertical Device)
Source: http://www.materialsnet.com.tw (2002/05)
p.8
[email protected]; 2002/06/11Rational YouProcesses of DG-MOSFET-Type 2 (Vertical Device)-1
Source: http://www.materialsnet.com.tw (2002/05)
(1) Implant Channel (2) Deposit Stack (3) Etch Trench & Form Recesses
(4) Grow Channel (5) Planarize & Implant Channel
(6) Dep. Poly Drain Pad & Nitride
p.9
[email protected]; 2002/06/11Rational YouProcesses of DG-MOSFET-Type 2 (Vertical Device)-2
Source: http://www.materialsnet.com.tw (2002/05)
(7) SSD RTA & Pattern Pad (8) Deposit Nitride Spacer (9) Etch Spacer
(10) Remove Sacrificial Gate
Layer (11) Grow Gate Oxide &
Deposit Gate (12) Pattern Gate & Activate
p.10
[email protected]; 2002/06/11Rational You Processes of FinFET (i)
Source: http://www.materialsnet.com.tw (2002/05)
(1) After Depositing Si3N4 and SiO2 Hard Mask, Si Fin is Formed by Etching
(2) Phosphorus-doped-poly Si and SiO2 Stacked Layer Deposited
(3) Source and Drain Were Etched While Si Fin is Protected by the Hard Mask
p.11
[email protected]; 2002/06/11Rational You Processes of FinFET (ii)
Source: http://www.materialsnet.com.tw (2002/05)
(3) Source and Drain Were Etched While Si Fin is Protected by the Hard Mask
(4) SiO2 Spacers are Formed
(5) After Depositing B-doped SiGe, Gate Pattern was Delincated
p.12
[email protected]; 2002/06/11Rational You 3D Structure of FinFET
Source: Hisamoto et al., IEDM (1998); Huang et al., IEDM (1999); http://www.materialsnet.com.tw (2002/05)
p.13
[email protected]; 2002/06/11Rational You 3D Structure of Strain MOSFET
Source: http://www.materialsnet.com.tw (2002/05)
p.14
[email protected]; 2002/06/11Rational YouMobility of Strain MOSFET (Improve 70%)
Source: http://www.materialsnet.com.tw (2002/05)
p.15
[email protected]; 2002/06/11Rational You Reference
1. International Technology Roadmap for Semiconductor, SIA,20012. G. Moore, IEDM, 11(1975)3. H.-S. P. Wong, ESSDERC,412(2001)4. Y. Taur, et al., Fundamental of Modern VLSI Devices, Cambridg
e(1998)5. J. Hutchby, ITRS Presentation, 20016. H.-S. Wong et al., IEDM, 427(1997)7. S-H Oh et al., IEDM ,65 (2000)8. D. Hisamoto et al., IEEE T-ED, 47, 2320 (2000)9. X. Huang et al.,IEDM,67(1999)10. K. Rim et al., Symp. VLSI Technology, 59 (2001)
Source: http://www.materialsnet.com.tw (2002/05)
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