20050408 Coding Style - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_93second/2005ppt/20050408... · 2010. 7. 14. · nLint vnLintis a design rule checker that can help hardware

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Coding StyleCoding Style

Lecturer: Wein Tsung Shen (沈文中)Date: 2005.04.08


pp. 2Coding Style 2005.04.08

Principles of RTL Coding StylesPrinciples of RTL Coding StylesvReadabilityvSimplicityvLocalityvPortabilityvReusabilityvReconfigurability



Naming ConventionsNaming Conventionsv Lowercase letters for signal namesv Uppercase letters for constantsv Case-insensitive namingv Use clk for clocks, rst for resetsv Suffixesv _n for active-lowv _a for asyncv _z for tri-state

v Identical names for connected signals and portsv Do not use HDL reserved wordsv Consistency within group, division and corporation



File HeaderFile HeadervShould be included for all source filesvContentsvAuthor informationvRevision historyvPurpose descriptionvAvailable parametersvReset scheme and clock domainvCritical timing and asynchronous interfacevTest structures

vA corporation-wide standard template



Example: ALU.vExample: ALU.v



PortsPortsvOrderingvOne port per line with appropriate commentsvOutputs first then inputsvClocks, resets, enables, other controls, address

bus then data busvInstantiating MappingvUsing named mapping instead of positional

mapping



PrePre--RTL Preparation ChecklistRTL Preparation ChecklistvCommunicate design issues with your teamvNaming conventions, revision control, directory

trees and other design organizations.vHave a specification for your design?vTake it for granted that everyone has a

specification BEFORE they start coding.vDesign partitionvFollow the specification’s recommendations for

partition.vBreak the design into major functional blocks.



PrePre--RTL Preparation ChecklistRTL Preparation ChecklistvWork from the outside: I/O interfacesvMake sure the function and timing of each

interface is clear.vHow are the buses defined?vTry to use unidirectional buses wherever possible.

vAre there any compatibility requirements?vGet the tester’s specification and understand how

the chip is supposed to behave.vWhat other IP are you using?vStart with the interface to each IP block.



RTL Coding StyleRTL Coding StylevCreate a block level drawing of your design

before you begin coding.vDraw a block diagram of the functions and sub-

functions of your design.vAlways think of the poor guy who has to read

your RTL code.vCorrelate “top to bottom” in the RTL description

with ”left to right” in the block diagram.vComments and headers.

vHierarchical design



Comments and FormatsComments and Formatsv Appropriate commentsv Process (always block), function, …

v Comment end statementsv One statement per linev Coding in a tabular mannerv Line length restrictionv A fixed number between 72-78

v Indentationv 2 or 4v do not use tab



Coding PracticesCoding PracticesvLittle-endian for multi-bit busv[31:0] instead [0:31]

vOperand sizes should matchvreg [32:0] a; a = 33’h1_ffff_ffff;

a = 1; // a is 33’h1_0000_0001vUse parentheses () in complex statementsvDo not assign signals don’t-care valuesvAvoid don’t-care propagation

vReset all storage elementsvAvoid don’t-care propagation



Coding PracticesCoding PracticesvUse high level constructs (case, if, always@)

as much as possible.vDC takes Boolean expressions and gate level

instantiations and replaces them with a sum-of-products “pla”-like internal description that is fed to the gate level mapping optimization.

vDon’t instantiate gates unless you have to; make the code technology independent.vPut a wrapper around the gate level design.

vUse for-loops only for bit-wise operations that can only be described one bit at a time.



Combinational vs. Sequential BlocksCombinational vs. Sequential BlocksvUse separate always@ processes for

sequential logic and combinational logic.vThere is a sequential optimization process in DC.

vCombinational blockvUse blocking (=) assignmentsvMinimize signals required in sensitivity listvAssignment should be applied in topological order

vSequential blockvUse non-blocking (



Function, Conditional StatementsFunction, Conditional Statementsv Use function to model combinational logic when

possible, instead of repeating the same sections of code.

v Know whether you have prioritized or parallel condition.v Prioritized: if-else, parallel: case

v Completely specify all branches of all conditional statements.v If you completely specify the case statement (or use default),

DC will recognize the case is fully specified and parallel.



Coding for FSMCoding for FSMv Partition FSM and non-FSM logicv Prefer Moore (PO is PI-independent) to Mealy (PO is

PI-dependent)v Prefer Moore with state-outputs as POsv 3-always paradigmv One for sequential logicv One for next-state logicv One for PO logic (if required)

v Use parameters to define the state namesv Assign a default (reset) state



PortabilityPortabilityvDo not use hard-coded numbersvAvoid embedded synthesis scriptsvUse technology-independent librariesvAvoid instantiating gates



Clocks and ResetsClocks and Resetsv Simple clocking is easier to understand, analyze, and

maintainv The preferred clocking structure is a single global clock and

positive edge-triggered flops.v Avoid using both edges of the clockv Duty-cycle sensitivev Difficult DFT process

v Don’t buffer clock and reset networksv Should be handled during physical synthesis later

v Avoid gated clocksv Clock gating circuits tend to be technology specific and

timing dependent.



Clocks and ResetsClocks and Resetsv Avoid internally generated clocks and resetsv Limited testability

Q’

QD

Q’

QD

clock



Clocks and ResetsClocks and Resetsv Gated clock / internally generated clock designv If your design requires a gated clock, model it using

synchronous load registers.

Q’QD

Q’QD

Q’QD

submodule1

submodule2

submodule3

clk1

clk2

clk3

TOPClock Generationclock



Low PowerLow PowervClock gatingv50%~70% power consumed in clock network

reportedvGating the clock to an entire blockvGating the clock to a register

always @(posedge clk)if (en)

q



SynchronicitySynchronicityv Infer technology-independent registersv (positive) edge-triggered registers

v Avoid latches intentionallyv Except for small memory and FIFOv For low-power

v Avoid latches unintentionallyv Avoid incomplete assignment in case statementv Use default assignmentsv Avoid incomplete if-then-else chain

v Avoid combinational feedback loopsv STA and ATPG problem



Coding for SynthesisCoding for SynthesisvNo # delay statementsvAvoid full_case and parallel_casevEvil twinvPre-synthesis and post-synthesis simulation

mismatchvExplicitly declare wiresvAvoid glue logic at the top-levelvAvoid expression in port connections



PartitioningPartitioning

v Register all outputsvMake output drive strengths and input delay predictablev Ease time budgeting and constraints

R1clk

A B R2clk

C

R1clk

ABC R2clk

R1clk

R2clk

ABC

Bad

Better

Best



PartitioningPartitioningvKeep related logic togethervImprove synthesis quality

vPartition logic with different design goalsvAvoid asynchronous logicvTechnology dependentvMore difficult to ensure correct functionality and

timingvAs small as possible and isolation

vKeep sharable resources in the same block



PartitioningPartitioningv Avoid timing exceptionv Point-to-point, false path, multi-cycle path

v Keep sharable resources in the same block

muxmux

mux

AB

CD

AB

CD

control control



nLintnLintvnLint is a design rule checker that can help

hardware designers to create syntax and semantics correct HDL code.vnLint reads in HDL source code, analyzes it,

and outputs warnings and errors.vIncluding position and message.

vnLint checks against approximately 200 rules, which are RMM compliant.



Example: bad_conditional.vExample: bad_conditional.v

Incomplete conditional assignment

Incomplete sensitivity list

Error!!need “ ; ”

1

2

3



Use commandUse commandvnLint bad_conditional.v

1

23

1

2



No Error & WarningNo Error & Warning



GUIGUIvnLint –gui &



Import DesignImport Design



Edit FileEdit File



File OrganizerFile Organizer



Rule OrganizerRule Organizer



Lint Lint --> Run> Run



Fix errorFix error



Fix Warning 1Fix Warning 1



Fix Warning 2Fix Warning 2



Search RuleSearch RulevRight clock -> Search Rule



Show Source On Show Source On nTracenTracevTools -> Preferences



Show Source On Show Source On nTracenTrace



No Error & WarningNo Error & Warning

Documents

20050408 Coding Style - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_93second/2005ppt/20050408... · 2010. 7. 14. · nLint vnLintis a design rule checker that can help hardware